KR100710340B1 - Apparatus for driving Plasma Display Panel - Google Patents

Abstract

Disclosed is a driving device of a plasma display panel. The apparatus includes a charging unit for charging a sustain up voltage supplied from the sustain voltage source to a scan electrode in a sustain period, and a voltage having a level higher than the falling ramp pulse voltage by a level of the charged sustain up voltage in the scan period in the address period. And a scan bias voltage supply unit for supplying the power supply.

Description

Apparatus for driving plasma display panel

1 is a waveform diagram of typical signals for driving a PDP.

Fig. 2 is a circuit diagram of an embodiment of a drive device for a PDP according to the present invention.

3 and 4 are diagrams for describing an operation of the driving apparatus of the PDP shown in FIG. 2.

5 is a waveform diagram illustrating the operation of the scan bias voltage supply unit.

6 is a circuit diagram illustrating an actual implementation of the plasma display driving apparatus according to the present invention shown in FIG. 2.

FIG. 7 shows a waveform diagram of a signal generated by the plasma display driving apparatus according to the present invention shown in FIG. 6 and supplied to a scan electrode.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for driving a plasma display panel (hereinafter referred to as " PDP "). In particular, the present invention relates to a scan bias voltage during an address period while driving an AC surface discharge PDP. Or a drive device of a PDP which eliminates the need for a DC / DC converter to generate a scan high voltage.

In the conventional AC type surface discharge PDP, time division driving is performed by dividing one frame into several subfields having different emission counts in order to realize gray level of an image. At this time, each subfield is divided into a reset period for initializing the entire screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gradation according to the number of discharges. Lose.

FIG. 1 is a waveform diagram of general signals for driving a PDP, and illustrates a signal Y supplied to a scan electrode, a signal X supplied to an address electrode, and a signal Z supplied to a sustain electrode.

Referring to FIG. 1, each subfield is divided into a reset period, an address period, and a sustain period. In the set-up period of the reset period, the rising ramp pulse Ramp-up is simultaneously applied to all the scan electrodes Y. This rising ramp pulse causes a slight discharge in the cells of the entire screen to generate wall charges in the cells. Ramp-down falling from the positive voltage lower than the peak voltage of the ramp-up ramp in the set-down period of the reset period after the ramp-up ramp-up is supplied. Is simultaneously applied to the scan electrodes (Y). Ramp-down generates a weak erase discharge in the cells, thereby eliminating unnecessary charges among the wall charges and the space charges generated by the setup discharge, and the wall charges required for the address discharge in the cells of the entire screen. To remain uniformly.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the negative scan pulse and the positive data pulse and the wall voltage generated in the reset period are added, address discharge is generated in the cells to which the data pulse is applied.

In the sustain period, the sustain pulse Su is applied to the scan electrodes Y and the sustain electrodes Z alternately. The high level of the sustain pulse Sus is the sustain voltage Vs, and the low level of the sustain pulse Sus may be the reference potential. However, in the half sustain mode, the high level of the sustain pulse (Sus) is half the value (Vs / 2) of the positive (+) of the sustain voltage (Vs), and the low level of the sustain pulse (Sus) is sustain. It can be the negative half value (-Vs / 2) of the voltage Vs.

As mentioned above, the conventional PDP driving method requires a DC / DC converter to generate a corresponding electric potential of each signal Y, Z or X in each period. For example, in the case of the signal Y, the rising ramp pulse voltage V1 used in the reset period is generated, and the scan bias voltage V3 and the negative scan voltage (or falling ramp pulse voltage) used in the address period are generated. A DC / DC converter is needed to produce V5. In addition, a DC / DC converter is required to generate the sustain up voltage V2 and the sustain down voltage V4 used in the sustain period. Here, in general, the sustain up voltage V2 corresponds to the sustain voltage Vs, and the sustain down voltage V4 corresponds to the reference potential Vref. Alternatively, in the half sustain mode, the sustain up voltage V2 may be Vs / 2, and the sustain down voltage V4 may be -Vs / 2.

As described above, since the potentials required in each period are all different, a DC / DC converter for converting from a DC voltage having a predetermined level to another DC voltage having a corresponding level is required.

As a result, the conventional plasma display panel driving apparatus requires a separate DC / DC converter in order to generate the scan bias voltage V3 used in the address period. In addition, since a constant voltage level ΔV is required between the negative scan voltage V5 and the scan bias voltage V3, the level of the scan bias voltage V3 may change as the level of the negative scan voltage V5 changes. There is also a problem that is required.

An object of the present invention is to provide a plasma display panel driving apparatus capable of generating a voltage used in an address period without the help of a separate DC / DC converter.

In order to achieve the above object, the driving device of the plasma display panel according to the present invention includes a charging unit for charging a sustain up voltage supplied to the scan electrode in the sustain period from the sustain voltage source, and a charged sustain up voltage rather than a falling ramp pulse voltage. And a scan bias voltage supply unit supplying a voltage having a level as high as a level in the address period as a scan bias voltage.
In this case, the driving apparatus of the plasma display panel operates in the half sustain mode in the sustain period.
In this case, the charging unit is provided between a capacitor for charging a sustain up voltage supplied from the sustain up voltage source, the sustain up voltage source and the capacitor, and a first switch turned on in the sustain period, and provided between the capacitor and the ground. And a first diode having an anode and a cathode.
In addition, the scan bias voltage supply unit is provided in series between the falling ramp pulse voltage source and the charging unit, and scans the second and third switches and the contacts of the capacitor and the first switch and are turned on in the address period. And a second diode having an anode and a cathode connected between the scan bias voltages supplied to the electrodes.

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Hereinafter, a configuration and an operation of a driving apparatus of a plasma display panel according to the present invention will be described with reference to the accompanying drawings.

Fig. 2 is a circuit diagram of an embodiment of a drive device for a PDP according to the present invention.

The driving circuit of the PDP shown in FIG. 2 includes an energy recovery unit 10, a rising ramp pulse supply unit 12, a charging unit 14, a scan bias voltage supply unit 16, a falling ramp pulse supply unit 18, and a scan driver 20. ), Switches (PASS_BOTTOM and PASS_TOP).

Prior to describing the operation of the charging unit 14 and the scan bias voltage supply unit 16 according to the present invention, the peripheral circuits of the charging unit 14 and the scan bias voltage supply unit 16 will be described. In order to facilitate understanding of the present invention, the energy recovery unit 10, the rising ramp pulse supply unit 12, the falling ramp pulse supply unit 18, and the scan driver 20 of the driving device of the PDP include a circuit as shown in FIG. 2. Although described as having, the present invention is not limited thereto.

First, the energy recovery unit 10 shown in FIG. 2 includes the switches ER_UP and ER_DWON connected in parallel between the reference potential and the inductor L, and a positive sustain voltage (+) to the panel capacitor Cp. A switch SUS_UP for supplying Vs / 2) and a switch SUS_DOWN for supplying a negative sustain voltage (-Vs / 2) to the panel capacitor Cp. Diodes D1 and D2 for limiting reverse current are connected in series between the switches ER_UP and ER_DOWN. The panel capacitor Cp equivalently represents the capacitance of the panel.

In the set-up period, the switch SET_UP of the rising ramp pulse supply unit 12 is turned on so that the voltage Vset_up of the rising ramp pulse supply is supplied to the scan electrode through the scan driver 20. To this end, the rising ramp pulse supply 12 is composed of a diode D3, a capacitor C1, a switch SET_UP and a variable resistor R1.

In the set down period, the switch SET_DN of the falling ramp pulse supply unit 18 is turned on so that the voltage V_y of the falling ramp pulse is supplied to the scan electrode. To this end, the falling ramp pulse supply unit 18 is composed of a switch SET_DN and a variable resistor R2. Here, V_y may be a negative value or a positive value.

In the sustain period, the switches SUS_UP and SUS_DOWN are alternately turned on, so that a sustain pulse su is alternately applied to the scan electrodes and the sustain electrodes. In the half sustain mode as shown in Fig. 2, the high level of the sustain pulse sus becomes the half value Vs / 2 of the positive (+) of the sustain voltage Vs, and the low level of the sustain pulse su. This negative voltage (-) of the sustain voltage Vs becomes (-Vs / 2).

3 and 4 are diagrams for describing an operation of the driving apparatus of the PDP shown in FIG. 2.

Referring to FIG. 3, the charging unit 14 charges the sustain up voltage (+ Vs / 2) supplied to the scan electrode in the sustain period. To this end, the charging unit 14 may be implemented with a switch SCAN, a capacitor C2, and a diode D4. Here, the capacitor C2 charges the sustain up voltage (+ Vs / 2), and the switch SCAN is installed between the sustain up voltage source (+ Vs / 2) and the capacitor C2 and turned on in the sustain period. Diode D4 has an anode and a cathode provided between capacitor C2 and ground, which is a reference potential. Through this configuration, the switches SUS_UP, PASS_BOTTOM, and SCAN are turned on and the switches SUS_DOWN, PASS_TOP, and S1 are turned off in the sustain period. Therefore, a current path leading to the ground through the switches SUS_UP, PASS_BOTTOM and SCAN through the capacitor C2 and the diode D4 to the ground is formed in the direction of the arrow 30 so that the sustain up voltage (+ Vs / 2) becomes the capacitor ( C2) can be charged.

5 is a waveform diagram illustrating the operation of the scan bias voltage supply unit 16.

4 and 5, the scan bias voltage supply unit 16 has a level higher than that of the falling ramp pulse voltage V_y by a level of the sustain up voltage (+ Vs / 2), and the voltage is equal to the following equation (1). Is supplied to the scan electrode through the scan driver 20 as a scan bias voltage Vscb.

To this end, the scan bias voltage supply unit 16 may be implemented with switches S1 and S2 and a diode D5. The switches S1 and S2 are provided in series between the falling ramp pulse voltage source V_y and the charging unit 14 and are turned on in the address period. The diode D5 has a positive electrode and a negative electrode connected between the contact point between the capacitor C2 and the switch SCAN and the scan bias voltage supplied to the scan electrode, respectively.

Through the above-described configuration, the switches S2, S1, and S3 are turned on and the switches SET_DN, PASS_TOP, and S4 are turned off in the address period. Thus, a current path 32 is formed leading to the scan electrode via the switches S2 and S1, the capacitor C2, the diode D5 and the switch S3. Therefore, the scan bias voltage in which the voltage (+ Vs / 2) charged in the capacitor C2 starts to discharge as the switch S1 is turned on and floats against the falling ramp pulse voltage V_y is shown in FIG. 5. Can be generated as shown. In FIG. 5, it can be seen that the voltage difference between the scan bias voltage Vscb and the falling ramp pulse voltage V_y is maintained at ΔV.

In FIG. 2, in the driving apparatus of the conventional PDP, instead of the switch SCAN connected to the switch PASS_BOTTOM to supply the scan bias voltage Vscb, the scan voltage Vsc is supplied from the scan voltage source Vsc. Instead of providing the capacitor C2 and the diode D4 between the fields SCAN and S1, a switch is provided, and the diode D5 is not provided. In this case, a current needs to flow toward the scan driver 20 in order to perform a scan operation. In order to generate a scan voltage Vsc necessary therein, a separate DC / DC converter must be provided. However, as shown in FIG. 2, instead of providing the scan voltage source Vsc or generating the scan voltage Vsc, when the switch SCAN is connected to the switch PASS_BOTTOM and the charging unit 14 is provided, a separate unit is provided. The scan bias voltage Vscb as shown in FIG. 5 can be supplied without a DC / DC converter.

FIG. 6 is a circuit diagram illustrating an actual implementation of the plasma display driving apparatus according to the present invention illustrated in FIG. 2, and the sustain voltage Vs is assumed to be 100 volts.

FIG. 7 shows a waveform diagram of the signal Y generated by the plasma display driving apparatus according to the present invention shown in FIG. 6 and supplied to the scan electrode.

Referring to FIG. 7, it can be seen that the scan bias voltage Vscb 50 floats by ΔV relative to V_y.

In the PDP driving apparatus according to the present invention, each switch (ER_UP, ER_DOWN, SUS_UP, SUS_DOWN, SET_UP, PASS_BOTTOM, SCAN, PASS_TOP, S1, S2, SET_DN, S3 and S4) is a metal oxide film as shown in FIG. Although it may be implemented as a semiconductor oxide field effect transistor (MOSFET), the present invention is not limited thereto.

As described above, the driving apparatus of the plasma display panel according to the present invention can reduce the cost of the circuit by removing the DC power supply (Vsc) required to generate the scan bias voltage (Vscb) in the address period, the scan bias Unlike the conventional PDP driving device which holds the voltage only at a specific potential (-Vs / 2 or GND), the scan bias voltage Vscb can be held at a specific voltage (ΔV) compared to the voltage V_y of the falling ramp pulse. Since the degree of freedom is high, the degree of freedom of waveforms according to actual driving conditions can be improved.

Claims (4)

A charging unit configured to charge a sustain up voltage supplied from the sustain voltage source to the scan electrode in the sustain period; And And a scan bias voltage supply unit supplying a voltage having a level higher than the falling ramp pulse voltage by the level of the charged sustain up voltage as a scan bias voltage in an address period. The plasma display panel driving apparatus of claim 1, wherein the driving apparatus of the plasma display panel operates in a half sustain mode in the sustain period. The method of claim 1, wherein the charging unit A capacitor charging the sustain up voltage supplied from the sustain up voltage source; A first switch disposed between the sustain up voltage source and the capacitor and turned on in the sustain period; And a first diode having an anode and a cathode provided between the capacitor and the ground. The method of claim 3, wherein the scan bias voltage supply unit Second and third switches provided in series between the falling ramp pulse voltage source and the charging unit and turned on in the address period; And And a second diode having a positive electrode and a negative electrode connected between the capacitor and the contact point of the first switch and the scan bias voltage supplied to the scan electrode.

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