KR100570767B1 - Plasma display device driving method thereof - Google Patents

Abstract

The present invention relates to a plasma display device. According to the present invention, a transistor for applying sustain discharge voltage and a rising reset voltage and a non-scanning voltage is connected to an upper transistor of a scan IC, and a transistor for applying a falling reset voltage and a scan voltage is connected to a lower part of a scan IC, and The switch above the scan IC is turned off when applying the falling reset voltage and the scan voltage, which are the voltage of. In this way, the positive voltage supply and the negative voltage supply are shut off, which eliminates the high-capacity switch that forms on the main path to prevent short-circuit currents, and minimizes circuit impedance to reduce distortion in the sustain voltage waveform. Can be.

PDP, Scan IC, High Capacity Switch

Description

Plasma display and driving method {PLASMA DISPLAY DEVICE DRIVING METHOD THEREOF}

1 is a circuit diagram of a Y electrode driver according to the prior art.

2 is a schematic diagram of a plasma display device according to an exemplary embodiment of the present invention.

3 is a circuit diagram of a Y electrode driver according to an exemplary embodiment of the present invention.

4 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention.

5A to 5B are diagrams showing current paths in respective modes of the Y electrode driver according to the exemplary embodiment of the present invention.

The present invention relates to a plasma display device, and more particularly to a driving circuit of the plasma display device.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display device is classified into a direct current type and an alternating current type according to the shape of a driving voltage waveform to be applied and the structure of a discharge cell.

In the AC plasma display panel, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

In general, the driving method of the AC plasma display panel includes a reset period, an addressing period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell. The addressing period is an address voltage for a cell (addressed cell) turned on to select a cell that is turned on and a cell that is not turned on in a panel. It is a period of time to perform the operation of accumulating wall charge by applying a. The sustain period is a period in which a discharge for actually displaying an image on the addressed cell is applied by applying a sustain discharge voltage pulse.

1 shows a Y electrode driving circuit according to the prior art.

As shown in FIG. 1, the conventional Y electrode driving circuit includes a reset driver 10, a scan driver 20, and a sustain driver 30.

The reset driver 10 may include a rising ramp switch Yrr for generating a reset waveform up to a rising voltage Vset in a reset period and a falling ramp switch Yfr for generating a reset waveform falling down to a voltage Vnf, and a power source ( Vset, Vnf), a capacitor Cset operating from a floating power supply, and a switch Ypp, Ynp.

The scan driver 20 generates a scan pulse in the address period, the capacitor Csc and the switch YscL that store the powers VscH and VscL and the voltages VscH-VscL that supply the voltage applied to the scan electrode that is not selected. And a plurality of scan driver ICs connected to the respective Y electrodes. Each scan driver IC includes a switch SCH for supplying the high voltage VscH to the panel capacitor Cp and a switch SCL for supplying the low voltage VscL transferred from the switch YscL.

The sustain driver 30 generates a sustain discharge pulse in the sustain period, and includes a capacitor Ce, a switch Yr, Yf, a diode Dr, Df, an inductor L, and a power supply Vs constituting the reactive power recovery circuit. ) And a switch (Ys, Yg) connected between the ground and ground (GND) to supply a voltage (Vs or 0V) of the panel capacitor.

In the conventional driving circuit, when the rising reset waveform is applied to the Y electrode in the reset period, the switch Ypp is turned off to prevent the sustain driving unit 30 from applying a voltage higher than the sustain discharge voltage Vs. By blocking the current path connected to the Y electrode at 323, a voltage higher than the voltage Vs is applied to the Y electrode through the capacitor Cset and the switch Yrr. In addition, when the falling reset waveform is applied to the Y electrode to the negative voltage Vnf in the reset section and when the negative voltage VscL is applied to the selected discharge cell in the scan section, the switch Ynp is turned off to switch Yg. , Ypp) prevents the potential from being clamped to ground voltage.

However, since the switch (Ynp) is located on the main path path to which the sustain discharge voltage is applied, the switch (Ynp) must withstand both the large current during the sustain discharge and the high voltage applied to the reset section, and thus an expensive device having a high breakdown voltage should be used. In addition, since the switch Ynp is connected to the main path, the discharge impedance may be affected during the sustain discharge due to the pattern impedance.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device with a switch on a main path and a driving method thereof.

According to an aspect of the present invention, a plasma display device includes a panel including a plurality of address electrodes arranged in a column direction, a scan electrode and a sustain electrode arranged in a row direction, and a voltage supplied to the scan electrodes. A scan driver for

The scan driver,

A first transistor and a second transistor having a contact electrically connected to the scan electrode, supplying a scan voltage to the selected scan electrode through the second transistor, and a non-scan voltage to the unselected scan electrode through the first transistor. A first driver for applying a sustain discharge pulse alternately having a first voltage and a second voltage lower than the first voltage to the scan electrode through the selection circuit for supplying a voltage to the scan electrode through the first transistor of the selection circuit; And a second driver configured to apply a voltage lower than the second voltage to the scan electrode through the second transistor of the circuit.

The first driving unit,

A rising reset voltage generation unit supplying a gradually increasing voltage during a reset period, a sustain voltage generation unit supplying the sustain discharge pulse during a sustain period, and a non-scan voltage supply unit supplying the non-scan voltage during an address period,

The second driver includes a scan voltage supply unit configured to supply the scan voltage lower than the second voltage during the address period.

In this case, the sustain voltage generator is connected in series between a first power supply for supplying the first voltage and a second power supply for supplying the second voltage, and a third transistor having a contact electrically connected to one end of the first transistor. And a fourth transistor,

The rising reset voltage generator includes a first capacitor having one end connected to a contact point of the third transistor and the fourth transistor, a fifth transistor electrically connected to the other end of the first capacitor and one end of the first transistor. ,

The non-scan voltage supply unit includes a sixth transistor electrically connected between a third power supply for supplying the non-scan voltage and the first transistor,

The scan voltage supply unit includes a seventh transistor YscL electrically connected between a fourth power supply for supplying the scan voltage and the second transistor.

The sustain voltage generation unit turns on the first transistor and the third transistor or the first transistor and the fourth transistor to apply the first voltage or the second voltage to the scan electrode.

The rising reset voltage generation unit turns on the first transistor and the fifth transistor to apply a reset voltage rising from the third voltage to the fourth voltage to the scan electrode.

A driving method of a plasma display device according to an aspect of the present invention is a driving method of a plasma display device including a plurality of first electrodes and a second electrode.

Gradually increasing the voltage of the first electrode to a first voltage through a first path; gradually decreasing the voltage of the first electrode to a second voltage through a second path; Sequentially applying a scan voltage to the first electrode through the first electrode, and applying a non-scan voltage to the first electrode to which the scan voltage is not applied through the first path and through the first path. Applying a voltage for sustain discharge to the electrode.

In this case, the plasma display device includes a selection circuit including a first transistor SCH and a second transistor SCL whose contacts are electrically connected to the first electrode.

The first path is formed by a first transistor, and the second path is formed by the second transistor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a method of driving a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

2 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a plasma display device according to an exemplary embodiment of the present invention includes a display panel 100, an address driver 200, a Y electrode driver 320, an X electrode driver 340, and a controller 400. do.

The display panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, first electrodes Y1 to Yn (hereinafter referred to as Y electrodes), and second electrodes X1 arranged in the row direction. ˜Xn) (hereinafter referred to as X electrode).

The address driver 200 receives an address driving control signal SA from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The Y electrode driver 320 and the X electrode driver 340 receive the Y electrode driving signal SY and the X electrode driving signal SX from the controller 200 and apply them to the X electrode and the Y electrode, respectively.

The control unit 400 receives an image signal from the outside, generates an address driving control signal SA, a Y electrode driving signal SY, and an X electrode driving signal SX, respectively, and generates an address driving unit 200 and a Y electrode driving unit ( 320 and the X electrode driver 340.

3 is a detailed circuit diagram of the Y electrode driver 320 according to an embodiment of the present invention.

As shown in FIG. 3, the Y electrode driver 320 according to an exemplary embodiment of the present invention uses the rising reset / non-scan driver 321, the down reset / scan driver 322, the holding driver 323, and the scan IC. Include.

The rising reset / non-scanning driving unit 321 is connected to a power supply Vset-Vs and connected to a rising ramp switch Yrr and a power supply Vset-Vs for applying a waveform that gradually rises to the Y electrode in the reset period. And a capacitor Cset and a switch Ypp that charge Vset-Vs. When the switch Yrr is turned on, the switch Ypp is turned off to cut off the main path, thereby applying a waveform rising to the voltage Vset to the Y electrode. In addition, the rising reset / non-scan driver 321 includes a switch YscH connected to a power supply VscH for supplying a negative voltage and applying the non-scan voltage VscH to a Y electrode not selected in the address period. .

The falling reset / scan driver 322 is connected to a power supply Vnf supplying a negative voltage, and a falling ramp switch Yfr for applying a waveform that gradually descends to the Y electrode in a reset period, and a power supply for supplying a negative voltage. The switch YscL is connected to the VscL and supplies a scan voltage VscL applied to the selected Y electrode in the address period.

The sustain driver 323 generates a sustain discharge pulse in the sustain period, and includes a capacitor Ce, a switch Yr, Yf, a diode Dr, Df, an inductor L, and a power supply Vs constituting the reactive power recovery circuit. ) Is connected between the ground and ground (GND) and supplies a switch (Ys) and a switch (Yg) for supplying voltages Vs and 0V of the panel capacitor, respectively.

The scan IC is connected to a plurality of Y electrodes and includes a plurality of selection circuits including a switch SCH for supplying the non-scan voltage VscH to the panel capacitor Cp and a switch SCL for supplying the scan voltage VscL. Is made of.

Here, the panel capacitor Cp equivalently represents the capacitance component between the X electrode and the Y electrode. Also, for convenience, the X electrode of the panel capacitor Cp is displayed as being connected to the ground terminal, but the X electrode driver 340 is actually connected to the X electrode. In FIG. 3, each of the switches is represented by an n-channel MOSFET, and each switch may include a body diode.

In addition, according to the exemplary embodiment of the present invention, the rising reset / non-scanning driver 321 and the holding driver 323 are connected to the high side switch SCH of the scan IC, and the falling reset / scan driver 322 is a low value of the scan IC. It is connected to the side switch (SCL). Therefore, even when the switch Ynp is not added to the main path as in the prior art illustrated in FIG. 1, when the negative voltage is applied to the Y electrode, the potential of the Y electrode is not clamped to the ground voltage.

Next, the driving method of the driving circuit according to the exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5.

4 is a driving waveform diagram of a driving circuit according to an embodiment of the present invention, Figure 5 shows the flow of current in each section.

First, it is assumed that the voltage Vset-Vs is charged in the capacitor Cset. The charging of such a voltage can be easily performed by turning on the switch Yg of the sustain discharge unit 323.

Next, the switch SCH and Ys are turned on to turn off the switch Ypp and turn on the switch Yrr while the voltage Vs is applied to the panel capacitor Cp. Then, the voltage Vs is supplied to the first terminal of the capacitor Cset connected to the switch Ys, and the voltage Vset-Vs is precharged to the capacitor Cset, so that the voltage Vs is connected to the power supply Vset-Vs. The voltage at the second terminal of the capacitor Cset becomes the voltage Vset. Accordingly, the voltage Vset of the second terminal of the capacitor Cset is supplied to the Y electrode of the panel capacitor Cp through the switch Yrr and the high side switch SCH of the scan IC. At this time, since the switch Yrr is a ramp switch for flowing a constant current between the source and the drain, a voltage gradually rising from the voltage Vs to the voltage Vset is applied to the Y electrode of the capacitor Cp (FIG. 5A). See the path ①). In addition, the low side switch SCL of the scan IC is turned off while the switch Yrr is turned on.

Next, the switch Yrr is turned off while the switches SCH and Ys are turned on. Then, the Y electrode voltage decreases to the voltage Vs (see path ② of FIG. 5A).

Then, the switch Yfr is turned on while the switches SCH and Ys are turned off and the switch SCL is turned on. Then, the voltage of the Y electrode of the panel capacitor Cp gradually decreases from the voltage Vs to the negative voltage Vnf (see path ③ in FIG. 5A). In addition, while the voltage of the Y electrode falls to the negative voltage Vnf, the switch SCH is turned off so that the holding driver 323 and the falling reset / scan driver 322 are separated from each other. The voltage at the Y electrode is not clamped to ground voltage even if there is no separate switch that blocks the flow.

Next, in the address period, the switches Yfr and SCL are turned off and the switches VscH and the switches SCH of all the selection circuits are turned on to apply the non-scanning voltage VscH to all the Y electrodes (path ④ in FIG. 5B). In this state, the scan voltage VscL is sequentially applied to the Y electrode through the operation of turning on the switch SCL of each selection circuit connected to the Y electrode (see path ⑤ in FIG. 5B). At this time, the switch VscH and the switch VscL may remain turned on during the address period, and when the switch SCH is turned on, the non-scanning voltage VscH is applied to the Y electrode through the switch VscH. Is applied, and the scan voltage VscL is applied to the Y electrode through the switch VscL when the switch SCL is turned on.

In addition, when the switch SCL is turned on even in the address period, the switch SCH is turned off and the sustain driver 323 and the falling reset / scan driver 322 are separated, so that the voltage of the Y electrode is not clamped to the ground voltage.

Thereafter, in the sustain period, the switch SCL is turned off and the switch Ys and the switch Yg are alternately turned on while the sustain discharge voltage is applied to the Y electrode. In addition, since the operation of the power recovery circuit is general, description thereof is omitted.

As described above, according to the exemplary embodiment of the present invention, the falling reset / scanning supplying the negative voltage to the rising reset / non-scanning driving unit 321 and the sustain driving unit 323 supplying the high voltage through the switches SCH and SCL of the scan IC. By separating the driver 322, the switch Ynp may be removed to prevent the negative voltage from being clamped to the ground voltage on the main path.

Further, in the embodiment of the present invention, the falling reset final voltage Vnf and the scan voltage VscL are set differently, but the number of power sources can be reduced by setting the falling reset final voltage to be the same as the scan voltage.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

As described above, according to the present invention, the rising reset / non-scan driver 321 and the sustain driver 323 for supplying a high voltage are connected to the high side switch SCH of the scan IC, and the falling reset for supplying a negative voltage. / Scan drive 322 to the low side switch (SCL) of the scan IC to separate them. In this way, since the switch Ynp on the main path can be removed, the distortion of the sustain voltage waveform can be reduced by minimizing the circuit impedance.

In addition, according to the present invention, the number of circuit components is reduced and the size of the circuit board is reduced because the main switch formed by a plurality of FETs connected in parallel on the main path is removed.

Claims (9)

A panel including a plurality of address electrodes arranged in a column direction, a scan electrode and a sustain electrode arranged in a row direction; A scan driver for supplying a voltage to the scan electrode; The scan driver, A first transistor and a second transistor having a contact electrically connected to the scan electrode, supplying a scan voltage to the selected scan electrode through the second transistor, and a non-scan voltage to the unselected scan electrode through the first transistor. A selection circuit for supplying; A first driver configured to apply a sustain discharge pulse alternately having a first voltage and a second voltage lower than the first voltage to the scan electrode through the first transistor of the selection circuit; And A second driver configured to apply a voltage lower than the second voltage to the scan electrode through the second transistor of the selection circuit; Plasma display device. The method of claim 1, The first driving unit, A rising reset voltage generation unit supplying a gradually increasing voltage during the reset period; A sustain voltage generator supplying the sustain discharge pulse during a sustain period; And A non-scan voltage supply unit configured to supply the non-scan voltage during an address period, The second driver includes a scan voltage supply unit configured to supply the scan voltage lower than the second voltage during the address period. Plasma display device. The method of claim 2, The sustain voltage generator may include a third transistor connected in series between a first power supply for supplying the first voltage and a second power supply for supplying the second voltage, and a third transistor having a contact electrically connected to one end of the first transistor. 4 contains transistors, The rising reset voltage generator includes a first capacitor having one end connected to a contact point of the third transistor and the fourth transistor, a fifth transistor electrically connected to the other end of the first capacitor and one end of the first transistor. , The non-scan voltage supply unit includes a sixth transistor electrically connected between a third power supply for supplying the non-scan voltage and the first transistor, The scan voltage supply unit includes a seventh transistor YscL electrically connected between a fourth power supply for supplying the scan voltage and the second transistor. Plasma display device. The method of claim 3, The sustain voltage generation unit turns on the first transistor and the third transistor or the first transistor and the fourth transistor to apply the first voltage or the second voltage to the scan electrode. The rising reset voltage generation unit turns on the first transistor and the fifth transistor to apply a reset voltage rising from the third voltage to a fourth voltage to the scan electrode. Plasma display device. The method of claim 2, The scan driver, And an eighth transistor electrically connected between a fifth power supply for supplying a fifth voltage lower than the second voltage and the second transistor, and a drop for applying a reset voltage falling to the fifth voltage to the scan electrode. Reset voltage supply Plasma display device further comprising. The method according to any one of claims 1 to 5, And the second voltage is a ground voltage. The method of claim 5, And the fifth voltage has the same magnitude as the scan voltage. In the driving method of a plasma display device including a plurality of first electrodes and a second electrode, Gradually raising the voltage of the first electrode to a first voltage through a first path; Gradually lowering the voltage of the first electrode to a second voltage through a second path; Sequentially applying a scan voltage to the first electrode through the second path, and applying a non-scan voltage to the first electrode to which the scan voltage is not applied through the first path; And Applying a voltage for sustain discharge to the first electrode through the first path; Method of driving a plasma display device comprising a. The method of claim 8, The plasma display device includes a selection circuit including a first transistor SCH and a second transistor SCL whose contacts are electrically connected to the first electrode. The first path is formed by a first transistor, and the second path is formed by the second transistor. A method of driving a plasma display device.

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