KR100670151B1 - Plasma display and driving apparatus thereof - Google Patents

Abstract

A plasma display device and a driving method thereof are provided to reduce manufacturing cost of the plasma display device by reducing the breakdown voltage of a switch connected between positive and negative voltage sources for a scan electrode. A driving circuit for a plasma display device includes a sustain driver(410), a reset driver(420), and a scan driver(430). The sustain driver includes a power recovery unit(411) and transistors(Ys,Yg). The transistor(Ys) is connected between a voltage source(Vs) and a Y electrode of a panel capacitor(Cp), and applies the Vs voltage on the Y electrode, while the transistor(Yg) applies 0 voltage on the Y electrode. A first terminal of a capacitor(Cer) is connected to a junction between the transistors. The capacitor(Cer) is charged to a voltage, which corresponds to the middle point between the Vs and 0 voltages. A source of a transistor(Yr) is connected to a second terminal of the inductor(L). A drain of the transistor(Yr) is connected to a first terminal of the capacitor(Cer). A drain of a transistor(Yf) is connected to a second terminal of the inductor. A source of the transistor(Yf) is connected to a first terminal of the capacitor(Cer).

Description

Plasma display and its driving device {PLASMA DISPLAY AND DRIVING APPARATUS THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a driving circuit of the scan driver 400 for generating the driving waveform of FIG. 2.

4A and 4B are diagrams illustrating an operation process for generating a driving waveform in a reset period among the driving waveforms of FIG. 2, respectively.

The present invention relates to a plasma display device and a driving device thereof.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, a plurality of discharge cells are arranged in a matrix form.

The display panel of the plasma display device is driven by dividing one frame into a plurality of subfields having respective weights. Each subfield includes a reset period, an address period, and a sustain period. The reset period is a period for initializing the discharge cells in order to stably perform the address discharge. The address period is a period for selecting cells that are turned on and cells that are not turned on in the display panel. The sustain period is a period in which sustain discharge for actually displaying an image is performed for the cells to be turned on.

In order to initialize the discharge cells, in the reset period, the voltage of the scan electrode is gradually decreased to cause weak discharge in the discharge cells to initialize the discharge cells. In this case, the voltage of the scan electrode is generally reduced from a positive voltage (Vs voltage) to a negative voltage (Vnf voltage). In this case, a switch connected to a power supply for supplying a Vs voltage and a power supply for supplying a Vnf voltage and The voltage across the connected switch between the connected switches is the voltage (Vs-Vnf). Therefore, a switch having a breakdown voltage of (Vs-Vnf) or higher must be used, and a switch having a high breakdown voltage has a high cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display device and a driving device thereof capable of reducing the breakdown voltage of a switch.

According to an aspect of the present invention, a driving apparatus of a plasma display device including a plurality of first electrodes and a plurality of second electrodes performing a display operation together with the plurality of first electrodes is provided. The driving device is a first switch connected between the plurality of first electrodes and a first power supply for supplying a first voltage, the first switch operative to gradually decrease the voltages of the plurality of first electrodes, the plurality of firsts. A second switch having a first end connected to an electrode and a contact of the first switch, a second power supply for supplying a second voltage and a third switch connected between the second end of the second switch, and the first switch And a fourth switch connected between a third power supply for supplying a third voltage lower than two voltages, and a second end of the second switch, wherein the third switch is turned on in a reset period to thereby turn on the plurality of first electrodes. After the second voltage is applied to the first switch, the first switch is turned on to gradually decrease voltages of the plurality of first electrodes, and during the period of time during which the voltages of the plurality of first electrodes gradually decrease. 4th The turn-on value.

According to another feature of the present invention, a plurality of first electrodes, a plurality of second electrodes performing a display operation together with the plurality of first electrodes, and a plurality of first electrodes, respectively, are respectively connected to a first end. And a plurality of selection circuits having a second stage and applying the voltage of the first stage or the voltage of the second stage to a corresponding first electrode, the second stage of supplying the second stage and the first voltage of the plurality of selection circuits. A first switch connected between a power supply and operable to gradually decrease voltages of the plurality of first electrodes; a second end of the plurality of selection circuits connected to a second end of the plurality of selection circuits and a first end of the first switch; A switch, a third switch connected between a second power supply for supplying a third voltage and a second end of the second switch, an inductor having a first end connected to a second end of the second switch, and the third Charging the fourth voltage lower than the voltage The plasma display device including a capacitor, and a fourth switch connected between the second stage and the capacitor of the inductor is provided. During the reset period, the plasma display device turns on the third switch to apply the third voltage to the plurality of first electrodes through the second end of the plurality of selection circuits, and then turns on the first switch to turn the third switch on. The voltages of the plurality of first electrodes are gradually decreased, and the fourth switch is turned on for a period of time during which the voltages of the plurality of first electrodes are gradually reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to be "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

In the present invention, the wall charge refers to a charge formed close to each electrode on the cell wall (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as “formed”, “accumulated” or “stacked” on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

Now, a plasma display device and a driving device thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a scan electrode driver 400, and a sustain electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes (hereinafter referred to as “A electrodes”) A1 to Am extending in the column direction, and a plurality of sustain electrodes extending in pairs to each other in the row direction (hereinafter, “X”). Electrodes ”(X1 to Xn) and scan electrodes (hereinafter referred to as“ Y electrodes ”) (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and the X electrode and the Y electrode perform a display operation for displaying an image in the sustain period. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 12. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an A electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each A electrode.

The scan electrode driver 400 receives a Y electrode driving control signal from the controller 200 and applies a driving voltage to the Y electrode.

The sustain electrode driver 500 receives the X electrode driving control signal from the controller 200 and applies a driving voltage to the X electrode.

Next, a driving waveform of the plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2. In the following description, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described.

2 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention.

As shown in Fig. 2, in the rising period of the reset period, the voltage of the Y electrode gradually increases from the Vs voltage to the Vset voltage while the X electrode is held at the reference voltage (0 V in Fig. 2). In FIG. 2, the voltage of the Y electrode is shown to increase in the form of a lamp. Then, while the voltage of the Y electrode is increased, a weak discharge (hereinafter referred to as “weak discharge”) occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is applied to the Y electrode. And a positive wall charge is formed on the X and A electrodes.

In the falling period of the reset period, the voltage of the Y electrode gradually decreases from the Vs voltage to the Vnf voltage while the X electrode is maintained at the Ve voltage. Then, while the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode. Is erased. In general, the magnitude of the (Vnf-Ve) voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period.

In the address period, in order to select a discharge cell to be turned on, while a Ve voltage is applied to the X electrode, a scan pulse having a VscL voltage is sequentially applied to the plurality of Y electrodes. At this time, the Va voltage is applied to the A electrode passing through the discharge cell to be selected from the plurality of discharge cells formed by the Y electrode and the X electrode to which the VscL voltage is applied. Then, an address discharge occurs between the A electrode to which the Va voltage is applied and the Y electrode to which the VscL voltage is applied, and the Y electrode to which the VscL voltage is applied, and the X electrode to which the Ve voltage is applied, thereby causing a positive wall charge, A, to the Y electrode. Negative wall charges are formed on the electrode and the X electrode, respectively. Here, the VscL voltage may be set at a level equal to or lower than the Vnf voltage. The VscH voltage higher than the VscL voltage is applied to the Y electrode to which the VscL voltage is not applied, and the reference voltage is applied to the A electrode of the discharge cell that is not selected. In order to perform this operation in the address period, the scan electrode driver 400 selects the Y electrode to which the scan pulse of the VscL voltage is applied among the Y electrodes Y1 to Yn. For example, in a single drive, the Y electrodes can be selected in the order arranged in the vertical direction. When one Y electrode is selected, the address electrode driver 300 selects a discharge cell to be turned on among discharge cells formed by the corresponding Y electrode. That is, the address electrode driver 300 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am.

In the sustain period, a sustain discharge pulse having alternating Vs voltages and 0V voltages is applied to the Y electrode and the X electrode in the opposite phase to generate a sustain discharge between the Y electrode and the X electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the Y electrode and the process of applying the sustain discharge pulse of the Vs voltage to the X electrode are repeated the number of times corresponding to the weight indicated by the corresponding subfield.

Next, with reference to FIG. 3, the drive circuit which produces | generates the drive waveform of FIG. 2 is demonstrated in detail. The switches used below are shown as n-channel field effect transistors (FETs) with body diodes (not shown), and may be composed of other switches having the same or similar functions. The capacitive component formed by the X electrode and the Y electrode is shown as a panel capacitor Cp.

3 is a diagram illustrating a driving circuit of the scan driver 400 for generating the driving waveform of FIG. 2.

As shown in FIG. 3, the scan driver 400 includes a sustain driver 410, a reset driver 420, and a scan driver 430.

The sustain driver 410 includes a power recovery unit 411 and transistors Ys and Yg. The power recovery unit 411 includes transistors Yr and Yf, an inductor L, diodes Dr and Df, and a capacitor Ce.

The transistor Ys is connected between the power supply Vs supplying the Vs voltage and the Y electrode of the panel capacitor Cp, and the transistor Yg is connected to the power supply 0V supplying the 0V voltage and the Y of the panel capacitor Cp. It is connected between the electrodes. At this time, the transistor Ys applies a Vs voltage to the Y electrode, and the transistor Yg applies a 0V voltage to the Y electrode.

The first stage of the capacitor Ce is connected to the contacts of the transistors Ys and Yg, and the capacitor Ce is charged with a voltage Vs / 2 halfway between the voltage Vs and the voltage 0V. The source of the transistor Yr is connected to the second end of the inductor L having the first end connected to the Y electrode, and the drain of the transistor Yr is connected to the first end of the capacitor Ce. The drain of the transistor Yf is connected to the second end of the circuit, and the source of the transistor Yf is connected to the first end of the capacitor Ce.

The diode Dr is connected between the source of the transistor Yr and the inductor L, and the diode Df is connected between the drain of the transistor Yf and the inductor L. The diode Dr is for setting the rising path of increasing the voltage of the panel capacitor Cp when the transistor Yr has a body diode, and the diode Df is the Y electrode when the transistor Yf has a body diode. This is to set the falling path for lowering the voltage of. At this time, if the transistors Yr and Yf do not have a body diode, the diodes Dr and Df may be removed. The connected power recovery unit 411 increases the voltage of the Y electrode from 0V voltage to Vs voltage or decreases from Vs voltage to 0V by using resonance of the inductor L and the panel capacitor Cp.

Meanwhile, the order of connection between the inductor L, the diode Df, and the transistor Yf in the power recovery unit 411 may be changed, and the connection sequence between the inductor L, the diode Dr, and the transistor Yr1 may be changed. Can be changed. For example, the inductor L may be connected between the contacts of the transistors Yr and Yf and the power recovery capacitor Ce. In addition, although the inductor L is connected to the contacts of the transistors Yr and Yf in FIG. 3, the inductor may be connected to each of the rising path formed by the transistor Yr and the falling path formed by the transistor Yf. .

The reset driver 420 includes transistors Yrr, Yfr, Ypp, and Ynp, a capacitor Cset, a zener diode ZD, and a diode Dset, and the voltage of the Y electrode is increased from the voltage Vs in the rising period of the reset period. It gradually increases up to the voltage Vset, and gradually decreases the voltage of the Y electrode from the voltage Vs to the voltage Vnf in the falling period of the reset period.

A source of the transistor Yrr having a drain connected to the power supply Vset-Vs supplying the voltage (Vset-Vs) is connected to the Y electrode, and a source of the transistor Ynp having a drain connected to the source of the transistor Yrr is It is connected to the Y electrode. A source of the transistor Ypp having a drain connected to the source of the transistor Yrr is connected to a contact point of the transistors Ys and Yg. A capacitor Cset is connected between the source of the transistor Ypp and the drain of the transistor Yrr, and the capacitor Cset is charged to the voltage (Vset-Vs) when the transistor Yg is turned on. In addition, the diode Dset is connected in the opposite direction to the body diode of the transistor Yrr to block current caused by the body diode of the transistor Yrr.

The transistor Yfr is connected between the power supply VscL supplying the VscL voltage and the Y electrode of the panel capacitor Cp. Since the voltage Vnf is higher than the voltage VscL in the driving waveform of FIG. And a Zener diode (ZD) is connected between the Y electrode and the Y electrode. Here, it is assumed that the voltage Vnf is higher than the voltage VscL by the breakdown voltage. Meanwhile, the zener diode ZD may be connected between the VscL and the transistor Yfr. Since the Vnf voltage is higher than the VscL voltage, when the transistor YscL is turned on, a current path may be formed through the body diode of the transistor Yfr. Therefore, the transistor Yfr may be formed in a back-to-back form to block the current path through the body diode of the transistor Yfr.

The scan driver 230 includes a selection circuit 431, a capacitor CscH, a diode DscH, and a transistor YscL, and applies a VscL voltage to the Y electrode to select a discharge cell to be turned on in an address period. The voltage VscH is applied to the Y electrode of the discharge cell that will not be. In general, a selection circuit 431 is connected to each of the Y electrodes Y1 to Yn in the form of an IC so that the plurality of Y electrodes Y1 to Yn can be sequentially selected in the address period. The driving circuit of the scan electrode driver 400 is commonly connected to the Y electrodes Y1-Yn. In FIG. 3, only the selection circuit 431 connected to one Y electrode is illustrated.

The selection circuit 431 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode of the panel capacitor Cp. The first end of the capacitor CscH is connected to the contact point of the source of the transistor Scl and the drain of the transistor Sch, and the drain of the transistor Sch is connected to the second end of the capacitor CscH. The transistor YscL is connected between the power supply VscL and the Y electrode of the panel capacitor Cp, and the cathode of the diode DscH whose anode is connected to the power supply VscH supplying the VscH voltage is connected to the transistor Sch. It is connected to the drain. Here, the transistor YscL is turned on so that the capacitor CscH is charged with a voltage of (VscH-VscL).

In FIG. 3, each transistor Ys, Yg, Yr, Yf, Yrr, YscL, Sch, Scl, Ynp, Ypp is shown as one transistor, but each transistor Ys, Yg, Yr, Yf, Yrr, YscL is shown as one transistor. , Sch, Scl, Ynp, and Ypp) may be formed of one transistor or a plurality of transistors connected in parallel.

Hereinafter, a method of generating the driving waveform of FIG. 2 will be described with reference to FIGS. 4A and 4B. Only the voltage applied to the Y electrode in the reset period in the driving waveform of FIG. 2 will be described.

4A and 4B are diagrams illustrating an operation process for generating a driving waveform in a reset period among the driving waveforms of FIG. 2, respectively. First, it is assumed that the transistors Yg, Ypp, Ynp, and Scl are turned on before the voltage of 0 V is applied to the Y electrode of the panel capacitor Cp before FIG. 4A starts.

4A, in the rising period of the reset period, the transistor Ys is turned on and the transistor Yg is turned off, so that the power supply Vs, the transistors Ys, Ypp, Ynp, the body diode and the panel of the transistor Scl. The voltage Vs is applied to the Y electrode through the current path of the capacitor Cp (①).

Subsequently, transistor Yrr is turned on and transistors Ys and Ypp are turned off, so that power supply Vs, transistor Ys, capacitor Cset, transistors Yrr and Ynp, body diode of transistor Scl and The voltage of the Y electrode is gradually increased to the voltage Vset through the current path of the panel capacitor Cp (2).

Next, referring to FIG. 4B, in the falling period of the reset period, the transistor Yrr is turned off and the transistor Ys is turned on, so that the panel capacitor Cp, the transistor Scl, the body diode of the transistor Ynp, and the transistor ( Ypp), the voltage Vs is applied to the Y electrode through the current path of the body diode of the transistor Ys and the power supply Vs (③).

Subsequently, the transistor Yfr is turned on and the transistor Ys is turned off, so that the voltage of the Y electrode Vnf through the current paths of the panel capacitor Cp, the zener diode ZD, the transistor Yfr, and the power supply VscL. The voltage is gradually reduced to the voltage (voltage lower than the breakdown voltage of the zener diode ZD than the voltage VscL) (4). At this time, if there is no Zener diode ZD, the Vnf voltage becomes the same voltage as the VscL voltage as shown in the driving waveform shown in FIG. 2. When the voltage of the Y electrode gradually decreases from the voltage of Vs to the voltage of Vnf, the transistor Yf is turned on instantaneously (④ '). In this way, the breakdown voltage of the transistor Ynp can be reduced.

Specifically, when the transistor Yfr is turned on and the voltage of the Y electrode is reduced to the voltage Vnf, the voltage of the source of the transistor Ynp is reduced to the voltage Vnf while the voltage Vs is applied to the drain of the transistor Ynp. The voltage difference between the drain and the source of the transistor Ynp is (Vs-Vnf). However, as in the embodiment of the present invention, if the transistor Yf is turned on momentarily before the transistor Yfr is turned on and the voltage of the Y electrode is reduced to the voltage Vnf, the inductor L, the diode Df, and the transistor ( Through the current path of Yf) and the capacitor Cer, the voltage of the drain of the transistor Ynp is reduced to the voltage charged at the capacitor Cer, that is, the voltage Vs / 2. Since the voltage of the source of the transistor Ynp is reduced to the voltage Vnf, the voltage difference between the drain and the source of the transistor Ynp becomes (Vs / 2-Vnf). As described above, according to the exemplary embodiment of the present invention, the transistor Ynp having a lower breakdown voltage (Vs / 2-Vnf) may be used as compared with the conventional Vs-Vnf, thereby reducing the cost of the circuit element.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, when the voltage of the Y electrode is reduced from the voltage Vs to the voltage Vnf in the reset period, the switch is connected between the switch connected to the power supply for supplying the Vs voltage and the switch connected to the power supply for supplying the Vnf voltage. Can reduce the internal pressure.

Claims (8)

A driving apparatus of a plasma display device comprising a plurality of first electrodes and a plurality of second electrodes performing a display operation together with the plurality of first electrodes. A first switch connected between the plurality of first electrodes and a first power supply for supplying a first voltage, the first switch operative to gradually decrease a voltage of the plurality of first electrodes; A second switch having a first end connected to the contacts of the plurality of first electrodes and the first switch, A third switch connected between a second power supply for supplying a second voltage and a second end of the second switch; A capacitor charging a third voltage lower than the second voltage, and A fourth switch connected between the capacitor and a second end of the second switch, After the third switch is turned on in the reset period to apply the second voltage to the plurality of first electrodes, the first switch is turned on to gradually decrease the voltages of the plurality of first electrodes, And the fourth switch is turned on for a period of time during which the voltage of the first electrode is gradually decreased. The method of claim 1, An inductor formed on a path formed by the capacitor, the fourth switch and the second end of the second switch, And a resonance is formed between the capacitor, the inductor, and the plurality of first electrodes when the fourth switch is turned on in the sustain period. The method of claim 2, And a fifth switch connected between the capacitor and the second end of the second switch. In the sustaining period, the driving device turns on the fourth switch to decrease the voltages of the plurality of first electrodes, and turns on the fifth switch to increase the voltages of the plurality of first electrodes. The method according to any one of claims 1 to 3, And a Zener diode formed between the first power source and the first switch or between the first switch and the plurality of first electrodes. A plurality of first electrodes, A plurality of second electrodes performing a display operation together with the plurality of first electrodes; A plurality of selection circuits respectively connected to the plurality of first electrodes, each having a first end and a second end and applying a voltage of the first end or a voltage of the second end to a corresponding first electrode; A first switch connected between a second end of the plurality of selection circuits and a first power supply for supplying the first voltage, the first switch operative to gradually decrease voltages of the plurality of first electrodes; A second switch having a first end connected to a second end of the plurality of selection circuits and a contact of the first switch; A third switch connected between a second power supply for supplying a third voltage and a second end of the second switch; An inductor having a first end connected to a second end of the second switch, A capacitor charging a fourth voltage lower than the third voltage, and A fourth switch connected between the second end of the inductor and the capacitor, In the reset period, after the third switch is turned on to apply the third voltage to the plurality of first electrodes through the second stage of the plurality of selection circuits, the first switch is turned on to turn on the plurality of first electrodes. And gradually turning on the fourth switch and turning on the fourth switch during a period of time during which the voltage of the plurality of first electrodes gradually decreases. The method of claim 5, A fifth switch connected between the second end of the inductor and the capacitor, and And a sixth switch connected between third power supplies that supply a fifth voltage lower than the fourth voltage. In the retention period, Turn on the fifth switch to increase the voltage of the plurality of first electrodes, turn on the third switch to apply the second voltage to the plurality of first electrodes, and turn on the fourth switch to turn on the plurality of first electrodes. And reducing the voltage of the first electrode of the second electrode and turning on the sixth switch to apply the fifth voltage to the plurality of first electrodes. The method of claim 6, The first switch includes two transistors connected back-to-back. The method of claim 6, And a Zener diode formed between the first power supply and the first switch or between the first switch and the plurality of first electrodes.

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