KR100708853B1 - Plasma display and driving method thereof - Google Patents

Abstract

In the plasma display device, a second voltage and a third voltage are applied to the scan electrode and the address electrode while the first voltage is applied to the sustain electrode in the address period. In the sustain period, a sustain discharge pulse having a high level voltage and a low level voltage is applied to the scan electrode while a fourth voltage lower than the first voltage is applied to the sustain electrode. At this time, the second voltage is made higher than the low level voltage of the sustain discharge pulse. In this way, the circuit element price can be reduced as compared with the case where the second voltage is lower than the low level voltage of the sustain discharge pulse.

PDP, electrode, discharge, drive board, voltage, transistor, current path

Description

Plasma display device and driving method thereof {PLASMA DISPLAY AND DRIVING METHOD THEREOF}

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

FIG. 2 is an electrode array diagram of the plasma display panel shown in FIG. 1.

3 is a schematic plan view of the chassis base shown in FIG. 1.

4 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a driving circuit of a scan driving board capable of generating the driving waveform of FIG. 4.

6A to 6C are views showing the operation of the driving circuit shown in FIG. 6 in the reset period, the address period, and the sustain period, respectively.

FIG. 7 is a diagram illustrating a current path that may occur when the VscL voltage is lower than the -Vs voltage in the driving circuit of FIG. 5.

FIG. 8 is a diagram illustrating a driving circuit for blocking the current path shown in FIG. 7.

The present invention relates to a plasma display device and a driving method thereof.

The plasma display device is a display device using a plasma display panel that displays text or an image by using plasma generated by gas discharge. In the plasma display panel, a plurality of discharge cells are arranged in a matrix form.

The display panel of the plasma display device is driven by dividing one frame into a plurality of subfields having respective weights. Each subfield includes a reset period, an address period, and a sustain period. The reset period is a period for initializing the discharge cells in order to stably perform the address discharge. The address period is a period for selecting cells that are turned on and cells that are not turned on in the display panel. The sustain period is a period in which sustain discharge for actually displaying an image is performed for the cells to be turned on.

To perform this operation, sustain discharge pulses having a high level voltage (Vs voltage) and a low level voltage (0 V) are applied to the scan electrode and the sustain electrode in an opposite phase in the sustain period, and the scan electrode in the reset period and the address period. The reset waveform and the scan waveform are applied. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

An object of the present invention is to provide a plasma display device capable of reducing the size of a sustain driving board for driving a sustain electrode. Another object of the present invention is to provide a method of driving a plasma display device capable of reducing the unit cost of circuit elements of the plasma display device.

According to one aspect of the invention, a plurality of first electrodes and the plurality of second electrodes and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, wherein the first electrode, Provided is a method of driving one frame divided into a plurality of subfields in a plasma display device in which a discharge cell is formed at an intersection point of a second electrode and a third electrode. The driving method includes applying a second voltage and a third voltage to a second electrode and a third electrode of a discharge cell to be turned on in a state where a first voltage is applied to the first electrode in an address period, and a sustain period. In the state in which a fourth voltage lower than the first voltage is applied to the first electrode, a fifth voltage higher than the fourth voltage and a sixth voltage lower than the fourth voltage are alternately applied to the second electrode. Steps. In this case, the second voltage is higher than the sixth voltage.

According to another aspect of the present invention, a plasma display device includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A plasma display panel in which a plurality of discharge cells are formed by a first electrode, a second electrode, and a third electrode, and a plurality of second electrodes in a state in which a first voltage is applied to the plurality of first electrodes in an address period. A second voltage is sequentially applied, and a high level voltage and a low level voltage are alternately applied to the plurality of second electrodes while a third voltage lower than the first voltage is applied to the plurality of first electrodes in the sustain period. The branch includes a driver for applying a sustain discharge pulse. In this case, the low level voltage of the sustain discharge pulse is lower than the second voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between. In addition, when a part is said to "include" a certain component, this means that it may further include other components, without excluding the other components unless otherwise stated.

In the present invention, the wall charge refers to a charge formed close to each electrode on the cell wall (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as “formed”, “accumulated” or “stacked” on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, FIG. 2 is an electrode arrangement diagram of the plasma display panel illustrated in FIG. 1, and FIG. 3 is a schematic plan view of the chassis base illustrated in FIG. 1. .

First, as shown in FIG. 1, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40.

The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 2, the plasma display panel 10 includes a plurality of address electrodes (hereinafter referred to as “A electrodes”) A1 to Am extending in the column direction, and a plurality of holding electrodes extending in pairs in the row direction. Electrodes (hereinafter referred to as "X electrodes") (X1 to Xn) and scan electrodes (hereinafter referred to as "Y electrodes") (Y1 to Yn). In general, the X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn. The Y electrodes Y1 to Yn and the X electrodes X1 to Xn are arranged to be orthogonal to the A electrodes A1 to Am. At this time, the discharge space at the intersection of the A electrodes A1 to Am and the X and Y electrodes X1 to Xn and Y1 to Yn forms the cell 12. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

Next, referring to FIG. 3, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed at any one of the upper and lower portions of the chassis base 20. In FIG. 3, a plasma driving apparatus for single driving is described as an example, but in the case of dual driving, the address buffer board 100 is disposed above and below the chassis base 20, respectively. The address buffer board 100 receives an address driving control signal from the control board 400 and applies a voltage for selecting discharge cells to be displayed to each of the A electrodes A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, and the scan drive board 200 is connected to the scan buffer board 300 through a connection member 26 such as a conductive pattern or a cable, and scan The buffer board 300 is electrically connected to the Y electrodes Y1 to Yn through a flexible printed circuit (FPC) 22. In addition, the scan drive board 200 is electrically connected to the X electrodes X1 to Xn through the connection member 24 and the flexible printed circuit (FPC) 22 formed longer than the connection member 26. It is connected. The scan driving board 200 receives a driving signal from the control board 400 and applies a driving voltage to the Y electrodes Y1 to Yn and the X electrodes X1 to Xn. The scan buffer board 300 applies a voltage for sequentially selecting the Y electrodes Y1 to Yn to the Y electrodes Y1 to Yn in the address period. In FIG. 3, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The control board 400 receives an image signal from the outside to generate a control signal for driving the A electrodes A1 to Am and a control signal for driving the Y and X electrodes Y1 to Yn and X1 to Xn, respectively. The board 100 is applied to the scan driving board 200.

The control board 400 and the power board 500 may be disposed in the center of the chassis base 20. The power board 500 supplies power for driving the plasma display device.

Here, the address buffer board 100, the scan driving board 200, and the scan buffer board 300 form a driving unit for driving the A electrode, the Y electrode, and the X electrode, and the control board 100 controls the driving unit. The power board 500 forms a power supply unit for supplying power to the driving unit and the control unit.

A driving waveform of the plasma display device according to the first exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.

4 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention. In the following description, only the driving waveforms applied to the Y electrode, the X electrode, and the A electrode forming one cell will be described. In the driving waveform of FIG. 4, voltages applied to the Y electrode and the X electrode are supplied from the scan driving board 200 and the scan buffer board 300, and a voltage applied to the A electrode is supplied from the address buffer board 100.

As shown in Fig. 4, in the rising period of the reset period, the voltage of the Y electrode is gradually increased from the voltage of Vs to the voltage of Vset while the A electrode and the X electrode are maintained at the reference voltage (0 V in Fig. 4). In FIG. 4, the voltage of the Y electrode is shown to increase in the form of a lamp. Then, while the voltage of the Y electrode is increased, a weak discharge (hereinafter referred to as “weak discharge”) occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is applied to the Y electrode. And a positive wall charge is formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 4, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions.

In the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the X electrode is maintained at the Vb voltage. Then, while the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode, and between the Y electrode and the A electrode, and the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode. Is erased. In general, the magnitude of the voltage (Vnf-Vb) is set near the discharge start voltage between the Y electrode and the X electrode. Then, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, thereby preventing the cells that will not be turned on in the address period from being discharged in the sustain period.

In the address period, in order to select a discharge cell to be turned on, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively, while the voltage of the X electrode is maintained at the Vb voltage. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. Then, an address discharge occurs in the discharge cells formed by the A electrode to which the Va voltage is applied and the Y electrode to which the VscL voltage is applied, thereby forming positive wall charges on the Y electrode and negative wall charges on the A electrode and the X electrode, respectively. do. Here, the VscL voltage is higher than the -Vs voltage, which is the low voltage of the sustain discharge pulse. As described above, the reason why the VscL voltage is lower than the -Vs voltage will be described later with reference to the driving circuits of FIGS. 5 and 6.

On the other hand, in order to perform this operation in the address period, the scan buffer board 300 selects the Y electrode to which the scan pulse of the VscL voltage is applied among the Y electrodes Y1 to Yn. For example, in a single drive, the Y electrodes can be selected in the order arranged in the vertical direction. When one Y electrode is selected, the address buffer board 100 selects a discharge cell to be turned on among the discharge cells formed by the corresponding Y electrode. That is, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am.

Specifically, first, a scan pulse is applied to the Y electrode of the first row (Y1 in FIG. 2) and an address pulse is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the address pulse is applied, thereby forming positive wall charges on the Y electrode and negative wall charges on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while a scan pulse is applied to the Y electrode (Y2 of FIG. 2) in the second row, an address pulse is applied to the A electrode located in the cell to be turned on in the second row. Then, an address discharge occurs in the cell formed by the A electrode to which the address pulse is applied and the Y electrode in the second row, thereby forming wall charges in the cell. Similarly, an address pulse is applied to the A electrode positioned in the cell to be turned on while the scan pulse is sequentially applied to the Y electrodes of the remaining rows, thereby forming wall charges in the corresponding cell.

Subsequently, in the cell in which the address discharge occurred in the address period, the wall voltage Vwxy was formed between the Y electrode and the X electrode so that the potential of the Y electrode was higher than the potential of the X electrode. In the state held at the voltage, a sustain discharge pulse having a voltage of Vs is first applied to the Y electrode to generate a sustain discharge between the Y electrode and the X electrode. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is higher than the voltage Vfxy. As a result of the sustain discharge, negative wall charges are formed on the Y electrode and positive wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vwyx is formed so that the potential of the X electrode is high with respect to the potential of the Y electrode. do.

Subsequently, a sustain discharge pulse having a voltage of -Vs is applied to the Y electrode to generate a sustain discharge between the Y electrode and the X electrode. As a result, a positive wall charge is formed at the Y electrode and a negative wall charge is formed at the X electrode and the A electrode, so that a sustain discharge can occur when a Vs voltage is applied to the Y electrode. Thereafter, a sustain discharge pulse having an alternating voltage of Vs and -Vs is applied to the Y electrode a number of times corresponding to the weight indicated by the corresponding subfield.

As described above, in the first embodiment of the present invention, the driving voltage is applied to the Y electrode while the voltage Vb is applied to the X electrode only during the falling period and the address period of the reset period, and the reference voltage is applied to the X electrode in the remaining period. The reset operation, the address operation and the sustain discharge operation can be performed only by the waveform. In this case, since the Vb voltage is supplied from the scan driving board 200, only one board may be driven. As a result, the area occupied by the driving boards 100 to 500 on the chassis base 20 may be reduced, and the overall circuit cost required for driving the plasma display panel may be reduced. The Vb voltage is applied to the X electrode through the relatively long connecting member 24, but the Vb voltage remains constant during the falling period and the address period of the reset period, so that there is little effect of waveform distortion due to parasitic components. .

Next, with reference to FIG. 5, the drive circuit which produces | generates the drive waveform of FIG. 4 is demonstrated in detail. The switches used below are shown as n-channel field effect transistors (FETs) with body diodes (not shown), and may be composed of other switches having the same or similar functions. The capacitive component formed by the X electrode and the Y electrode is shown as a panel capacitor Cp. Although the X electrode is shown as biased with the ground voltage for convenience, the ground voltage or the Vb voltage is actually applied to the X electrode according to the reset period, the address period, and the sustain period.

5 is a diagram illustrating a driving circuit of the scan driving board 200 for generating the driving waveform of FIG. 4.

As shown in FIG. 5, the driving circuit of the scan driving board 200 includes a sustain driver 210, a reset driver 220, and a scan driver 230.

The sustain driver 210 includes transistors Ys1, Ys2, and Yg, and alternately applies a Vs voltage and a -Vs voltage to the Y electrode in the sustain period. A source of the transistor Ys1 having a drain connected to the power supply Vs supplying the Vs voltage is connected to the Y electrode of the panel capacitor Cp, and a transistor connected to the power supply (-Vs) supplying the voltage -Vs ( The drain of Ys2) is connected to the Y electrode of the panel capacitor Cp. In addition, a transistor Yg is connected between the Y electrode of the panel capacitor Cp and the ground terminal 0, which is a power supply for supplying a 0V voltage, and to block a current path through the body diode of the transistor Yg, Yg) may be formed in two transistors back-to-back.

The reset driver 220 includes transistors Yrr and Yfr, a zener diode ZD, and a diode Dset, and gradually increases the voltage of the Y electrode from the voltage Vs to the voltage Vset in the rising period of the reset period, and resets the voltage. In the falling period of the period, the voltage of the Y electrode is gradually decreased from the voltage of Vs to the voltage of Vnf. A source of the transistor Yrr having a drain connected to the power supply Vset supplying the Vset voltage is connected to the Y electrode of the panel capacitor Cp. The diode Dset is formed in a direction opposite to the body diode of the transistor Yrr in order to block current caused by the body diode of the transistor Yrr. The transistor Yfr is connected between the power supply VscL supplying the VscL voltage and the Y electrode of the panel capacitor Cp. Since the Vnf voltage is higher than the VscL voltage in the driving waveform of FIG. 4, the transistor Yfr ) Is connected to the anode of the Zener diode (ZD) and the cathode of the Zener diode (ZD) is connected to the Y electrode of the panel capacitor (Cp). Here, it is assumed that the voltage Vnf is a voltage higher by the breakdown voltage than the voltage VscL. Since the Vnf voltage is higher than the VscL voltage, when the transistor YscL is turned on, a current path may be formed through the body diode of the transistor Yfr. Therefore, in order to block the current path through the body diode of the transistor Yfr, the transistor Yfr may be formed in a back-to-back form.

The scan driver 230 includes a selection circuit 231, a capacitor CscH, a diode DscH, and a transistor YscL, and applies a VscL voltage to the Y electrode to select a discharge cell to be turned on in an address period. The voltage VscH is applied to the Y electrode of the discharge cell that will not be. In general, a selection circuit 231 is connected to each of the Y electrodes Y1-Yn in the form of an IC so that the plurality of Y electrodes Y1-Yn can be sequentially selected in the address period. The driving circuit of the scan driving board 200 is commonly connected to the Y electrodes Y1-Yn. In FIG. 5, only the selection circuit 231 connected to one Y electrode is illustrated. The selection circuit 231 includes transistors Sch and Scl. The source of the transistor Sch and the drain of the transistor Scl are respectively connected to the Y electrode of the panel capacitor Cp. The second end of the capacitor CscH, whose first end is connected to the contact point of the source of the transistor Scl and the drain of the transistor Schc, is connected to the drain of the transistor Sch, and the power supply VscH supplies the VscH voltage. The cathode of the diode DscH having an anode connected thereto is connected to the drain of the transistor Sch. Here, the transistor YscL is turned on, and the capacitor CscH is charged with the voltage (VscH-VscL). Since the transistor YscL is connected between the power supply VscL and the Y electrode of the panel capacitor Cp, and the VscL voltage is formed higher than the -Vs voltage, blocking the current by the body diode of the transistor YscL. The transistor YscL may be formed in a back-to-back form.

Meanwhile, in the driving circuit of FIG. 5, a power recovery circuit (not shown) may be connected to the contacts of the transistors Ys1 and Ys2 to recover and reuse the reactive power formed by the sustain discharge pulse in the sustain period.

Hereinafter, a method of generating the driving waveform of FIG. 4 will be described with reference to FIGS. 6A to 6C. First, it is assumed that before the start of FIG. 6A, the transistors Yg and Scl are turned on so that a 0V voltage is applied to the Y electrode of the panel capacitor Cp.

6A to 6C are views showing the operation of the driving circuit shown in FIG. 6 in the reset period, the address period, and the sustain period, respectively.

As shown in Fig. 6A, in the rising period of the reset period, the transistor Ys1 is turned on and the transistor Yg is turned off, so that the body diode and panel capacitor of the power supply Vs, the transistor Ys1, the transistor Scl ( The voltage Vs is applied to the Y electrode through the current path of Cp) (①). Subsequently, transistor Yrr is turned on and transistor Ys1 is turned off, so that the voltage at the Y electrode gradually advances to the voltage Vset through the current path of the power supply Vset, the body diode of the transistor Scl, and the panel capacitor Cp. (②).

In the falling period of the reset period, the transistor Yrr is turned off and the transistor Ys1 is turned on, so that the Y electrode is turned on through the current path of the panel capacitor Cp, the transistor Scl, the transistor Ys1, and the power supply Vs. The voltage Vs is applied (③). Subsequently, the transistor Yfr is turned on and the transistor Ys1 is turned on so that the voltage of the Y electrode is changed to the Vnf voltage through the current path of the panel capacitor Cp, the zener diode ZD, the transistor Yfr, and the power supply VscL. It is gradually decreased until (④).

As shown in Fig. 6B, in the address period, the transistor Yfr is turned off, the transistors YscL and sch are turned on, and the capacitor CscH charged with the power supply VscL, transistor YscL, and VscH voltage and The voltage VscH is applied to the Y electrode through the current path of the transistor Sch (5). When the Y electrode of the discharge cell to be turned on is selected, the transistor Sch is turned off and the transistor Scl is turned on so that the panel capacitor Cp, the body diode of the transistor Scl, the transistor YscL, and the power supply VscL are turned on. The voltage VscL is applied to the Y electrode through the current path of (6). Subsequently, when another Y electrode is selected, the transistor Sch is turned on again to apply a VscH voltage to the Y electrode (5). At the end of the address period, the transistor YscL is turned off and the transistor Yg is turned on to ground. (0), a 0 V voltage is applied to the Y electrode through the current path of the transistor Yg, the body diode of the transistor Scl, and the panel capacitor Cp (7).

Next, as shown in FIG. 6C, in the sustain period, the transistor Ys1 is turned on and the transistor Yg is turned off, so that the power supply Vs, the transistor Ys1, the body diode and the panel capacitor of the transistor Scl ( The voltage Vs is applied to the Y electrode through the current path of Cp) (8). Subsequently, transistor Ys2 is turned on and transistor Ys1 is turned off, so that -Vs is applied to the Y electrode through a current path to the panel capacitor Cp, transistor Scl, transistor Ys2, and power source (-Vs). Voltage is applied (⑨). This operation may be repeated to apply a sustain discharge pulse alternately having a voltage of Vs and a voltage of -Vs to the Y electrode.

On the other hand, before the voltage Vs is applied to the Y electrode through the current path (8) and the -Vs voltage is applied to the Y electrode through the current path (9) in the sustain period, the transistor Yg is turned on and the 0V voltage is applied to the Y electrode. May be applied.

At this time, when the voltage VscL is set lower than the voltage -Vs, when the transistor YscL is turned on in the address period, as shown in FIG. And a current path to the power supply VscL. Short circuits can be generated by this current path and the circuit elements can be destroyed. Therefore, in order to block the current path, as shown in the driving circuit of FIG. 8, when the transistor YscL is turned on, a transistor Ynp that can block the path between the power source -Vs and the power source VscL is required. However, when the VscL voltage is set higher than the -Vs voltage as in the embodiment of the present invention, when the transistor YscL is turned on, the current path shown in FIG. 7 is not formed. Therefore, unlike the driving circuit shown in FIG. 8, the transistor Ynp may be removed. This reduces the cost of the circuit elements.

Also, when the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A electrode and the Y electrode and the external voltage Vnf between the A electrode and the Y electrode is the discharge start voltage Vfay between the A electrode and the Y electrode. Is determined. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the size of the sustain driving board for driving the sustain electrode can be reduced, and the unit cost of the circuit element can be reduced in the plasma display device.

Claims (10)

A plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, wherein the first electrodes, the second electrodes, and the third electrodes In a plasma display device in which discharge cells are formed at intersections, a frame is driven by dividing a frame into a plurality of subfields. In the address period, applying a second voltage and a third voltage to the second electrode and the third electrode of the discharge cell to be turned on while the first voltage is applied to the plurality of first electrodes, and In the sustain period, a fifth voltage higher than the fourth voltage and a sixth lower than the fourth voltage to the plurality of second electrodes while a fourth voltage lower than the first voltage is applied to the plurality of first electrodes. Alternately applying voltage Including; And the second voltage is higher than the sixth voltage. The method of claim 1, Gradually reducing a voltage of the second electrode from a seventh voltage to an eighth voltage higher than the second voltage in a state in which the first voltage is applied to the plurality of first electrodes; A method of driving a plasma display device. The method of claim 2, In the reset period, gradually increasing voltages of the plurality of second electrodes from a ninth voltage to a tenth voltage while applying the fourth voltage to the plurality of first electrodes The driving method of the plasma display device further comprising. The method according to any one of claims 1 to 3, And the fourth voltage is a ground voltage. A plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, wherein the plurality of first electrodes, the plurality of second electrodes, and A plasma display panel in which a plurality of discharge cells are formed by the plurality of third electrodes, and A second voltage is sequentially applied to the plurality of second electrodes while a first voltage is applied to the plurality of first electrodes in an address period, and lower than the first voltage to the plurality of first electrodes in a sustain period. A driving unit configured to apply a sustain discharge pulse alternately having a high level voltage and a low level voltage to the plurality of second electrodes while a third voltage is applied, The low level voltage of the sustain discharge pulse is a voltage lower than the second voltage. The method of claim 5, The driving unit, A selection circuit connected to each of the plurality of second electrodes to apply the second voltage to the plurality of second electrodes in the address period; A first switch connected between a first power supply for supplying a high level voltage of the sustain discharge pulse and the plurality of second electrodes; A second switch connected between a second power supply for supplying a low level voltage of the sustain discharge pulse and the plurality of second electrodes; and And a third switch connected between a third power supply for supplying the second voltage and the plurality of second electrodes. The method of claim 6, The driving unit, A fourth switch connected between a fourth power supply for supplying a fourth voltage higher than the second voltage and the plurality of second electrodes, and And a Zener diode connected between the fourth switch and the plurality of second electrodes, And a voltage of the second electrode is gradually reduced to the fourth voltage while the first voltage is applied to the plurality of first electrodes in a reset period. The method according to any one of claims 5 to 7, The driving unit, A fifth switch connected between the plurality of second electrodes and a fifth power supply for supplying a fifth voltage between the high level voltage and the low level voltage of the sustain discharge pulse; In the sustain period, after the high level pulse of the sustain discharge pulse is applied to the plurality of second electrodes, the fifth switch is turned on before the low level of the sustain discharge pulse is applied to the plurality of second electrodes. Display device. The method of claim 8, The fifth switch includes two transistors connected back-to-back. The method of claim 8, And the third and fifth voltages are ground voltages.

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