KR100637513B1 - Plasma display device and driving method thereof - Google Patents

Abstract

In the plasma display device according to the present invention, when the plurality of first electrodes are divided into a plurality of groups including first and second groups, the plurality of first electrodes of the first group may be connected through a second end of a selection circuit. A first voltage is sequentially applied and a second voltage lower than the first voltage is applied to the plurality of first electrodes of the second group through the second end of the selection circuit. A first switch is connected between the second end of the selection circuit and the first end of the first power source, and a second switch is connected between the second end of the first power source and the second power source. A third switch is connected between the second stage and the third power source. In this case, the voltage supplied from the third power source is higher than the voltage supplied from the second power source, the first switch and the third switch are turned on to apply the first voltage to the first electrode. A first switch and a second switch are turned on to apply the second voltage to the first electrode. The third voltage is supplied by a power supply for supplying a voltage for processing an image signal in the plasma display device or a power supply for supplying a voltage for controlling a switch in a driving circuit of the plasma display device.

PDP, electrode, addressing, scanning voltage, transistor, switch, power supply, low voltage

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention.

3 is a driving circuit diagram according to a first embodiment for generating the driving waveform of FIG. 2.

4 is a diagram illustrating a current path for generating scan pulses applied to scan electrodes of groups G1 and G2 shown in FIG. 2.

FIG. 5 is a diagram illustrating a driving circuit and a current path according to a second embodiment for generating the driving waveform of FIG. 2.

6 is a diagram illustrating a configuration of a gate driver.

FIG. 7 is a diagram illustrating a driving circuit and a current path according to a third embodiment for generating the driving waveform of FIG. 2.

The present invention relates to a plasma display device and a driving method thereof.

In the plasma display panel of the AC plasma display device, scan electrodes and sustain electrodes that are parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

In general, a display panel of a plasma display device is driven by dividing one frame into a plurality of subfields having respective weights. As shown in FIG. 1, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cell.

In particular, in the address period, scan pulses are sequentially applied to the plurality of scan electrodes to select discharge cells to be displayed, and address pulses are applied to the address electrodes of the discharge cells to be turned on.

On the other hand, the address discharge is determined by the density of the priming particles and the wall voltage due to the wall charges formed in the discharge space. By the way, when the scan pulse is sequentially applied to the scan electrode (Y), the discharge cells formed on the top of the panel is the address discharge in the state that there are many priming particles formed in the reset period, while the discharge cells formed at the bottom of the panel The address discharge occurs in the state where much priming particles formed in the reset period disappear. In addition, since the wall voltage also disappears over time, in the scan electrode to which the scan pulse is applied later in time, the discharge delay time may be longer than the width of the scan pulse due to the disappearance of the priming particles and the wall charge, and thus the address discharge may not occur or may occur weakly. .

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device and a method of driving the same, which can reduce a unit cost of a driving circuit for generating a driving waveform capable of performing a stable addressing operation.

According to an aspect of the present invention, a plasma display device including a plurality of first electrodes and a plurality of second electrodes is provided. The plasma display device includes a plurality of selection circuits electrically connected to a plurality of first electrodes to selectively apply a voltage supplied to a first end and a voltage supplied to a second end to the first electrode, and the plurality of first electrodes. When dividing the first electrode into a plurality of groups including first and second groups, a first voltage is sequentially applied to the plurality of first electrodes of the first group through a second end of the selection circuit. And a driving circuit for applying a second voltage lower than the first voltage to the plurality of first electrodes of a second group through the second end of the selection circuit. The driving circuit may include a first switch connected between a second end of the selection circuit and a first end of a first power source, a second switch connected between the second end of the first power source and a second power source, and the first switch. And a third switch connected between the second end of the first power source and the third power source.

In this case, the voltage supplied from the third power source is higher than the voltage supplied from the second power source, the first switch and the third switch are turned on, and the first voltage is applied to the first electrode. A switch and a second switch may be turned on to apply the second voltage to the first electrode. Here, the second power source may be a ground power source.

The voltage supplied from the third power source is lower than the voltage supplied from the second power source. The first switch and the second switch are turned on to apply the first voltage to the first electrode. A second voltage may be applied to the first electrode while the switch and the third switch are turned on. Here, the second power source may be a ground power source.

The driving circuit may further include a controller configured to process input image data to generate a control signal for controlling the driving circuit, and the third voltage may be generated by a power supply supplying a voltage to the controller. . The third voltage may be generated by a power supply for supplying a voltage supplied to a driver for controlling a switch formed in the driving circuit.

According to another aspect of the present invention, a method of driving the first electrode in an address period in a plasma display device including a plurality of scan electrodes is provided. The driving method may include connecting a first end of a first power source to a second power source, and when the plurality of scan electrodes are divided into a plurality of groups, the first power source and the second power source may be used. Sequentially applying a first voltage to the plurality of scan electrodes belonging to the first group, connecting a first end of the first power supply to a third power supply that supplies a voltage lower than the second power supply, and the first And applying a second voltage to a plurality of scan electrodes belonging to a second group of the plurality of groups through a power source and the third power source. In this case, the second power supply may supply a ground voltage, the third power supply may supply a negative third voltage, the third power supply may supply a ground voltage, and the second power supply may supply a positive third voltage. Can supply

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like reference numerals designate like parts throughout the specification.

In the present invention, the wall charge refers to a charge formed in the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulated in the electrode. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

A plasma display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. And a power supply unit 600.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 100 includes a substrate (not shown) on which the sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a substrate (not shown) on which the address electrodes A1 to Am are arranged. The two substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y driving control signal. The control unit 200 divides and drives one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

The power supply unit 600 supplies power required for driving the plasma display device to the control unit 200 and the respective driving units 300, 400, and 500.

Hereinafter, a driving waveform applied to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn in each subfield will be described with reference to FIG. 2. The following description will be made based on the discharge cells formed by one address electrode, sustain electrode and scan electrode.

2 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention. In FIG. 2, only one sustain electrode X and one address electrode A are illustrated.

In the reset period, the voltage of the scan electrode Y is increased from the voltage Vs to the voltage Vset while the sustain electrode X is held at 0V. Then, a weak reset discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively, and negative wall charges are accumulated on the scan electrode Y, and the address electrode A and the sustain electrode are accumulated. Positive wall charges build up on electrode X. Then, the scan electrode Y is reduced from the voltage Vs to the voltage Vnf. At this time, a reference voltage (assuming 0 V in FIG. 2) is applied to the address electrode A, and the sustain electrode X is biased to the Ve voltage. Then, while the voltage of the scan electrode Y decreases, a weak reset discharge occurs between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A, and thus the scan electrode ( The negative wall charges formed on Y) and the positive wall charges formed on the sustain electrode X and the address electrode A are erased.

Next, in the address period, a scan pulse having voltages VscL1 and VscL2 is sequentially applied to the scan electrode Y to select a discharge cell, and the scan electrodes to which the voltages VscL1 and VscL2 are not applied are subjected to a VscH voltage (ratio). Bias). Then, an address pulse having a Va voltage is applied to an address electrode A passing through a discharge cell to be selected from among a plurality of discharge cells formed by the scan electrodes Y to which the voltages VscL1 and VscL2 are applied. The non-address electrode A applies a reference voltage (0 V in FIG. 2). Then, an address discharge is generated in the discharge cells formed by the address electrode A to which Va voltage is applied and the scan electrode Y to which the voltages VscL1 and VscL2 are applied, and the wall of the positive electrode is formed on the scan electrode Y. An electric charge is formed and a negative wall charge is formed on the sustain electrode X. In addition, a negative wall charge is also formed on the address electrode A. FIG.

According to an embodiment of the present invention, when a scan pulse is applied to the scan electrode Y in the address period, the scan electrode Y is divided into a plurality of groups G1 and G2 according to the order in which the scan pulses are applied. Groups G1 and G2 are shown to include k and (nk) scan electrodes, respectively.

In detail, a scan pulse having a VscL1 voltage is applied to the scan electrodes Y1 to Yk of the group G1 positioned at the upper end of the plasma display panel 100, and the group positioned at the bottom of the plasma display panel 100 ( A scan pulse having a VscL2 voltage lower than the VscL1 voltage is applied to the scan electrodes Yk + 1 to Yn of G2). Then, the difference between the scan voltage and the address voltage (| VscL2-Va |) in the group G2 becomes larger than the difference between the scan voltage and the address voltage (| VscL1-Va |) in the group G1 and thus the group G2. In this case, the discharge delay time is shortened, so that stable address discharge can be caused even in the discharge cells formed by the scan electrodes of the group G2.

Subsequently, in the sustain period, the sustain discharge pulse of the Vs voltage is sequentially applied to the scan electrode Y and the sustain electrode X. FIG. Then, if the wall voltage is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period, the discharge is performed at the scan electrode Y and the sustain electrode X by the wall voltage and the Vs voltage. This happens. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. .

Next, a driving circuit capable of generating a driving waveform according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a driving circuit diagram according to a first embodiment for generating the driving waveform of FIG. 2. In the following, each transistor may be formed with a body diode having an anode connected to a source and a cathode connected to a drain.

As shown in FIG. 3, the scan electrode driver 500 includes a rising reset part 501, a falling reset part 502, a scan driver 503, and a sustain discharge part 504.

The scan driver 503 includes a plurality of selection circuits 510 respectively connected to the plurality of scan electrodes Y. In FIG. 4, only one scan electrode Y and one selection circuit 510 are provided for convenience of description. Shown. The capacitive component formed by the sustain electrode X adjacent to the scan electrode Y is illustrated as a panel capacitor Cp, and the sustain electrode driver 400 (not shown) is connected to the scan electrode Y. It is marked as ground for convenience.

The rising reset unit 501 includes a diode Dset, a capacitor Cset, and a transistor Ypp and Yrr, and the voltage Vs from the voltage Vs to the scan electrode Y are set. Apply a voltage that gradually rises to the voltage.

The capacitor Cset has a cathode connected between the source of the transistor Ypp and the drain of the transistor Yrr, and the drain of the transistor Ypp and the source of the transistor Yrr are respectively connected to the second node N2. At this time, the capacitor Cset is charged to the voltage (Vset-Vs) when the transistor Yg described below is turned on, and the transistor Yrr is set to the voltage of the panel capacitor Cp at turn-on. A small current flows from the drain to the source to slowly rise to voltage.

And diode (Dset) is (Vset-Vs) It is connected between the power supply (Vset-Vs) supplying the voltage and the contact of the drain of the transistor (Yrr) and the capacitor (Cset) to block the current path to the capacitor (Cset)-diode (Dset)-power supply (Vset-Vs) Let's do it.

The falling reset part 502 includes transistors Ynp and Yfr, and Vnf at the voltage Vs at the scan electrode Y. Apply a voltage that gradually rises to the voltage.

The drain of the transistor Yfr is connected to the first node N1 and the source of the transistor Yfr is connected to a power supply Vnf supplying a voltage Vnf which is the final voltage of the falling period, and the transistor Yfr is turned on. A minute current flows from the drain to the source to gradually reduce the voltage of the scan electrode Y to the voltage Vnf. At this time, the transistor Ynp is Vnf. It cuts off the current path towards power source GND-transistor Yg-transistor Ypp-transistor Ynp-transistor Yfr that can be formed when the voltage is negative.

The scan driver 503 includes a selection circuit 510, a diode Dsch, a capacitor Csch, and transistors YscL1 and YscL2, and the VscL1 voltage or VscL2 is sequentially applied to the scan electrode Y. Apply voltage.

In general, a selection circuit 510 is connected to each scan electrode Y1-Yn in the form of an IC so that the plurality of scan electrodes Y1-Yn may be sequentially selected in an address period. The driving circuit of the scan electrode driver 500 is commonly connected to the scan electrodes Y1-Yn.

The selection circuit 510 includes transistors Sch and Scl, the source of the transistor Sch and the drain of the transistor Scl are connected to the scan electrode Y of the panel capacitor Cp, and the transistor Scl. ) Is connected to the first node N1.

The capacitor Csch is connected between the drain of the transistor sch and the first node N1, and the diode Dsch is a power supply VscH for supplying a VscH voltage and a contact between the capacitor Csch and the drain of the transistor Sch. ) Is connected between. The first end of the capacitor Csch is connected to the drain of the transistor Sch, and the second end of the capacitor Csch is connected to the first node N1. The transistors YscL1 and YscL2 are connected between the first node N1 and the power supplies VscL1 and VscL2 for supplying the VscL1 voltage and the VscL2 voltage, respectively, and the VscL1 voltage to the scan electrode Y forming the discharge cell to be selected. Or supply the VscL2 voltage. That is, in the address period, the transistor Sch is turned on to apply the VscH voltage to the scan electrode Y which is not selected using the voltage charged in the capacitor Csch, and the scan electrode to be selected by turning on the transistor scl ( The voltage VscL1 or VscL2 is applied to Y). In this case, according to an exemplary embodiment of the present invention, the transistor YscL1 is turned on to apply the voltage VscL1 to the scan electrode Y of the group G1, and the transistor YscL2 is turned on to turn on the scan electrode of the group G2. The voltage VscL2 is applied to Y).

The sustain discharge unit 504 includes transistors Ys and Yg, and applies a Vs voltage and a 0V voltage to the scan electrode Y.

Transistor Ys is connected to a power source Vs whose drain is supplying the voltage Vs and source is connected to the third node N3, transistor Yg is connected to the third node N3 and the source is 0V. It is connected to the power supply (0V) that supplies. In addition, a power recovery circuit (not shown) may be connected to the third node N3 to recover and reuse reactive power generated by the sustain discharge pulse in the sustain period. As such a power recovery circuit there is a circuit proposed by L.F.Weber (US Pat. Nos. 4,866,349 and 5,081,400). When the VscL voltage is lower than the Vnf voltage, a current path may be formed through the body diode of the transistor Yfr when the transistor YscL is turned on. In order to block the current path, as shown in FIG. 3, a transistor Yfr1 may be further formed in which the body diode is formed in the opposite direction to the body diode of the transistor Yfr. In addition, a diode may be connected instead of the transistor Yfr1.

Hereinafter, a method of generating a scan pulse in an address period using the driving circuit of FIG. 3 will be described in detail with reference to FIG. 4.

4 is a diagram illustrating a current path for generating scan pulses applied to scan electrodes of groups G1 and G2 shown in FIG. 2. First, the transistor YscL1 is turned on so that the capacitor Csch is charged with the voltage (VscH-VscL1), and the scan is not selected using the voltage charged in the capacitor Csch by turning on the transistor Sch in the address period. The voltage VscH is applied to the electrode Y.

Then, as shown in FIG. 4, when the scan electrode Y of the group G1 is sequentially selected in the address period, the transistor Scl of the selection circuit of the scan electrode Y selected is turned on to thereby turn on the group G1. VscL1 voltage is applied to scan electrode (Y) (path 1).

In this manner, after sequentially applying the VscL1 voltage to the scan electrode Y of the group G1, the transistor YscL1 is turned off and the transistor YscL2 is turned on. Then, the capacitor Csch is charged with the voltage (VscH-VscL2), and the VscH voltage is applied to the scan electrode Y through the transistor Sch of the selection circuit.

When the scan electrode Y of the group G2 is sequentially selected, the transistor Scl of the selection circuit of the scan electrode Y selected is turned on to turn on the VscL2 voltage to the scan electrode Y of the group G2. Apply (path ②).

In this manner, the voltage VscL1 may be applied when the scan electrode Y of the group G1 is selected in the address period, and the voltage VscL2 may be applied when the scan electrode Y of the group G2 is selected.

However, according to an embodiment of the present invention, the address cells are stably addressed even in the discharge cells formed by the scan electrodes to which the scan pulses are applied later by using different scan voltages VscL1 and VscL2 for each group G1 and G2 in the address period. Although it may cause a discharge, the circuit unit cost increases because a separate power source for supplying the scan voltages VscL1 and VscL2 must be added. Hereinafter, a driving circuit capable of applying different scan voltages to groups G1 and G2 without increasing a circuit unit cost will be described in detail with reference to FIG. 5.

FIG. 5 is a diagram illustrating a driving circuit and a current path according to a second embodiment for generating the driving waveform of FIG. 2.

As shown in FIG. 5, the driving circuit according to the second embodiment of the present invention connects the switches SW1 and SW2 in series to a power supply for supplying a VscL2 voltage instead of a power supply VscL1 for supplying a VscL1 voltage. SW1 is connected to a power supply (0V) supplying a ground voltage, and switch SW2 is connected to a power supply (Vb) supplying a Vb voltage. At this time, the voltage Vb is the difference between the scan voltage VscL1 applied to the scan electrode Y of the group G1 and the scan voltage VscL2 applied to the scan electrode Y of the group G2 in the above-described address period. Corresponds to the voltage.

As shown in FIG. 5, in the address period, the switch SW2 and the transistors YscL2 and Scl are turned on to apply the VscL1 voltage to the scan electrode Y to be selected from the scan electrodes of the group G1 (path). ① '). That is, a voltage corresponding to the sum of the VscL2 voltage and the Vb voltage is applied to the scan electrode Y of the group G1 through the path ① '.

Then, when the scan electrode Y is selected among the scan electrodes of the group G2, the switch SW2 is turned off, the switch SW1 is turned on, and VscL2 is applied to the scan electrode Y of the group G2. Apply voltage (path ② ').

Meanwhile, a gate driver for driving the transistor will be described in detail with reference to FIG. 6.

6 illustrates a gate driver. In FIG. 6, only the gate driver of the transistor YscL2 is shown in the driving circuit.

As shown in FIG. 6, the gate driver 520 includes a level shifter 521, a capacitor C1, and resistors R1 and R2. The gate driver 520 connects the resistors R1 and R2 in series between the gate and the source of the transistor, one end of the capacitor C1 is electrically connected to the contact between the resistors R1 and R2, and the capacitor C1 The other end of)) is electrically connected to the output terminal of the level shifter 521. At this time, the capacitor is charged with a voltage equal to the source voltage of the transistor.

Referring to the operation of the gate driver 520, when the input voltage 5V is input to the level shifter 521, the level shifter 521 outputs 15V (or 9V), and the capacitor C1 has a source voltage of the transistor. Since the transistor is charged, the transistor is driven by the gate-source voltage of the transistor becoming 15V (or 9V). In addition, when the input voltage 0V is input to the level shifter 521, the level shifter 521 outputs 0V, so that the transistor is not driven because the gate voltage of the transistor becomes the same as the source voltage. As described above, the gate driver drives the transistor by the voltage charged in the capacitor C1 and the voltage output from the level shifter 521.

In general, the power supply unit 600 supplies various high voltages required for plasma discharge, for example, a sustain discharge voltage Vs, an address voltage Va, a reset voltage Vset, and a scan voltage vscL2 to a driving circuit. The power supply unit 600 supplies low voltages such as 3.3V and 5V to the control unit 200 for image processing, and 9V and 15V to the gate driver of the transistor to drive the transistors of the drivers 300, 400, and 500. Supply the low voltage of. Therefore, according to the second embodiment of the present invention, by using the power supply for supplying the low voltage as the power supply Vb for supplying the Vb voltage, it is not necessary to use a power supply for generating a separate voltage. In this case, although only one voltage Vb is illustrated in FIG. 4, one of various low voltages supplied from the power supply unit 600 may be selected and used according to an address discharge characteristic by adding a switch.

In addition, since the unit cost of the switch is much lower than that of the transistor, the present invention is more than using two transistors YscL1 and YscL2 to supply different scan voltages VscL1 and VscL2 in the address period. As in the second embodiment of the present invention, the use of one transistor YscL2 and the addition of two switches SW1 and SW2 reduce the cost of the driving circuit.

In addition, although the switches SW1 and SW2 are connected to the positive electrode of the VscL2 power supply in FIG. 5, the switches SW1 'and SW2' may be connected to the positive electrode of the VscL1 power supply. Hereinafter, such an embodiment will be described in detail with reference to FIG. 7.

FIG. 7 is a diagram illustrating a driving circuit and a current path according to a third embodiment for generating the driving waveform of FIG. 2.

As shown in FIG. 7, the switches SW1 'and SW2' are connected in series to a power supply for supplying a VscL1 voltage instead of the power supply VscL2, and the switch SW1 'is connected to a power supply 0V for supplying a ground voltage. The switch SW2 'is connected to the cathode of the power supply Vb supplying the voltage Vb. Then, when the switch SW1 is turned on via the path ① ”, the VscL1 voltage is applied to the scan electrode Y of the group G1, and when the switch SW2 is turned on via the path ②”, the VscL2 voltage is applied to the group G2. Is applied to the scan electrode Y.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, by dividing the plurality of scan electrodes (Y) into a plurality of groups in the scanning order, and by applying different scan voltages for each group, it is possible to stably generate an address discharge even in a discharge cell that performs addressing operation later in time. do. In this case, in order to apply different scan voltages for each group, a transistor and a separate additional power source are required. Different scan voltages are applied to the scan electrodes of the group. This reduces the cost of the drive circuit. In addition, according to the address discharge characteristics, any one of various low voltages supplied from the power supply unit can be selected and used, which can cause more stable discharge.

Claims (12)

A plurality of first electrodes, A plurality of selection circuits electrically connected to the plurality of first electrodes, for selectively applying a voltage supplied to a first end and a voltage supplied to a second end to the first electrode, and In the address period, when dividing the plurality of first electrodes into a plurality of groups including first and second groups, a first through the second end of the selection circuit to the plurality of first electrodes of the first group. A driving circuit for sequentially applying a voltage and applying a second voltage lower than the first voltage to the plurality of first electrodes of the second group through the second end of the selection circuit, The drive circuit, A first switch connected between the second end of the selection circuit and the first end of a first power source, A second switch connected between a second end of the first power supply and a second power supply supplying a ground voltage; and A third switch connected between a second end of the first power supply and a third power supply supplying a voltage supplied to a driver controlling a switch formed in the driving circuit; Including; The first voltage is sequentially applied to the plurality of first electrodes through the first power source and the second power source, and the first voltage is sequentially applied to the plurality of first electrodes through the first power source and the third power source. A plasma display device which applies two voltages. A plurality of first electrodes, A plurality of selection circuits electrically connected to the plurality of first electrodes, respectively, for selectively applying a voltage supplied to a first end and a voltage supplied to a second end to the first electrode; In an address period, a first voltage is sequentially applied to a plurality of first electrodes belonging to a first group of the plurality of first electrodes through a second end of the selection circuit, and to a plurality of first electrodes belonging to a second group. A driving circuit for applying a second voltage lower than the first voltage through a second end of the selection circuit, and And a controller configured to process the input image data to control the driving circuit. The drive circuit, A first switch connected between the second end of the selection circuit and the first end of a first power source, A second switch connected between a second end of the first power supply and a second power supply supplying a ground voltage; and A third switch connected between a second end of the first power supply and a third power supply supplying a voltage supplied to the controller; Including; The first voltage is sequentially applied to the plurality of first electrodes through the first power source and the second power source, and the first voltage is sequentially applied to the plurality of first electrodes through the first power source and the third power source. A plasma display device which applies two voltages. The method according to claim 1 or 2, The voltage supplied from the third power source is higher than the voltage supplied from the second power source, The first and third switches are turned on to apply the first voltage to the first electrode, and the first and second switches are turned on to apply the second voltage to the first electrode. . The method according to claim 1 or 2, The voltage supplied from the third power source is lower than the voltage supplied from the second power source, The first switch and the second switch are turned on to apply the first voltage to the first electrode, and the first switch and the third switch are turned on to apply the second voltage to the first electrode. Display device. delete delete delete A method of driving the plurality of scan electrodes in an address period in a plasma display device including a plurality of scan electrodes, the method comprising: Connecting a first end of a first power supply for supplying a negative first voltage to a second power supply for supplying a ground voltage, When dividing the plurality of scan electrodes into a plurality of groups, sequentially applying the first voltage to a plurality of scan electrodes belonging to a first group of the plurality of groups through the first power source and the second power source; Connecting a first end of the first power supply to a third power supply for supplying a voltage for controlling a switch in a driving circuit of the plasma display device; and Applying a second voltage to a plurality of scan electrodes belonging to a second group of the plurality of groups through the first power source and the third power source; Method of driving a plasma display device comprising a. A method of driving the plurality of scan electrodes in an address period in a plasma display device including a plurality of scan electrodes, the method comprising: Connecting a first end of a first power supply for supplying a negative first voltage to a second power supply for supplying a ground voltage, When dividing the plurality of scan electrodes into a plurality of groups, sequentially applying the first voltage to a plurality of scan electrodes belonging to a first group of the plurality of groups through the first power source and the second power source; Connecting a first end of the first power supply to a third power supply for supplying a voltage for processing an image signal in the plasma display device; and Applying a second voltage to a plurality of scan electrodes belonging to a second group of the plurality of groups through the first power source and the third power source; Method of driving a plasma display device comprising a. The method according to claim 8 or 9, The third power supply supplies a negative third voltage, and the first voltage is applied to the plurality of scan electrodes belonging to the first group before the plurality of scan electrodes belonging to the second group. . The method according to claim 8 or 9, The third power supply supplies a positive third voltage, and the second voltage is applied to the plurality of scan electrodes belonging to the second group before the plurality of scan electrodes belonging to the first group. . delete

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