KR100529083B1 - Plasma display panel and driving apparatus thereof - Google Patents

Abstract

The present invention relates to a plasma display panel and a driving device thereof. The driving apparatus of the plasma display panel according to the present invention sets the final voltage of the falling reset pulse higher than the scan pulse voltage applied at the beginning of the address period, and gradually lowers the scan pulse voltage in a part of the address period. In this way, the address discharge efficiency can be increased.

Description

Plasma display panel and its driving device {PLASMA DISPLAY PANEL AND DRIVING APPARATUS THEREOF}

The present invention relates to a plasma display panel (PDP) and a driving device thereof.

Recently, PDPs have been in the spotlight as flat panel display devices due to their high brightness, high luminous efficiency, and wide viewing angles, compared to other display devices.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

In this case, the wall charge refers to a charge formed in the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulated in the electrode. Such wall charges are not actually in contact with the electrodes themselves, but here wall charges are described as "formed", "accumulated" or "stacked" on the electrodes. In addition, wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

3 is a view showing a driving waveform according to the prior art.

As shown in Fig. 3, at the end of the reset period, the voltage of the scan electrode is lowered to the voltage VscL while maintaining the wall voltage between the scan electrode and the sustain electrode at a value close to the discharge start voltage. In the address period, scan pulses having the low voltage VscL and the high voltage VscH are sequentially applied to the scan electrodes, and at the same time, data pulses are applied to the address electrodes to cause address discharge.

On the other hand, the address discharge is determined by the density of the priming particles and the decay rate of the wall voltage formed in the discharge space. However, since the time when the scan pulse is applied after the reset discharge is generated toward the bottom of the panel from the first scan electrode toward the bottom of the panel, the density of the priming particles is gradually lowered toward the bottom of the panel. Further, the wall voltage gradually collapses toward the lower end, and the voltage on the discharge space gradually decreases. Therefore, there is a problem that the discharge delay time is longer toward the bottom, thereby reducing the address margin.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display panel and a driving device thereof capable of improving a discharge margin in an address period.

According to an aspect of the present invention, there is provided a plasma display panel including: a panel including a plurality of first electrodes and a plurality of second electrodes; And a driving circuit outputting a signal for driving the first electrode.

The drive circuit,

The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits each including a second transistor; A third transistor electrically connected to a second end of the first transistor and operative to gradually decrease a voltage of the first electrode; A fourth transistor having a first end electrically connected to a second end of the third transistor, and a second end electrically connected to a first power supply for supplying a first voltage; A first capacitor electrically connected to a second end of the third transistor and electrically connected to a second power source for supplying a second voltage; And a fifth transistor having a first end electrically connected to the first end of the capacitor and a second end electrically connected to the second end of the capacitor.

The drive circuit,

In the reset period, the third and fourth transistors are turned on to gradually lower the voltage of the first electrode to the first voltage,

During at least some of the address periods, the fifth transistor repeats the on / off operation.

In the reset period,

When the fifth transistor is turned off, the third and fourth transistors are turned on to charge the first capacitor with a voltage equal to the difference between the first voltage and the second voltage.

The non-scanning voltage is supplied by a second capacitor electrically connected between the second end of the first transistor and the first end of the second transistor to charge a substantially constant voltage.

In addition, at the beginning of the address period,

The non-scan voltage is applied to the first electrode by turning off the fourth transistor and turning on the first transistor while the third transistor is turned on;

As soon as a non-scan voltage is applied to the first electrode, a voltage equal to a third voltage among the voltages charged in the first capacitor is discharged.

In addition, during at least a part of the beginning of the address period,

Turning on the second transistor to selectively apply a voltage charged in the first capacitor discharged by the third voltage to the first electrode,

Later in the address period,

The first transistor is turned on to apply the first voltage to the first electrode while the third and fifth transistors are turned on.

A driving apparatus of a plasma display panel according to an aspect of the present invention is a driving apparatus of a plasma display panel which applies a voltage to a panel capacitor formed by a plurality of first electrodes, a plurality of second electrodes, and the first and second electrodes. ,

The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits including a second transistor; A third transistor electrically connected to a second end of the first transistor to operate to gradually decrease the voltage of the first electrode; And a second voltage connected between the second terminal of the third transistor and a first power supply for supplying a first voltage, and repeating an operation of discharging and maintaining the charged voltage in at least a part of an address period. It includes a capacitor.

The display device may further include a fourth transistor connected in parallel with the capacitor between the second terminal of the third transistor and the first power supply.

The voltage charged in the capacitor is discharged and maintained by repeating the operation in which the fourth transistor is turned on / off.

The apparatus may further include a fifth transistor electrically connected between the second power supply for supplying a third voltage corresponding to the sum of the first voltage and the second voltage and the second terminal of the third transistor.

The first transistor is turned on together with the third transistor to gradually lower the voltage of the first electrode to the third voltage, and is turned off in the address period.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.

4 is a diagram illustrating a plasma display panel device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel device according to an exemplary embodiment of the present invention includes a plasma panel 100, an address driver 200, a Y electrode driver 320, an X electrode driver 340, and a controller 400. Include.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, first electrodes Y1 to Yn (hereinafter referred to as Y electrodes), and second electrodes X1 arranged in the row direction. ˜Xn) (hereinafter referred to as X electrode).

The address driver 200 receives an address driving control signal SA from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The Y electrode driver 320 and the X electrode driver 340 receive the Y electrode driving signal SY and the X electrode driving signal SX from the controller 200 and apply them to the X electrode and the Y electrode, respectively.

The control unit 400 receives an image signal from the outside, generates an address driving control signal SA, a Y electrode driving signal SY, and an X electrode driving signal SX, respectively, and generates an address driving unit 200 and a Y electrode driving unit ( 320 and the X electrode driver 340.

5 is a driving waveform diagram applied to the plasma display panel according to the first embodiment of the present invention.

As shown in Fig. 5, according to the first embodiment of the present invention, the final voltage of the falling ramp applied in the second half of the reset period is set by the voltage Vz higher than the lower limit voltage VscL of the conventional scan pulse. During the address period, the first scan electrode Y ₁ is applied with the final voltage VscL + Vz of the falling ramp as a scan pulse, and the scan pulse voltage is gradually lowered to the last n th scan electrode Y _n . As a voltage (VscL) is applied.

FIG. 6 is a detailed circuit diagram of the Y electrode driver of the plasma display panel according to the first exemplary embodiment of the present invention for generating the driving waveform of FIG. 5.

As shown in FIG. 6, the Y electrode driver 320 according to the first exemplary embodiment of the present invention includes a rising reset driver 321, a falling reset and scan driver 322, and a sustain driver 323.

The reset driver 321 is a rising ramp that generates a reset waveform rising in a reset period. The reset driver 321 is a power supply Vset-Vs for supplying a voltage Vset-Vs, a capacitor Cset operating with a floating power supply, and a lamp switch Yrr. And a switch Ypp formed in the main path through which the sustain voltage generated by the sustain driver 323 is applied to the panel capacitor to prevent the reverse flow of the current.

Before the reset period, the capacitor Cset is charged to the voltage (Vset-Vs) by the power supply Vset-Vs to which the switch Yg supplies the voltage (Vset-Vs) at turn-on. At the beginning of the reset period, the switch Ys is turned on to apply the voltage Vs to the Y electrode. When the switch Yrr is turned on, the voltage of the panel capacitor Cp is changed by the voltage charged in the capacitor Cset. Gradually rises up to Vset).

The sustain driver 323 generates a sustain discharge pulse in the sustain period, the switches Ys and Yg connected between the power supply Vs and the ground GND, the power recovery capacitor Cyr and the switches Yr and Yf, Inductors Ly and diodes YDr, YDf, YDCH, YDCL.

Before the sustaining period, the capacitor Cyr is charged with the voltage Vs / 2. When the switch Yr is turned on in the sustaining period, resonance occurs between the inductor Ly and the panel capacitor Cp, causing the panel capacitor ( Cp is charged, and then the voltage Vs is continuously supplied to the panel capacitor Cp through the switch Ys. In addition, when the switch Yf is turned on, resonance occurs between the inductor Ly and the panel capacitor Cp to discharge the panel capacitor Cp, and thereafter, the voltage of the panel capacitor Cp is changed through the switch Yg. Keep it at 0V.

At this time, the diodes YDr and YDf are formed in the opposite direction to the body diodes of the switches Yr and Yf to block currents that may be formed by the body diodes of the switches Yr and Yf, and the diodes YDCH and YDCL. ) Clamp the second stage potential of the inductor Ly to voltage Vs and voltage GND, respectively.

The falling reset and scan driver 322 is a falling ramp that generates a falling reset waveform. The switch is formed in the main path to which the discharge voltage is applied to the panel capacitor Cp to prevent a reverse flow of the lamp switch Yfr and the current. (Ypn). The scan driver generates a scan pulse in the address period, and includes a scan IC including a plurality of selection circuits connected to a power source VscH and VscL, a capacitor Csc, a switch YscL, and a Y electrode. The scan IC includes switches SCH and SCL, and a source of the switch SCH and a drain of the switch SCL are connected to the Y electrode of the panel capacitor Cp.

In addition, the scan driver according to the first embodiment of the present invention further includes a capacitor CscL and a zener diode Dz. The switch (YscL), the capacitor (CscL) and the zener diode (Dz) are connected in parallel to the power supply (VscL), and the switch (Yfr) is the switch (YscL), the capacitor (CscL), and the zener diode (Dz) and the switch (SCL). ) Are connected in series.

Here, the panel capacitor Cp equivalently represents the capacitance component between the X electrode and the Y electrode. Also, for convenience, the X electrode of the panel capacitor Cp is displayed as being connected to the ground terminal, but the X electrode driver 340 is actually connected to the X electrode.

In FIG. 6, each of the switches is represented by an n-channel MOSFET, and each switch may include a body diode.

The process of applying the scanning pulse to the panel capacitor Cp by the driving circuit according to the first embodiment of the present invention will be described in detail with reference to FIGS. 5 to 7.

According to the first embodiment of the present invention, after the rising ramp reset waveform is applied to the Y electrode, the switch Yfr is turned on in the state where the switch YscL is turned off in the falling ramp reset period. Then, the capacitor CscL is charged while the Y electrode voltage of the panel capacitor gradually decreases through the path of the switch SCL-Yfr-capacitor CscL, and the Zener diode Dz is connected in parallel with the capacitor CscL. Since the zener diode Dz is connected, the voltage of the zener diode Dz is applied as much as the breakdown voltage Vz. Accordingly, the capacitor CscL is charged with the breakdown voltage Vz of the zener diode Dz, and the voltage of the Y electrode of the panel capacitor Cp is higher by the voltage Vz than the voltage VscL by the voltage VscL + Vz. Descends.

Thereafter, a scan pulse is applied to the Y electrode through the on and off operations of the switches SCH, SCL, and YscL during the address period.

That is, at the beginning of the address period, the switches SCL of all the selection circuits are first turned off and the switches SCH are turned on to apply the voltage charged in the capacitor Csc to all the Y electrodes. The voltage of the Y electrode is then the voltage (VscH + Vz). Next, the switch SCH of the selection circuit connected to the Y electrode to which the scan pulse is to be applied is turned off and the switches SCL and YscL are turned on while the switch Yfr is turned on to sequentially apply scan pulses to the Y electrode. do.

At this time, since the voltage Vz is charged in the capacitor CscL, the voltage VscL + Vz is applied to the first scan electrode as a scan pulse. In addition, while the switch YscL is turned on, the voltage charged to the capacitor CscL through the switch YscL is gradually discharged, so that the switch YscL is turned on and turned off (scan pulse on one Y electrode). Scan pulse voltage decreases little by little. Similarly, while the scan pulse is sequentially applied to the Y electrode, the operation of decreasing and maintaining the voltage of Node 2 by the turn on / off operation of the switch YscL is repeated. The change of the scan pulse voltage in this address period is shown in FIG.

In addition, since the voltages VscH-VscL are charged in the capacitor Csc, as the voltage of Node 2 decreases, the voltage on the high side of the selection circuit is also lowered by that much. Therefore, as shown in FIG. 7, the voltage applied to the unselected scan electrode is also gradually decreased from the voltage VscH + Vz to the voltage VscH while repeating the operation of decreasing / maintaining.

As such, when the scan pulse voltage applied to the Y electrode is gradually lowered toward the bottom of the panel, the density of the priming particles is lowered due to the time difference addressed after the reset discharge, thereby solving the problem that addressing is less likely to occur at the bottom of the panel.

In addition, the voltage difference Vz of the scan pulses applied to the first scan electrode and the nth scan electrode can be changed according to the breakdown voltage of the zener diode Dz, and the slope at which the scan pulse voltage falls is a switch YscL. It can be easily adjusted by adjusting the on-time and on-off frequency.

8 is a driving waveform diagram applied to the plasma display panel according to the second embodiment of the present invention.

As shown in Fig. 8, according to the second embodiment of the present invention, the final voltage Vnf of the falling ramp applied at the end of the reset period is ΔV higher than the falling ramp final voltage in the waveform according to the first embodiment of the present invention. Set it higher.

In addition, the address period is divided into three periods of T1, T2, and T3, the scan pulse voltage is kept constant in the T1 period, and the scan pulse voltage is gradually lowered to the voltage VscL in the T2 period, and the scan pulse is again in the T3 period. Keep the voltage constant.

FIG. 9 is a detailed circuit diagram of the Y electrode driver of the plasma display panel according to the second embodiment of the present invention for generating the driving waveform of FIG. 8.

As shown in FIG. 9, the Y electrode driver 320 according to the second exemplary embodiment of the present invention includes a rising reset driver 321, a falling reset and scan driver 322, and a sustain driver 323.

Since the configurations of the rising reset driver 321 and the sustain driver 323 are the same as those of the first embodiment of the present invention, description thereof will be omitted.

The falling reset and scan driver 322 is a falling ramp that generates a falling reset waveform, and a switch Ynf and a current connected between the ramp switch Yfr, the switch Yfr and the power supply Vnf supplying the reset final voltage. The switch Ypn is formed in the main path to which the discharge voltage is applied to the panel capacitor Cp in order to prevent the reverse flow. The scan driver generates a scan pulse in the address period, and includes a scan IC including a plurality of selection circuits connected to a power source VscH and VscL, a capacitor Csc, a switch YscL, and a Y electrode. The scan IC includes switches SCH and SCL, and a source of the switch SCH and a drain of the switch SCL are connected to the Y electrode of the panel capacitor Cp.

In addition, the scan driver according to the second embodiment of the present invention further includes a capacitor CscL. The switch YscL and the capacitor CscL are connected in parallel between the node 2 and the power supply VscL, and the switch Yfr is connected between the node 1 and the node 2. . In addition, the switch YscL and the switch Ynf are connected in series between the power source VscL and the power source Vnf.

The process of applying the scanning pulse to the panel capacitor Cp by the driving circuit according to the second embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

After the rising lamp reset waveform is applied to the Y electrode, the switch Yfr and the switch Ynf are turned on while the switch YscL is turned off in the falling lamp reset period. Then, the voltage of the Y electrode, that is, Node 1, gradually decreases to the voltage Vnf as shown in FIG. 10 through the path of the body diode of the switch SCL-switch Yfr-switch Ynf. In addition, the voltage of the node 2 increases to the voltage Vnf by a resistor CscL and a resistor (not shown) included in the gate driving circuit of the switch Ynf connected to the drain of the switch Ynf. The capacitor CscL is charged with a voltage Vnf-VscL corresponding to the difference between the voltage Vnf of the node 2 and the voltage VscL.

Next, at the beginning of the address period, the switches SCL of all the selection circuits are first turned off and the switches SCH are turned on to apply the voltage charged in the capacitor Csc to all the Y electrodes. That is, since the voltage VscH-VscL is charged in the capacitor Csc, and the voltage of the node 1 Node 1 is the voltage Vnf, the voltage VscH-VscL + Vnf is applied to the Y electrode. At this time, since the switch Yfr is turned on and the switch Ynf is turned off, the capacitor Csc and the capacitor CscL are connected in series. Therefore, the voltage charged in the capacitor CscL is discharged by ΔV when the voltage charged in the capacitor Csc is applied to the Y electrode.

In this state, scan pulses are sequentially applied to the Y electrode by turning off the switch SCH of the selection circuit connected to the Y electrode until the end of the T1 period and turning on the switch SCL with the switch Yfr turned on. Is authorized. Therefore, during the period T1, a scan pulse lower by ΔV than the voltage Vnf is applied to the Y electrode.

Next, during the period T2, a scan pulse is applied to the Y electrode while repeating the operation of turning on / off the switch YscL in the same manner as in the first embodiment of the present invention.

That is, since the voltage Vnf-VscL-ΔV is charged in the capacitor CscL, the voltage Vnf-VscL-ΔV is applied as a scan pulse to the Y electrode at the beginning of the T2 period. In addition, since the voltage charged to the capacitor CscL is gradually discharged while the switch YscL is turned on, the scan pulse voltage decreases little by little until the switch YscL is turned on and turned off.

In addition, in FIG. 10, a shape in which the voltage is reduced is shown as a straight line for convenience, but in practice, as the voltage charged in the capacitor CscL is discharged, the voltage of Node 2 is also reduced or maintained.

In addition, since the voltages VscH-VscL are charged in the capacitor Csc, as the voltage of the node 2 decreases, the voltage on the high side of the selection circuit is reduced by that much. Therefore, the voltage applied to the unselected scan electrode is also gradually decreased from the voltage VscH-VscL + Vnf to the voltage VscH while repeating the operation of decreasing / maintaining.

Next, while the switches Yfr and YscL are continuously turned on during the T3 period, the scan pulse is applied by sequentially turning on the switch SCL connected to the Y electrode. Therefore, a scan pulse of the voltage VscL is applied to the Y electrode during the T3 period.

In FIG. 9, although both the switch Ynf and the switch YscL are shown as N-type MOS transistors, the switch Ynf and the switch YscL are driven in order to drive the switch Ynf and the switch YscL as one driving circuit. One of the switches YscL may use an N-type MOSFET (or NPN transistor) and the other may use a P-type MOSFET (or PNP transistor).

As described above, according to the second exemplary embodiment of the present invention, the address discharge efficiency can be further increased by setting the scan pulse voltage at the beginning of the address period to be lower than the reset final voltage and gradually lowering the scan pulse voltage in the middle of the address period.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

For example, in the first and second embodiments of the present invention, the address period is divided into three sections T1, T2, and T3. However, the address period is different from the voltage Vnf at the Y electrode in the address period without distinguishing the address period. The scan pulse gradually decreasing from the low voltage to the voltage VscL may be applied.

As described above, according to the present invention, the address discharge efficiency can be improved by setting the final voltage of the falling reset pulse higher than the conventional one by a predetermined voltage and gradually lowering the scan pulse voltage in the address period.

In addition, the discharge efficiency at the beginning of the address period can be further increased by setting the scan pulse voltage applied at the beginning of the address period to be lower than the final voltage of the falling reset pulse.

1 is a partial perspective view of a plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the prior art.

4 is a diagram illustrating a plasma display panel device according to an embodiment of the present invention.

5 is a driving waveform diagram applied to a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of the Y electrode driver of the plasma display panel according to the first exemplary embodiment of the present invention for generating the driving waveform of FIG. 5.

7 is a detailed view of driving waveforms applied to the plasma display panel according to the first embodiment of the present invention.

8 is a driving waveform diagram applied to the plasma display panel according to the second embodiment of the present invention.

FIG. 9 is a detailed circuit diagram of the Y electrode driver of the plasma display panel according to the second embodiment of the present invention for generating the driving waveform of FIG. 8.

10 is a detailed view of driving waveforms applied to the plasma display panel according to the second embodiment of the present invention.

Claims (11)

A panel including a plurality of first electrodes and a plurality of second electrodes; And A driving circuit for outputting a signal for driving the first electrode, The drive circuit, The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits each including a second transistor; A third transistor electrically connected to a second end of the first transistor and operative to gradually decrease a voltage of the first electrode; A fourth transistor having a first end electrically connected to a second end of the third transistor, and a second end electrically connected to a first power supply for supplying a first voltage; A first capacitor electrically connected to a second end of the third transistor and electrically connected to a second power source for supplying a second voltage; And A fifth transistor having a first end electrically connected to the first end of the capacitor and a second end electrically connected to the second end of the capacitor Plasma display panel comprising a. The method of claim 1, In the reset period, And turning on the third and fourth transistors to gradually lower the voltage of the first electrode to the first voltage. The method of claim 1, And the fifth transistor repeats an on / off operation for at least a part of an address period. The method of claim 2, In the reset period, And the third and fourth transistors are turned on while the fifth transistor is turned off to charge the first capacitor with a voltage equal to the difference between the first voltage and the second voltage. The method of claim 1, And wherein the non-scanning voltage is supplied by a second capacitor electrically connected between the second end of the first transistor and the first end of the second transistor to charge a substantially constant voltage. The method according to claim 4 or 5, Early in the address period, The non-scan voltage is applied to the first electrode by turning off the fourth transistor and turning on the first transistor while the third transistor is turned on; And a voltage equal to a third voltage among the voltages charged in the first capacitor when the non-scan voltage is applied to the first electrode. The method of claim 6, During at least some of the beginning of the address period, And turning on the second transistor to selectively apply a voltage charged in the first capacitor discharged by the third voltage to the first electrode. The method according to claim 4 or 5, Later in the address period, And turning on the first transistor to apply the first voltage to the first electrode while the third and fifth transistors are turned on. In the driving apparatus of the plasma display panel for applying a voltage to a panel capacitor formed by a plurality of first electrodes, a plurality of second electrodes, the first and second electrodes, The first transistor is connected to the first electrode to apply a scanning voltage to the selected first electrode and the second terminal is connected to the first electrode to supply non-scanning voltage to the unselected first electrode. A plurality of selection circuits including a second transistor; A third transistor electrically connected to a second end of the first transistor to operate to gradually decrease the voltage of the first electrode; And A capacitor connected between the second terminal of the third transistor and a first power supply for supplying a first voltage to charge the second voltage, and the capacitor repeats the operation of discharging and maintaining the charged voltage in at least a part of an address period. Driving device for a plasma display panel comprising a. The method of claim 9, A fourth transistor connected in parallel with the capacitor between the second terminal of the third transistor and the first power source, The voltage charged in the capacitor is discharged and maintained by repeating the operation in which the fourth transistor is turned on / off. Driving device of the plasma display panel. The method of claim 9, And a fifth transistor electrically connected between a second power supply for supplying a third voltage corresponding to the sum of the first voltage and the second voltage and a second terminal of the third transistor. Turned on together with the third transistor in a reset period to gradually lower the voltage of the first electrode to the third voltage, and turn off in an address period Driving device of the plasma display panel.