KR20080047872A - Plasma display device and driving method thereof - Google Patents

Abstract

A plasma display apparatus and a driving method thereof are provided to effectively prevent the erroneous operation of circuits by applying a voltage higher than the lowest voltage to first electrodes of panel capacitors. During a reset period, a waveform for initializing discharge cells is applied. During an address period, a waveform for selecting cells to be generated discharge among the discharge cells is applied. During a sustain period, a waveform for generating discharge is applied to the selected discharge cells. During a reset period, the lowest first voltage(VscL) among voltages, which are applied to the first electrodes(Y) during the address period, and a second voltage(VscH) are alternately applied to the first electrodes.

Description

Plasma display and driving method {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is an arrangement diagram of electrodes of a plasma display panel.

2 is a diagram illustrating a driving waveform of a conventional plasma display device.

3 is another exemplary view of a driving waveform of a conventional plasma display device.

Figure 4 shows a drive circuit of the switch according to the prior art.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

6 is a driving waveform diagram according to an embodiment of the present invention.

7 is a detailed circuit diagram of an X and Y electrode driving unit forming a driving waveform of the plasma display device according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display device, and more particularly to a method of driving a plasma display panel for improving the efficiency of sustain discharge.

Recently, flat display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. Among these flat panel display devices, PDPs have advantages of higher luminance and luminous efficiency and wider viewing angles than other flat panel display devices. Therefore, the PDP is in the spotlight as a display device to replace the conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

PDP is a flat display device that displays characters or images using plasma generated by gas discharge, and according to its size, tens to millions or more pixels are arranged in a matrix form as shown in FIG. 1. Are arranged. 1 shows an electrode arrangement diagram of a plasma display panel.

As shown in Fig. 1, the PDP electrode has a matrix structure of m x n. Specifically, the address electrodes A1 to Am are arranged in the column direction and the n rows of scanning electrodes Y1 to the row direction. Yn) and sustain electrodes X1 to Xn are arranged in a zigzag. The discharge cell 12 is formed in a space partitioned by the address electrode, the scan electrode, and the sustain electrode.

2 is a diagram illustrating an exemplary driving waveform of the plasma display device according to the related art.

As shown in FIG. 2, according to the conventional method of driving a PDP, a plurality of subfields constituting one frame are each composed of a reset section, an address section, and a sustain section.

The reset section serves to erase the wall charge state of the previous sustain discharge and to set up wall charge in order to stably perform the next address discharge. The address section is a section in which wall charges are accumulated on cells (addressed cells) turned on by selecting cells turned on and cells not turned on in the panel. The sustain section is a section in which a discharge for actually displaying an image on the addressed cell is applied by alternately applying a sustain discharge pulse Vs to the X electrode and the Y electrode.

In this case, the wall charge refers to a charge formed in the wall of the discharge cell (eg, the dielectric layer) close to each electrode and accumulated in the electrode. Such wall charges are not actually in contact with the electrodes themselves, but here wall charges are described as "formed", "accumulated" or "stacked" on the electrodes. In addition, wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

On the other hand, when the video is implemented in units of frames, the driving waveform is designed based on the frame of the shortest time since the period of each frame of the signal input from the image unit is not constant due to the type of the image. Thus, as shown in Figure 2 there is a pause between the frame and the frame.

Also, since a plasma display device generally has high power consumption due to its driving characteristics, an apparatus for controlling power consumption according to a load ratio of a frame to be displayed is required. As a method of controlling such power consumption, an automatic power control (APC) A method of limiting power consumption is used. That is, the number of sustain discharges is reduced when displaying a bright screen, and the number of sustain discharges is increased when displaying a dark screen. Therefore, the pause period between the frame displaying the bright screen and the next frame becomes long.

 In general, the resting period is included between the sustaining period of the last subfield of the previous frame and the reset period of the first subfield of the next frame or the sustaining period of the last subfield of one frame. Maintains the last state of sustain discharge. That is, one of the X and Y electrodes maintains a high level of voltage, which is a sustain discharge voltage, and the other of the electrodes maintains a low voltage. In the example of FIG. 2, the X electrode maintains 0V and the Y electrode maintains voltage Vs at rest.

On the other hand, a driving circuit of a plasma display device generating a conventional driving waveform includes a reset driver which forms a waveform which rises and falls gradually in a reset section, a scan driver that applies a scan pulse to a Y electrode in an address section, and a sustain pulse in a sustain section. It includes a holding drive for generating a.

A plurality of transistors are formed in each of the driving circuits as switches, and the reset driver and the scan driver include capacitors Cset and Csc which charge a predetermined voltage in advance and supply the voltage. The capacitors Cset and Csc charge a predetermined voltage through the switch of the reset driver and the scan driver, and gradually discharge when the sustain discharge voltage is applied to the Y electrode.

In addition, a bootstrap capacitor is formed at a power supply terminal of a circuit for driving each switch FET.

4 shows a driving circuit of a switch (FET) according to the prior art.

As shown in FIG. 4, in order to drive the switch FET, the transistors Q1 and Q2 using a push-pull circuit in which a bootstrap capacitor Cboot and transistors Q1 and Q2 are connected to the gate control power supply Vg. ) To turn on / off the switch (FET). The bootstrap capacitor Cboot charges the voltage Vcc = 15V when the source voltage of the switch FET is low, and uses the voltage to drive the switch FET. Here, the power supply Vg is a bias power supply of the transistors Q1 and Q2.

As mentioned above, the voltage Vs is applied to the Y electrode during the resting period. Therefore, when the pause period is long, the bootstrap capacitor Cboot is discharged because the voltage Vs is continuously applied to the source of the switch FET. Therefore, the transistor cannot be normally driven at the start of the next frame, and since the transistor does not operate normally, the charge voltage of the capacitors Cset and Csc is lowered later.

Therefore, the normal reset voltage or the scan voltage cannot be supplied, and in order to solve this problem, it is necessary to increase the discharge time by using a large capacitor.

However, PDP is being developed in a direction of lowering the manufacturing cost in order to increase the penetration rate, but using a capacitor with a large capacity causes a problem that the manufacturing cost increases.

For this reason, a driving scheme has been developed that uses a low-capacitance capacitor but does not discharge the bootstrap capacitor (Cboot) at rest. According to this driving method, a driving waveform as shown in FIG. 3 is applied to the X electrode, the Y electrode, and the A electrode.

3 is another exemplary view of a driving waveform of a conventional plasma display device. Referring to the driving waveform of the plasma display device illustrated in FIG. 3, the lowest voltage VscL among the voltages applied to the electrodes is applied to the Y electrode and 0 V is applied to the Y electrode during the resting period. Accordingly, as the voltage VscL is applied to the Y electrode, the bootstrap capacitor of the switch driving circuit is able to be charged, thereby preventing the bootstrap capacitor from being discharged in the resting period and thus not using a large capacitor. .

However, the driving method of the plasma display device shown in FIG. 3 causes the positive wall charges to be excessively accumulated on the panel capacitor by applying the lowest voltage VscL to the Y electrode during the idle period, causing false discharge in the next frame. do.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display device for preventing abnormal discharge and abnormal operation of a circuit.

According to an aspect of the present invention for achieving the above technical problem, a driving method of a plasma display device including a plurality of first electrodes and a second electrode is provided. The driving method includes the steps of: a) applying a waveform for initializing a discharge cell in a reset period; b) applying a waveform for selecting a cell to be discharged among the discharge cells in an address period; c) applying a waveform to cause a discharge to the selected discharge cell in the sustain discharge period; And d) during the rest period, applying a second voltage, which is alternated with a lowest first voltage among the voltages applied to the first electrode, to the first electrode in the address period.

According to another aspect of the present invention for achieving the above technical problem, there is provided a plasma display device for applying a voltage to the first electrode and the second electrode, and a panel capacitor formed between the first electrode and the second electrode. The plasma display device includes a sustain driver for applying a sustain discharge voltage to the first electrode; A scan unit to selectively apply a first voltage supplied from a first power source and a second voltage supplied from a second power source and a second voltage higher than the first voltage to the first electrode; A first switch electrically connected between the first power source and the second power source; A main path connected to the first electrode through the scan unit; A second switch electrically connected between the main path and a third power supply for supplying a third voltage which is a voltage for sustain discharge; And a third switch electrically connected between the main path and a fourth power supply for supplying a fourth voltage, wherein the first switch is turned on during the resting period, and a scan unit applies the second voltage to the first electrode. do.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 5.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention. As shown in FIG. 5, a PDP according to an exemplary embodiment of the present invention includes a plasma panel 100, an address driver 200, and a Y electrode driver. 320, an X electrode driver 340, and a controller 400.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, first sustain electrodes Y1 to Yn arranged in the row direction, and second sustain electrodes X1 to Xn. .

The address driver 200 receives an address driving control signal SA from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The Y electrode driver 320 and the X electrode driver 340 receive the Y electrode driving signal SY and the X electrode driving signal SX from the controller 200 and apply them to the X electrode and the Y electrode, respectively.

The control unit 400 receives an image signal from the outside, generates an address driving control signal SA, a Y electrode driving signal SY, and an X electrode driving signal SX, respectively, and generates an address driving unit 200 and a Y electrode driving unit ( 320 and the X electrode driver 340.

Hereinafter, a driving waveform and an operation of the driving circuit of the plasma display device according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7.

6 is a driving waveform according to an embodiment of the present invention, Figure 7 is a driving circuit diagram according to an embodiment of the present invention.

The plasma display device according to an exemplary embodiment of the present invention allows the bootstrap capacitor of the driving circuit to be charged in the idle period so that the circuit can operate normally even when the idle period becomes longer. Since the bootstrap capacitor is charged when the lowest voltage is applied to each part of the driving circuit, the present invention allows the lowest voltage to be applied to each part of the driving circuit in the resting period. Also, in the present invention, in order to prevent excessive positive wall charges from accumulating on the Y electrodes, a voltage VscH that is higher by a predetermined level with respect to the lowest voltage VscL among the voltages applied to each electrode in the address period is used. Applied to the Y electrode.

That is, as shown in FIG. 6, according to the driving waveform of the plasma display device according to the exemplary embodiment of the present invention, the scan voltage VscH is applied to the Y electrode and the voltage of 0 V is applied to the X electrode during the resting period.

7 is a detailed circuit diagram of an X and Y electrode driving unit forming a driving waveform of the plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 7, the driving circuit of the plasma display device according to the exemplary embodiment of the present invention includes an X electrode driver 340 and a Y electrode driver 320. In addition, the Y electrode driver 320 includes a reset driver 321, a scan driver 322, and a sustain driver 323.

The reset driver 321 is a rising ramp that generates a reset waveform rising in a reset period. The reset driver 321 is a power supply Vset-Vs for supplying a voltage Vset-Vs, a capacitor Cset operating with a floating power supply, and a lamp switch Yrr. And a switch (Ypp) formed in the main path to which the sustain voltage generated by the sustain driver 323 is applied to the panel capacitor to prevent the reverse flow of the current. The lamp switch Yfr is connected to the power supply VscL, and a switch Ypn is formed in the main path to which the discharge voltage is applied to the panel capacitor Cp to prevent the reverse flow of the current.

Before the reset period, the capacitor Cset is charged to the voltage (Vset-Vs) by the power supply Vset-Vs to which the switch Yg supplies the voltage (Vset-Vs) at turn-on. At the beginning of the reset period, the switch Ys is turned on to apply the voltage Vs to the Y electrode. When the switch Yrr is turned on, the voltage of the panel capacitor Cp is changed by the voltage charged in the capacitor Cset. Gradually rises up to Vset).

Thereafter, when the switch Ys is turned on, the switch Yrr is turned off to apply the voltage Vs to the Y electrode, and when the switch Ys is turned off and the switch Yfr is turned on, the Y electrode is charged. The voltage gradually decreases to the voltage VscL.

The scan driver 322 generates a scan pulse in the address period and includes a power source (VscH-VscL, VscL), a capacitor (Csc), a switch (YscL) and a scan IC. The scan IC includes switches SCH and SCL. The source of the switch Sch and the drain of the switch Scl are connected to the Y electrode of the panel capacitor Cp.

In the address period, the switch YscL is always turned on. The switch SCL is turned on to apply the voltage VscL to the selected Y electrode, and the power source VscH-VscL is applied to the unselected Y electrode. The voltage charged in the capacitor Csc is applied through the switch SCH.

The sustain driver 323 generates a sustain discharge pulse in the sustain period, the switches Ys and Yg connected between the power supply Vs and the ground GND, the power recovery capacitor Cyr and the switches Yr and Yf, Inductors Ly and diodes YDr, YDf, YDCH, YDCL.

Before the sustaining period, the capacitor Cyr is charged with the voltage Vs / 2. When the switch Yr is turned on in the sustaining period, resonance occurs between the inductor Ly and the panel capacitor Cp, causing the panel capacitor ( Cp is charged, and then the voltage Vs is continuously supplied to the panel capacitor Cp through the switch Ys. In addition, when the switch Yf is turned on, resonance occurs between the inductor Ly and the panel capacitor Cp to discharge the panel capacitor Cp, and thereafter, the voltage of the panel capacitor Cp is changed through the switch Yg. Keep it at 0V.

At this time, the diodes YDr and YDf are formed in the opposite direction to the body diodes of the switches Yr and Yf to block currents that may be formed by the body diodes of the switches Yr and Yf, and the diodes YDCH and YDCL. ) Clamps the second stage potential of the power supply Vs and the inductor Ly.

In addition, the X driver 340 generates a sustain discharge pulse in the power supply Vb and the switch Xb to generate an erase pulse applied to the X electrode in the reset period, and between the power supply Vs and the ground GND. And a switch (Xs, Xg), a power recovery capacitor (Cxr) and a switch (Xr, Xf), an inductor (Lx) and a diode (XDr, XDf, XDCH, XDCL) connected to.

The switches Xs and Xg, the capacitors Cxr, the switches Xr and Xf, the inductor Lx and the diodes XDr, XDf, XDCH and XDCL of the X driver 340 are respectively sustain drivers 323 of the Y electrode. Since the same operation as the switches (Ys, Yg), the capacitor (Cyr) and the switches (Yr, Yf), the inductor (Ly) and the diodes (YDr, YDf, YDCH, YDCL) are omitted.

Here, the panel capacitor Cp equivalently represents the capacitance component between the X electrode and the Y electrode.

In addition, in FIG. 7, each of the switches is represented by an n-channel MOSFET, and each switch may include a body diode.

The process of applying the waveform of FIG. 6 to the X and Y electrodes in the resting state by the driving circuit according to the embodiment of the present invention having such a configuration is as follows.

As shown in FIG. 6, since a voltage of 0 V should be applied to the X electrode during the rest period, only the switch Xg is turned on in the X driver 340 of FIG. 7 and all the other switches are turned off.

In addition, since the voltage VscH is to be applied to the Y electrode during the pause, the switch SCH of the scan IC is turned on. Then, the lowest voltage VscL applied in the address period is first formed in the power supply VscH-VscL connected to the drain of the switch SCH, and the voltage VscH that is as high as the set value based on the voltage VscL is formed. It is formed and applied to the Y electrode of the panel capacitor Cp. FIG. 6 illustrates a falling curve in which the voltage VscL is formed to show that the voltage VscH is generated based on the voltage VscL. At this time, the section in which the falling curve is extremely short is negligible.

The lowest voltage VscL is applied to the source terminal of the switch FET shown in FIG. 4 so that a small capacity bootstrap capacitor Cboot can be used. In general, in the switch driving circuit shown in FIG. 4, the Vcc voltage connected to the bootstrap capacitor Cboot is set to about 15V higher than the voltage VscL. Therefore, when the voltage VscL is applied to the source terminal of the switch FET, the bootstrap capacitor Cboot charges about 15V.

Referring to the operation of applying the lowest voltage VscL to the source terminal of the switch FET, the switch Ypn is turned off and the switch YscL of the scan driver 322 is turned on. Then, the source voltage of the switch Ypn becomes the voltage VscL, and a current path consisting of the capacitor Csc and the switch YscL is formed. Accordingly, the voltages VscH-VscL are charged in the capacitor Csc during the resting period.

In addition, when the switch Ypp is turned on, the switch Yg is turned on so that the lowest voltage (0V) is applied to the sustain driver 323 and the reset driver 321 so that the sustain driver 323 and the reset driver ( 321) to the resting state.

Accordingly, the voltage Vset is charged to the capacitor Cset during the rest period. In addition, since the source voltage of the switches Ys, Ypp, Yrr, and Ypn is at a low voltage of 0 V or the voltage VscL, the bootstrap capacitor Cboot is charged in the switch driving circuit shown in FIG.

Therefore, the switch of the driving circuit can operate normally even when the pause period is ended and the next frame is to be driven, and sufficient voltage is also charged in the capacitors Cset and Csc, and an excessive amount (+ To prevent wall charges from building up.

Meanwhile, various driving methods of the plasma display apparatus have been disclosed. Among them, there are methods of improving low discharge or false discharge by changing a waveform applied to an address period. Therefore, at least two voltages applied in the address period are used. In this regard, the present invention may use one of the voltages (divided based on the voltage level) except for the lowest voltage applied to the Y electrode in the address period. For example, when there are four remaining voltages except the lowest voltage, the present invention randomly selects one voltage level and applies the selected level voltage to the Y electrode. As another example, the lowest voltage or the highest voltage is selected and applied to the Y electrode during the resting period. As another example, a voltage having a level difference set with respect to the lowest of the four remaining voltages is applied to the Y electrode in the resting period.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the lowest voltage is applied to each circuit portion of the driving board of the plasma display device during the resting period, thereby making the bootstrap capacitor of the switch driving circuit chargeable, and a voltage higher than the lowest voltage is constant. By applying the first electrode of the panel capacitor to reduce the capacity of the bootstrap capacitor of each circuit portion, it is possible to effectively prevent abnormal discharge or abnormal operation of the circuit when an abnormal image is input.

Claims (8)

In the driving method of a plasma display device including a plurality of first electrodes and a second electrode, a) applying a waveform for initializing the discharge cells in the reset period; b) applying a waveform for selecting a cell to be discharged among the discharge cells in an address period; c) applying a waveform to cause a discharge to the selected discharge cell in the sustain discharge period; And d) during the rest period, applying a second voltage alternated with the lowest first voltage among the voltages applied to the first electrode to the first electrode in the address period; Method of driving a plasma display device comprising a. The method of claim 1, In step d), when the second voltage has a plurality of voltage levels, arbitrarily setting one level and applying the set level voltage to the first electrode. A method of driving a plasma display device. The method of claim 1, In step d), when the second voltage has a plurality of voltage levels, applying the lowest level voltage or the highest level voltage among the second voltages to the first electrode. A method of driving a plasma display device. The method of claim 1, In step d), when the second voltage has a plurality of voltage levels, applying a voltage having a fixed level difference with respect to the first voltage among the second voltages to the first electrode. A method of driving a plasma display device. A plasma display device for applying a voltage to a panel capacitor formed between a first electrode and a second electrode and the first electrode and the second electrode, A sustain driver for applying a sustain discharge voltage to the first electrode; A scan unit to selectively apply a first voltage supplied from a first power source and a second voltage supplied from a second power source and a second voltage higher than the first voltage to the first electrode; A first switch electrically connected between the first power source and the second power source; A main path connected to the first electrode through the scan unit; A second switch electrically connected between the main path and a third power supply for supplying a third voltage which is a voltage for sustain discharge; And A third switch electrically connected between the main path and a fourth power supply for supplying a fourth voltage; During the off-season, The first switch is turned on and the scan unit applies the second voltage to the first electrode. Plasma display device. The method of claim 5, The first power source includes a first capacitor, The first switch is turned on to charge the first capacitor Plasma display device. The method of claim 5, A reset driver connected between the contacts of the second and third switches and the scan unit, the reset driver including a second capacitor charging a fifth voltage and a fourth switch applying a gradually increasing reset waveform to the first electrode More, During the rest period, To turn on the third switch to charge the second capacitor Plasma display device. The method according to any one of claims 5 to 7, Further comprising a fifth switch located on the main path, During the rest period, Turning off the fifth switch to block the main path Plasma display device.

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