KR100590070B1 - Plasma display device and driving method thereof - Google Patents

Abstract

The plasma display device according to the present invention applies a first voltage to a first electrode of a discharge cell to be turned on and electrically connected to a plurality of first electrodes, respectively, and is higher than the first voltage to a first electrode of a discharge cell to be turned on. And a plurality of selection circuits for selectively applying a second voltage, and a driving circuit for gradually lowering the voltage of the first electrode from the second voltage to the third voltage in the reset period. In this case, each of the plurality of selection circuits includes a first transistor electrically connected between a first power supply for supplying the first voltage and the first electrode, a second power supply for supplying the second voltage, and the second power supply. And a second transistor electrically connected between the first electrode, and in the reset period, the second transistor is turned on to change the voltage of the first electrode to the second voltage. In general, in the reset period, the first transistor of the selection circuit is always on, but according to the present invention, after the second transistor of the selection circuit is turned on to change the voltage of the scan electrode Y, the voltage of the first electrode is gradually decreased. By doing so, stress and temperature of the first transistor can be reduced.

PDP, electrode, reset, falling, non-scanning voltage, selection circuit

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a driving waveform diagram of a conventional plasma display device.

2 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

3 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention.

4 is a driving circuit diagram for generating the driving waveform of FIG. 3.

5A to 5C are diagrams showing current paths in respective modes of the driving circuit of FIG. 4 for generating the driving waveform of FIG.

The present invention relates to a driving method of a plasma display device including a plasma display panel (PDP).

In the plasma display panel of the AC plasma display device, scan electrodes and sustain electrodes that are parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a driving waveform diagram of a conventional plasma display device.

In general, a display panel of a plasma display device is driven by dividing one frame into a plurality of subfields having respective weights. As shown in FIG. 1, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cell.

In this falling period of the reset period, as shown in FIG. 1, the voltage applied to the scan electrode Y is gradually reduced to the voltage Vnf, so as to be between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address. A weak discharge is caused between the electrodes A. By this weak discharge, the wall charge for addressing the scan electrode Y, the sustain electrode X, and the scan electrode Y and the address electrode A is set. At this time, the voltage of the scan electrode Y is generally reduced from the voltage Vs to the voltage Vnf, in order to use the power supply Vs used for sustain discharge without using an additional power supply.

However, when the voltage between the scan electrode Y and the address electrode A or between the scan electrode Y and the sustain electrode X is equal to or greater than the discharge start voltage in the discharge cell, the scan electrode and the address electrode or between the scan electrode and the sustain electrode Discharge occurs between. That is, while the voltage of the scan electrode Y gradually decreases, discharge occurs when the voltage between the two electrodes exceeds the discharge start voltage by the applied voltage and the wall voltage formed on both electrodes. That is, since discharge does not occur in the initial portion of the falling period, it is not necessary to reduce the voltage of the scan electrode from the voltage Vs to the scan electrode in the falling period as shown in FIG. If the start voltage of the scan electrode is high in the falling period, the falling slope becomes large.

In general, the weaker the discharge occurs in the cell as the slope of the voltage of the electrode gradually changes over time, the stronger the discharge occurs, the background luminance is increased.

An object of the present invention is to provide a plasma display device and a driving method thereof capable of reducing background luminance in a reset period.

According to an aspect of the present invention, there is provided a method of driving one frame divided into a plurality of subfields in a plasma display device including a plurality of first electrodes and a plurality of second electrodes. The driving method includes changing a voltage of the first electrode to a second voltage lower than the first voltage in a state in which a first voltage is applied to the first electrode in a reset period, and then changing the third voltage from the second voltage to a third voltage. Gradually decreasing to a voltage, and applying a fourth voltage to a first electrode to be selected while maintaining the voltage of the first electrode at the second voltage in an address period.

The driving method may further include gradually increasing a voltage of the first electrode from a fifth voltage to a sixth voltage in a reset period, wherein the first voltage is the same voltage as the sixth voltage. Can be.

The driving method may further include alternately applying the first voltage and a fifth voltage lower than the first voltage to the first electrode in the sustain period.

According to another aspect of the present invention, a plasma display device is provided. The display device includes a plurality of first electrodes and a plurality of second electrodes, each of which is formed on a plasma display panel in which a capacitive load is formed by the first electrode and the second electrode, and the plurality of first electrodes, respectively. A plurality of selection circuits for applying a first voltage to a first electrode of a discharge cell to be electrically connected and turned on, and selectively applying a second voltage higher than the first voltage to a first electrode of a discharge cell not to be turned on, and a reset period And a driving circuit for gradually decreasing the voltage of the first electrode from the second voltage to the third voltage.

In this case, each of the plurality of selection circuits includes a first transistor electrically connected between a first power supply for supplying the first voltage and the first electrode, a second power supply for supplying the second voltage, and the second power supply. And a second transistor electrically connected between the first electrodes, wherein in the reset period, the second transistor is turned on to change the voltage of the first electrode to the second voltage.

The driving circuit may further include a third transistor having a first end electrically connected to the first transistor of the selection circuit and a second end electrically connected to the first power supply. The second transistor may be turned off and the first and third transistors may be turned on so that the voltage of the first electrode may be gradually decreased from the second voltage to the third voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.

2 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and generally have one end connected in common to each other. The plasma display panel 100 includes a substrate (not shown) on which the sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a substrate (not shown) on which the address electrodes A1 to Am are arranged. Is done. The two substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell. The structure of the plasma display panel 100 is an example, and a panel having another structure to which the driving waveform described below may be applied may also be applied to the present invention.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an address electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

Hereinafter, a driving waveform applied to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn in each subfield will be described with reference to FIG. 3. The following description will be made based on the discharge cells formed by one address electrode, sustain electrode and scan electrode. In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

3 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention. In FIG. 3, only two subfields of the plurality of subfields are illustrated and represented as a first subfield and a second subfield, respectively. The reset period of the first subfield is shown as consisting of a rising period and a falling period, and the reset period of the second subfield is shown as being a falling period.

In the rising period of the reset period of the first subfield, the scan electrode Y is increased from the Vs voltage to the Vset voltage while the sustain electrode X is held at 0V. Then, a weak reset discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively, and negative wall charges are accumulated on the Y electrode, and the address electrode A and the sustain electrode X are accumulated. Positive wall charges accumulate at).

In the falling period of the reset period of the first subfield, the scan electrode Y is reduced from the VscH voltage to the Vnf voltage. At this time, a reference voltage (assuming 0 V in FIG. 3) is applied to the address electrode A, and the sustain electrode X is biased to the Ve voltage. Then, while the voltage of the scan electrode Y decreases, a weak reset discharge occurs between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A. The negative wall charges formed and the positive wall charges formed on the X and A electrodes are erased. At this time, the VscH voltage is a non-scanning voltage applied to the scan electrode Y which is not selected in the address period as described later. Therefore, when the falling start voltage of the scan electrode Y is set to a VscH voltage lower than the Vs voltage in the falling period as in the embodiment of the present invention, the falling slope can be set more gently in the predetermined falling period, thereby reducing the background luminance. In addition, strong discharge in the falling period can be prevented, and the falling period can be shortened. Also, by setting the falling start voltage to the VscH voltage, no additional power source is required.

Next, in the address period of the first subfield, a scan pulse having a VscL voltage is sequentially applied to the scan electrode Y to select a discharge cell, and the scan electrode to which the VscL voltage is not applied is biased to the VscH voltage. At this time, the VscL voltage is called a scan voltage, and the VscH voltage is also called a non-scan voltage. In addition, an address pulse having a Va voltage is applied to an address electrode A passing through a discharge cell to be selected from among a plurality of discharge cells formed by the scan electrode Y to which the VscL voltage is applied. A) biases to a reference voltage (0V in FIG. 3). Then, an address discharge occurs in the discharge cell formed by the address electrode A applied with the Va voltage and the scan electrode Y with the VscL voltage, and positive wall charges are formed on the scan electrode Y. A negative wall charge is formed in the sustain electrode X. In addition, a negative wall charge is also formed on the address electrode A. FIG.

Subsequently, in the sustain period of the first subfield, the sustain discharge pulse of the Vs voltage is applied to the scan electrode Y and the sustain electrode X in order. Then, when the wall voltage is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period, the discharge is generated at the scan electrode Y and the sustain electrode X by the wall voltage and the Vs voltage. Happens. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. .

In this manner, when the sustain period of the first subfield ends, the second subfield starts. In the reset period of the second subfield, the reset period of the second subfield is performed only in the falling period. In the reset period of the second subfield, the scan is performed while the sustain discharge pulse of the voltage Vs is applied to the scan electrode Y in the sustain period of the first subfield. The voltage of the electrode Y is reduced to the VscH voltage and then gradually decreased from the VscH voltage to the Vnf voltage.

At this time, when sustain discharge has occurred in the sustain period of the first subfield, negative (-) wall charges are formed on the scan electrode (Y), and positive (+) wall charges are formed on the sustain electrode (X) and the address electrode (A). When the discharge start voltage is exceeded with the wall voltage formed in the cell while the voltage of the scan electrode Y is gradually decreasing, the weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the scan electrode Y is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield is the first subfield. It becomes substantially the same as the wall charge state after the falling period of.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, no discharge occurs when the voltage of the scan electrode Y decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained as it is.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge.

Next, a driving circuit capable of generating a driving waveform according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 4.

4 is a driving circuit diagram for generating the driving waveform of FIG. 3. In the following, each transistor may be formed with a body diode having an anode connected to a source and a cathode connected to a drain.

As shown in FIG. 4, the scan electrode driver 500 includes a rising reset part 501, a falling reset part 502, a scan driver 503, and a sustain discharge part 504. The scan driver 503 includes a plurality of selection circuits 510 respectively connected to the plurality of scan electrodes Y. In FIG. 4, only one scan electrode Y and one selection circuit 510 are provided for convenience of description. Shown. The capacitive component formed by the sustain electrode X adjacent to the scan electrode Y is illustrated as a panel capacitor Cp.

The rising reset unit 501 includes a diode Dset, a capacitor Cset, and a transistor Ypp and Yrr, and the voltage Vs from the voltage Vs to the scan electrode Y are set. Apply a voltage that gradually rises to the voltage.

The capacitor Cset has a cathode connected between the source of the transistor Ypp and the drain of the transistor Yrr, and the drain of the transistor Ypp and the source of the transistor Yrr are respectively connected to the second node N2. At this time, the capacitor Cset is charged to the voltage (Vset-Vs) when the transistor Yg described below is turned on, and the transistor Yrr is set to the voltage of the panel capacitor Cp at turn-on. A small current flows from the drain to the source to slowly rise to voltage.

And diode (Dset) is (Vset-Vs) It is connected between the power supply (Vset-Vs) supplying the voltage and the contact of the drain of the transistor (Yrr) and the capacitor (Cset) to block the current path to the capacitor (Cset)-diode (Dset)-power supply (Vset-Vs) Let's do it.

The falling reset part 502 includes transistors Ynp and Yfr, and Vnf at the voltage VscH in the panel capacitor Cp. Apply a voltage falling down to the voltage. A drain of the transistor Yfr is connected to the first node N1 and a source of the transistor Yfr is connected to a power supply Vnf supplying a voltage Vnf which is the final voltage of the falling period. The transistor Yfr operates so that a minute current flows from the drain to the source so as to gradually decrease the voltage of the Y electrode to the voltage Vnf at turn-on. At this time, the transistor Ynp is Vnf. It cuts off the current path towards power source GND-transistor Yg-transistor Ypp-transistor Ynp-transistor Yfr that can be formed when the voltage is negative.

The scan driver 503 includes a selection circuit 510, a diode Dsch, a capacitor Csch, and a transistor YscL, and sequentially includes VscL at the Y electrode. Apply voltage.

In general, a selection circuit 510 is connected to each of the Y electrodes Y1 to Yn in the form of an IC so that the plurality of Y electrodes Y1 to Yn may be sequentially selected in the address period. The driving circuit of the scan electrode driver 500 is commonly connected to the Y electrodes Y1-Yn.

The selection circuit 510 includes transistors Sch and Scl, the source of the transistor Sch and the drain of the transistor Scl are connected to the Y electrode of the panel capacitor Cp, and the source of the transistor Scl. Is connected to the first node N1.

The capacitor Csch is connected between the drain of the transistor sch and the first node N1, and the diode Dsch is a power source VscH1 for supplying a voltage VscH1 and a contact between the capacitor Csch and the drain of the transistor Sch. ) Is connected between. The capacitor Csch is charged with the voltage VscH at the time of turning on the transistor Yg described below, and the first end of the capacitor Csch is connected to the drain of the transistor Sch, and the second end is connected to the first node N1. ) The transistor YscL is connected between the first node N1 and the power supply VscL1 supplying the VscL1 voltage and supplies the VscL1 voltage to the Y electrode forming the discharge cell to be selected. That is, in the address period, the transistor Sch is turned on to apply the VscH voltage to the unselected Y electrode, and the transistor scl is turned on to apply the VscL1 voltage to the Y electrode to be selected. In addition, according to an embodiment of the present invention, the transistor Sch is turned on in the falling period to discharge the voltage stored in the capacitor Csch, thereby gradually decreasing the voltage of the scan electrode Y from the VscH voltage in the falling period. .

The sustain discharge unit 504 includes transistors Ys and Yg, and applies a Vs voltage and a 0V voltage to the scan electrode Y.

Transistor Ys is connected to a power source Vs whose drain is supplying the voltage Vs and source is connected to the third node N3, transistor Yg is connected to the third node N3 and the source is 0V. It is connected to the power supply (0V) that supplies. In addition, a power recovery circuit (not shown) may be connected to the third node N3 to recover and reuse reactive power generated by the sustain discharge pulse in the sustain period.

When the VscL voltage is lower than the Vnf voltage, a current path may be formed through the body diode of the transistor Yfr when the transistor YscL is turned on. In order to block this current path, as shown in FIG. 4, a transistor Yfr1 may be further formed in which a body diode is formed in a direction opposite to the body diode of the transistor Yfr. In addition, a diode may be connected instead of the transistor Yfr1.

Hereinafter, a method of generating a driving waveform in the falling period of the reset period of FIG. 3 using the driving circuit of FIG. 4 will be described in detail with reference to FIGS. 5A to 5C. Only the voltage applied to the scan electrode Y in the reset period of the first subfield among the drive waveforms of FIG. 3 will be described.

5A to 5C are diagrams showing current paths in respective modes of the driving circuit of FIG. 4 for generating the driving waveform of FIG. 5A to 5C, only an operation process for generating a driving waveform in the reset period will be described. In the driving circuit of FIG. 4, the current path from the third node N3, the second node N2, the first node N1, and the panel capacitor Cp to the scan electrode Y is the body diode of the transistor Ypp. And through the body diodes of the transistor Ynp and the transistor Scl. In addition, the current paths of the panel capacitor Cp to the scan electrode Y, the first node N1, the second node N2, and the third node N3 may include a transistor Scl, a body diode of the transistor Ynp, and It is formed through the transistor Ypp. In the following, these two current paths are referred to as "main paths". The transistors Ypp, Ynp and Scl are turned on when the main path is formed.

First, as shown in FIG. 5A, first, the transistors Ynp, Ypp, and Yg are turned on before the reset period begins, and the capacitor Csch is charged with the VscH voltage (A). The transistor Yg is turned on, and the capacitor Cset is charged with the voltage (Vset-Vs) (B). Although not shown in the figure, the capacitor Cre is charged with the voltage Vs / 2. The transistor Yg is turned on before the reset period begins, and a ground voltage is applied to the scan electrode Y through the main path.

As shown in Fig. 5B, at the beginning of the rising period of the reset period, the transistor Ys is turned on and maintained at the voltage Vs at the scan electrode Y through the power supply Vs and the main path (path ①).

Next, in the rising period of the reset period, the transistor Yrr is turned on and the transistor Ypp is turned off, through the paths of the power supply Vs, the transistor Ys, the capacitor Cset, and the transistors Yrr, Ynp, scl. The voltage of the scan electrode Y gradually increases (path ②). At this time, the voltage of the scan electrode Y rises to the voltage Vset by the voltage Vs of the power supply Vs and the voltage (Vset-Vs) charged in the capacitor Cset.

As shown in FIG. 5C, at the beginning of the falling period of the reset period, the transistors Yg and sch are turned on and the transistors Yrr and scl are turned off so that the power source Vs, the transistors Yg, Ypp, Ynp, and the capacitor ( The voltage VscH is applied to the scan electrode Y through the paths of Csch and transistors (path ③). That is, as shown in FIG. 3, the voltage of the scan electrode Y is rapidly decreased from the Vset voltage to the VscH voltage.

Next, in the falling period of the reset period, the transistors Yfr and scl are turned on and the transistors Yg and sch are turned off. Then, the voltage of the scan electrode Y gradually decreases to the Vnf voltage through the paths of the transistors scl and Yfr (path ④).

In the conventional driving waveform, the transistor scl should always be turned on when the voltage is increased or decreased on the scan electrode Y in the reset period. However, in the exemplary embodiment of the present invention, the voltage of the scan electrode Y is decreased from the voltage of the scan electrode Y to the voltage Vnf from the scan electrode Y by using the capacitor Csch charged with the VscH voltage in the falling period. In this case, since the transistor scl is turned off and the transistor sch is turned on as described above, the stress of the circuit element scl in the selection circuit 510 can be reduced.

As described above, the above-described current paths (paths 1 to 4) describe the reset period of the first subfield among the driving waveforms of FIG. 3, and the current paths (paths 1 to 4) are implemented only by the current path shown in FIG. Can be.

In the exemplary embodiment of the present invention, the driving waveform shown in FIG. 3 is described as an example. However, unlike the driving waveform of FIG. 3, the reset period of all subfields may be applied to a general driving waveform including a rising period and a falling period. have.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, by lowering the start voltage of the scan electrode to the VscH voltage lower than the Vs voltage in the falling period, the falling slope becomes gentle, preventing strong discharge in the falling period and reducing the background luminance.

In general, in order to implement a driving waveform applied in the reset period, the transistor scl of the selection circuit is always turned on. However, in the present invention, a transistor in which the VscH voltage is stored in the fall period is used and the transistor sch of the selection circuit is used. The stress of the circuit element scl is reduced by turning on and gradually decreasing the voltage of the scan electrode Y to the voltage VscH.

Claims (7)

In a plasma display device including a plurality of first electrodes and a plurality of second electrodes, wherein a plurality of cells are formed by the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the reset period, after the first voltage is applied to the plurality of first electrodes, the voltage of the first electrode is changed to a second voltage lower than the first voltage, and then gradually increased from the second voltage to the third voltage. Reduction step, and In the address period, applying a fourth voltage lower than the second voltage to the first electrode of the cell to be selected, and applying the second voltage to the first electrode to which the fourth voltage is not applied. Method of driving a plasma display device comprising a. The method of claim 1, In the reset period, gradually increasing the voltage of the first electrode from a fifth voltage to a sixth voltage The driving method of the plasma display device further comprising. The method of claim 2, And the first voltage is equal to the sixth voltage. The method of claim 1, Alternately applying the first voltage and a fifth voltage lower than the first voltage to the first electrode in the sustain period; The driving method of the plasma display device further comprising. A plasma display panel including a plurality of first electrodes and a plurality of second electrodes, and a plurality of cells formed by the first electrode and the second electrode, and A first transistor connected to a first power supply for supplying a first voltage and a second transistor connected to the first electrode to apply the first voltage to a first electrode of a selected cell at turn-on and a first transistor A stage is connected to a second power supply for supplying a second voltage higher than the first voltage and a second stage is connected to the first electrode to apply the second voltage to a first electrode of a cell that is not selected at turn-on. A plurality of selection circuits each including a second transistor, and A driving circuit that gradually reduces the voltage of the plurality of first electrodes from the second voltage to a third voltage in a reset period Including; And after the second transistor is turned on in the reset period to change the voltage of the first electrode to the second voltage, the voltage of the plurality of first electrodes is reduced to the third voltage. delete The method of claim 5, The drive circuit, A third transistor electrically connected to a first transistor of the selection circuit, a second end connected to the first power source, and a third transistor operable to gradually decrease voltages of the plurality of first electrodes More, In the reset period, the second transistor is turned off and the first and third transistors are turned on so that the voltage of the first electrode is gradually decreased from the second voltage to the third voltage.

Images