JP2003195805A - Driving method for plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method which can realize stable address discharge by suppressing a decease in contrast due to reset discharge or securely performing the reset discharge and erasure discharge without causing any decrease in contrast as a driving method for a plasma display panel. <P>SOLUTION: A first field in which display is made by discharge between each second electrode and one first electrode adjacent to the second electrode and a second field in which display is made by discharge between each second electrode and the other first electrode adjacent to the second electrode are temporally separated, and the first field and second field each have a reset period, an address period, and a maintained discharge period; and a pulse which varies in applied voltage value with time is applied in the reset period to cause discharge. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for a plasma display panel (PDP).

The PDP, which is a self-luminous display device, has good visibility, is thin, and is capable of large-screen display, and is therefore attracting attention as a next-generation display device replacing the CRT. In particular, the surface discharge AC type PDP is expected to be used as a display device compatible with high-definition digital broadcasting because it can have a large screen, and a high image quality surpassing that of a CRT is required.

Higher image quality includes higher definition, higher gradation, higher brightness, and higher contrast. Higher resolution is achieved by making the pixel pitch finer, and higher gradation is achieved by increasing the number of subfields in the frame. Higher brightness can be achieved by increasing the amount of visible light obtained from a constant power and increasing the number of sustain discharges. Further, the high contrast is achieved by reducing the reflectance of external light on the surface of the display panel and reducing the light emission during black display that does not contribute to the display light emission.

[0004]

2. Description of the Related Art FIG. 10 is a schematic configuration diagram of a surface discharge type PDP, which shows a configuration of a PDP of a system for which display is performed between all sustain discharge electrodes, which the applicant of the present invention has already filed.
(Japanese Patent Laid-Open No. 9-160525) The PDP 1 is formed so that the sustain discharge electrodes X1 to X3 and Y1 to Y3 arranged in parallel on one substrate and the sustain discharge electrodes formed on the other substrate intersect with the sustain discharge electrodes. The address electrodes A1 to A4 are formed, and the partition walls 2 are arranged in parallel with the address electrodes and partition the discharge space. Discharge cells are formed in respective regions defined by the sustain discharge electrodes adjacent to each other and the address electrodes intersecting with the sustain discharge electrodes, and fluorescent bodies for obtaining visible light are provided. In addition, a gas for causing a discharge is sealed between both substrates. In this figure, for the sake of simplicity, three sustain discharge electrodes are provided and three address electrodes are provided.

In the PDP having this structure, since each sustain discharge electrode can perform sustain discharge between the sustain discharge electrodes on both sides thereof, the gaps (L1 to L) between all electrodes are formed.
All of 5) are display lines. For example, the X1 electrode and the Y1 electrode form the display line L1, and the Y1 electrode and the X2 electrode form the display line L2.

FIG. 11 is a sectional view taken along the address electrodes of the PDP of FIG. 10, where 3 is a front substrate, 4 is a rear substrate,
D1 to D3 respectively indicate discharge between the electrodes. Specifically, the discharge D1 can be generated by applying a voltage between the Y1 electrode and the X1 electrode. Further, a discharge D2 can be generated by applying a voltage between the Y1 electrode and the X2 electrode, and similarly, a discharge D2 can be generated between the X2 electrode and the Y2 electrode.
Can raise 3. In this way, by utilizing one electrode for the display on both sides of the electrode, it is possible to reduce the number of electrodes to achieve high definition and reduce the drive circuits for those electrodes.

FIG. 12 is a diagram showing the structure of a frame in the PDP of FIG. One frame is composed of two fields, a first field and a second field. In the first field, odd display lines (L
1, L3, L5), and the second
In the field, display is performed on the even-numbered display lines (L2, L4) to configure one-screen display.
Further, each field is composed of a plurality of subfields having a predetermined luminance ratio, and by selectively emitting light in these subfields according to display data,
The gradation, which is the difference in brightness for each pixel, is expressed. Then, each subfield is maintained based on the reset period for equalizing the cell states which are different depending on the display state in the immediately preceding subfield, the address period for writing new display data, and the written display data. It is composed of a sustain discharge period in which light emission display is performed by discharge.

FIG. 13 is a waveform diagram showing a conventional driving method in the PDP shown in FIG. 10, showing an arbitrary subfield in the first field.

In the reset period, a reset pulse having a voltage Vw exceeding the discharge start voltage is applied to all X electrodes, and discharge is started between the adjacent Y electrodes. As a result, the first discharge (reset discharge) is performed on all the display lines (L1 to L5), and wall charges due to positive ions and electrons are formed in the discharge cells. Next, when the reset pulse is removed and each electrode is held at the same potential, the second discharge (self-erasing discharge) is generated again due to the potential difference due to the wall charges themselves formed on the electrodes. At this time, since the electrodes have the same potential, positive ions and electrons formed by the discharge are recombined in the discharge space, and the wall charges disappear. By this discharge, the wall charge amount in all display cells can be made substantially uniform. (Uniformization of wall charge distribution) Next, in the address period, the voltage is sequentially applied from the Y1 electrode.
A scanning pulse composed of Vy is applied. At the same time, an address pulse having a voltage Va is applied to the address electrodes according to the display data to start the address discharge. that time,
In the first field, a pulse composed of the voltage Vx is supplementarily applied to the X1 electrode, which is an electrode pair for displaying on the Y1 electrode, and the discharge generated between the address electrode and the Y1 electrode is not applied to the X1 electrode. Transition between Y1 electrodes. As a result, wall charges required to start the sustain discharge are formed near the X1 electrode and the Y1 electrode. On the other hand, the voltage of the X2 electrode, which is an electrode pair that forms a line not displaying, is maintained at 0V, which prevents discharge from occurring on the X2 electrode side. Similarly, first, address discharge is sequentially performed on the odd-numbered Y electrodes.

After the address discharge by the odd-numbered Y electrodes is completed, a scanning pulse is applied to the Y2 electrode. At this time, a pulse having a voltage Vx is similarly applied to the X2 electrode, which is an electrode pair for performing display on the Y2 electrode, and the X3 electrode (not shown) is maintained at 0 V like the X1 electrode. Similarly, address discharge is sequentially performed on even-numbered Y electrodes, and address discharge is performed on odd display rows of the entire screen.

Next, in the sustain discharge period, sustain pulses of the voltage Vs are alternately applied to the X electrodes and the Y electrodes. At this time, the potential difference between the electrode pair of the line not displaying is 0V
By setting the phase of the sustain pulse so that, the discharge is prevented from occurring in the non-display line. For example,
Sustain pulses having different phases are applied to the pair of the X1 electrode and the Y1 electrode for displaying in the first field.
The sustain pulse has the same phase between the Y1 electrode and the X2 electrode which are the electrode pair of the non-display line. In this way, the display in one subfield is performed.

In FIG. 13, Vs is a voltage required for sustaining discharge and is normally set to about 170V. Vw is 3 as a voltage exceeding the discharge start voltage.
The scanning pulse −Vy is set to about −150V, and the address pulse Va is set to about 60V.
The total of the absolute values of Va and Vy is set to be equal to or higher than the discharge start voltage between the address electrode and the Y electrode. Further, Vx is about 50 V, which is set to a value at which the discharge between the address electrode and the Y electrode can move to the X electrode side to form sufficient wall charge.

[0013]

However, in the conventional driving method, in order to perform the reset discharge, the sufficient voltage pulse Vw exceeding the discharge start voltage in the discharge cell is applied, and the strong discharge occurs. The light emission that accompanies this discharge is background light emission that is irrelevant to the original image display, resulting in a reduction in contrast.

Further, it has been revealed that reset discharge may not be stably generated in all discharge cells, particularly in the case of the above-mentioned driving method in which all the sustain discharge electrodes are used as display lines. That is, although the discharge pulse is applied to all the display lines by the reset pulse applied to all the X electrodes, there is a possibility that the discharge is not generated in some cells due to the variation in the discharge start time of each discharge cell. is there.

Focusing on the X2 electrode in FIG. 11,
It is assumed that the discharge D2 between the X2 electrode and the Y1 electrode has occurred first. Then, when the charges generated by the discharge start to accumulate near the electrodes, a reverse bias is applied by the wall charges, and the effective voltage for the discharge space decreases. Specifically, wall charges due to electrons are formed on the X2 electrode side, and V applied to the electrode is
The effective voltage of the w voltage with respect to the discharge space is reduced. If the decrease in the effective voltage precedes the start of the discharge between the X2 electrode and the Y2 electrode, the reset period may end without the discharge between the X2 electrode and the Y2 electrode being performed. If the reset discharge is not performed in some of the discharge cells, the cell states cannot be made uniform, and the address discharge in the discharge cells cannot be stably generated, resulting in an erroneous display.

Even if the reset discharge can be generated in all cells, there is a possibility that the subsequent self-erase discharge is not stably generated. That is, the self-erase discharge is caused by the potential difference between the wall charges themselves formed by the reset discharge, and thus is often smaller than the reset discharge. For this reason, the wall charges formed by the reset discharge remain as they are without the self-erasing discharge occurring depending on the characteristic variations of the individual discharge cells. Alternatively, self-erase discharge may not occur because sufficient wall charges are not formed at the end of the reset discharge. as a result,
In the discharge cells where the erase discharge has not been performed, the subsequent address discharge is not normally performed, which causes an erroneous display.

As a method of solving these problems, it can be considered to raise the voltage of the reset pulse to more surely cause the discharge in all the cells. However, the further increase of the discharge voltage further increases the background light emission described above and deteriorates the contrast.

Furthermore, if the wall charge remains in the discharge cells and the address period is started due to the above reasons, another problem will occur. As described above, in the address period, the voltage Vx is applied to the X electrodes forming the display lines, and the X electrodes forming the non-display lines are held at 0 V, thereby preventing the occurrence of address discharge. However, if unnecessary wall charges remain, discharge may occur even in non-display lines.

For example, in FIG. 11, a voltage is applied to the Y1 electrode.
A scan pulse composed of Vy is applied, and an address pulse composed of voltage Va is applied to the address electrode to perform address discharge. At that time, since the voltage Vx is applied to the X1 electrode, the discharge is transferred between the Y1 electrode and the X1 electrode,
Discharge D1 is performed. At this time, X2 adjacent to the Y1 electrode
Since the electrodes are held at a voltage of 0 V, the generation of the discharge D2 should be able to be avoided. However, the discharge D2 may occur due to the bias of the residual charge due to the uncertainty of the reset discharge. As a result, negative wall charges are accumulated on the X2 electrode, and the address discharge D3 to be performed next is affected. The erroneous discharge due to the non-display electrode may occur due to variations in the discharge starting voltage among the discharge cells.

The sustain discharge in each subfield is
The discharge may spread depending on the sustain discharge voltage Vs and the cell structure. Referring to FIG. 6, when sustain discharge is performed between the electrodes X1 and Y1 and between the electrodes X2 and Y2, the electrodes Y1 and
A certain amount of wall charge is also accumulated between −X2. These are erased during the reset period of each subfield, but a part of them, especially the wall charges formed on the address electrode side, may remain without being erased. This wall charge has no effect in the field for displaying between the electrodes X1 and Y1 and between the electrodes X2 and Y2, but makes the address discharge unstable in the next field for displaying between the electrodes Y1 and X2. Cause.

According to the present invention, the reset discharge and the erase discharge are surely performed without suppressing the deterioration of the contrast due to the reset discharge or without causing the deterioration of the contrast.
An object of the present invention is to provide a driving method of a plasma display panel capable of realizing stable address discharge.

[0022]

In the method of driving a plasma display panel according to claim 1, a plurality of parallel first and second electrodes are arranged adjacent to each other, and the first and second electrodes are arranged. A method of driving a plasma display panel, wherein a plurality of third electrodes are arranged so as to intersect the electrodes of the second electrode and the second electrode.
A first field for displaying by discharge between each of the first electrodes adjacent to the first electrode, each second electrode, and each of the other first electrodes adjacent to each second electrode. And a second field for displaying by a discharge between the two, the first field and the second field each having a reset period, an address period, and a sustain discharge period. In the reset period, a pulse whose applied voltage value changes with the passage of time is applied to generate discharge.

According to the first aspect of the present invention, in the driving method in which all the sustain discharge electrodes are used for display, a weak discharge can be performed at the time of reset discharge, so that the amount of wall charges formed is small. Wall charges do not affect adjacent display lines. In addition, since the discharge is weak, the amount of light emission is small, and the contrast is not significantly lowered even though the reset discharge is performed.

In the plasma display panel driving method according to a second aspect of the present invention, after the discharge is generated by the application of the pulse, a second pulse whose applied voltage value changes with the passage of time is further erased. Try to discharge.

According to the second aspect of the present invention, the erase discharge is performed not by the self-erase discharge but by the application of a pulse whose applied voltage value changes with the passage of time.
It can be surely performed regardless of variations in the characteristics of the discharge cells and the amount of remaining wall charges. In addition, since the discharge is weak, the amount of light emission is small, and the contrast is not significantly reduced even though the erase discharge is performed.

According to a third aspect of the present invention, there is provided a method of driving a plasma display panel, wherein a pulse of a first polarity is applied to the first electrode of the one side and the first electrode of the other side is applied in the address period of the first field. A second polarity pulse is applied to the second electrode, the second electrode is sequentially applied to the second electrode.
Of the second polarity is applied to the other first electrode while the second polarity is applied to the other first electrode during the address period of the second field. The scanning pulse of the second polarity is sequentially applied to the second electrode while the pulse is being applied.

According to the present invention of claim 3, in the driving method in which all the sustain discharge electrodes are used for display, the potential difference between the non-display lines during the address period is reduced,
It is possible to prevent erroneous discharge from occurring.

In the driving method of the plasma display panel according to the fourth aspect, a plurality of parallel first and second electrodes are arranged adjacent to each other, and the first and second electrodes are arranged.
A method of driving a plasma display panel, wherein a plurality of third electrodes are arranged so as to intersect the electrodes of the second electrode, the second electrodes, and the first first electrodes adjacent to the second electrodes.
A second field for displaying by discharge between the second electrode and each second electrode, and a second field for displaying by discharge between each second electrode and each other first electrode adjacent to each second electrode. The fields are temporally separated from each other, and each of the first and second fields has a field reset period in which a discharge is performed to erase wall charges remaining at the end of the previous field, and a plurality of subfields. However, each of the plurality of subfields includes a reset period, an address period,
And a sustain discharge period.

According to the fourth aspect of the present invention, the wall charge remaining at the end of the previous field can be erased in the drive system in which all the sustain discharge electrodes are used for display.

In the plasma display panel driving method according to a fifth aspect of the present invention, the field reset period is a period for discharging between even-numbered first electrodes and odd-numbered second electrodes and an odd-numbered first electrode. Electrode and the even second
, A period of discharging between the electrodes of the odd numbered first electrode and the second electrode of the odd numbered, and a period of discharging between the first electrode of the even number and the second electrode of the even number And a period during which discharge is performed.

According to the fifth aspect of the present invention, the wall charges formed on each electrode, particularly the address electrode, can be surely erased during the field reset period.

In the method of driving a plasma display panel according to a sixth aspect of the present invention, each discharge in the field reset period is performed by applying a pulse between electrodes to perform reset discharge, and then by setting the potential of each electrode to the same potential, It is assumed that the self-erase discharge occurs due to the potential difference between the formed wall charges themselves.

According to the sixth aspect of the present invention, after the reset discharge is performed, it is possible to stably erase the wall charges by the self-erasing discharge.

In the driving method of the plasma display panel according to claim 7, the first and second fields are:
Prior to the field reset period, a field reset charge adjustment period for forming wall charges superimposed on the discharge in the field reset period is provided.

According to the present invention of claim 7, stable field reset can be performed regardless of the state of the discharge cell at the end of the field immediately before.

In the driving method of the plasma display panel according to claim 8, a step of applying a first pulse whose applied voltage value changes with the lapse of time during the field reset charge adjustment period to cause discharge, In order to adjust the amount of wall charges formed by the first pulse, a step of applying a second pulse whose applied voltage value changes with the passage of time is included.

According to the eighth aspect of the present invention, it is possible to allow the wall charges superimposed on the field reset to remain in an appropriate amount, and the discharge itself during the field reset charge adjustment period can also be a weak discharge.

In the driving method of the plasma display panel according to the ninth aspect, a plurality of parallel first and second electrodes are arranged adjacent to each other, and the first and second electrodes are arranged.
A plurality of third electrodes are arranged so as to cross the electrodes of the plasma display panel, and the method has a reset period, an address period, and a sustain discharge period. Adjacent to the second electrode and paired with the second electrode to form a display line
A pulse of the first polarity is applied to the electrodes of the
In the state where a pulse of the second polarity is applied to the first electrode adjacent to the second electrode and forming a non-display line with the second electrode,
The scanning pulse having the second polarity is sequentially applied to each second electrode.

In the plasma display panel driving method according to the tenth aspect of the present invention, the sequential scanning pulse is applied to each odd-numbered second electrode and then the sequential scanning pulse is applied to each even-numbered second electrode. To

[0040]

1 is a waveform diagram showing a first embodiment of the present invention. FIG. 1 shows an address electrode X1 in an arbitrary subfield in the first field for displaying odd lines.
The waveforms of the electrodes, the Y1 electrode, the X2 electrode, and the Y2 electrode are shown, each of which includes a reset period, an address period, and a sustain discharge period. In the following description, the X1 electrode and the X2 electrode are referred to as the X electrode, the Y1 electrode and the Y2 electrode are referred to as the Y electrode, and they are all referred to as the sustain discharge electrodes.

In the reset period, the address electrodes are set to 0 V and the positive and negative pulses are applied to the sustain discharge electrodes. That is, a pulse having a voltage −Vwx is applied to the X electrode, and a voltage Vwy is applied to the Y electrode.
Is applied. At this time, the pulse applied to the Y electrode is a dull pulse that reaches the voltage Vwy while changing the amount of voltage change per unit time. This makes X
A weak first discharge is generated between the electrode and the Y electrode.

When the rectangular wave Vw as in the prior art is applied as the applied voltage, a strong discharge is generated according to the difference Vw-Vf from the discharge start voltage Vf in the discharge cell, excessive wall charges are formed, and adjacent discharges are formed. It will affect the cell. However, the use of the blunt pulse causes each discharge cell to start discharge when the applied voltage exceeds the discharge start voltage Vf for each discharge cell, so that the generated discharge is only weak and the amount of wall charge formed. Will be a little. As a result, even if the reset discharge in a certain discharge cell precedes, it does not affect the adjacent discharge cells. Further, since the discharge is weak, the background light emission is also small.

Subsequently, a pulse having a voltage Vex is applied to the X electrode, and a pulse having a voltage -Vey is applied to the Y electrode. At this time, the pulse applied to the Y electrode is voltage −V while the voltage change amount per unit time changes.
It is a dull pulse reaching ey. As a result, the second discharge occurs, and the wall charges formed by the immediately preceding discharge are erased.

When self-erasing discharge is used as in the conventional case,
A situation in which no discharge occurs depending on the amount of wall charges formed or the characteristics of the discharge cell has occurred.
Since the discharge is forcibly caused by the voltage application of x + Vey, the erase discharge is surely performed. Further, since the applied pulse has a dull waveform, the discharge becomes weak and the contrast is not deteriorated. In addition, the above Vex
By setting + Vey to a voltage that is slightly lower than the discharge start voltage Vf, a small amount of wall charge generated by the first discharge is superposed and an erase discharge is performed.

The sustain discharge is basically carried out between the XY electrodes, but the address electrodes which are maintained at a potential lower than the sustain discharge voltage Vs during that period have wall charges of positive polarity. It is formed. In the first discharge of the present embodiment, since the negative polarity pulse is applied to the X electrode, the address − is formed by being superimposed on the wall charge remaining on the address electrode.
Discharge also occurs between the X electrodes, and the wall charges remaining near the address electrodes above the X electrodes are erased. Further, in the subsequent second discharge, since the negative polarity pulse is applied to the Y electrode, the wall charges remaining near the address electrode above the Y electrode are similarly erased.

Next, in the address period, scan pulses are sequentially applied to the Y electrodes to perform address discharge. X
Focusing on the electrodes, the voltage Vx is applied to the X electrodes that form a display line in pairs with the Y electrodes to which the scanning pulse is applied, and the address discharge is performed as in the conventional case. On the other hand, a voltage of -Vux is applied to the X electrodes forming the non-display lines, and the potential difference from the Y electrodes is reduced to prevent the address discharge from occurring in the non-display lines. It is the same as the conventional method that the sequential scanning pulse is applied to the odd-numbered Y electrodes to perform the address discharge, and then the sequential scanning pulse is applied to the even-numbered Y electrodes to perform the address discharge. .

When the address period ends, the sustain discharge period starts and the sustain pulse is alternately applied to the X electrodes and the Y electrodes, and the sustain discharge is repeated in the cells in which the address discharge has been performed in the address period. At this time, as in the conventional case, the phase of the sustain discharge pulse is set so that the sustain discharge does not occur in the non-display line.

In FIG. 1, the sum of the absolute values of -Vwx and Vwy in the reset period is set to a value exceeding the discharge start voltage between the X electrode and the Y electrode, for example -Vw.
x is -130V and Vwy is 220V. In the subsequent erase discharge, Vex is 60V and -Vey is -160V, for example. Further, Va in the address period is, for example, 60 V, -Vy of the scan pulse is, for example, -150 V, Vx of the X electrode is, for example, 50 V, -Vux is, for example, -80 V, and Vs of the sustain pulse is, for example, 170 V. Also Vex and Vx,
-Vey and -Vy may be set to the same voltage, whereby the circuit can be shared and the circuit scale can be suppressed.

FIG. 2 is a diagram showing the structure of a frame in the first embodiment of the present invention. The difference from that shown in FIG. 7 is that a field reset period is provided at the start of each field. The field reset period is for erasing wall charges remaining on the address electrode side when switching fields.

FIG. 3 is a waveform diagram showing a field reset in the first embodiment of the present invention. At time t1, a voltage of −Vy is applied to the Y1 electrode and a voltage of Vs is applied to the X2 electrode to cause discharge, and wall charges are formed. After that, when the pulse is removed and the potentials of the respective electrodes are held at the same potential, self-erasing discharge occurs due to the potential difference between the formed wall charges themselves, and the wall charges are erased. Similarly, time t
From 2 to t4, the reset discharge is sequentially performed between all the electrodes in four times to surely erase the wall charges. In this embodiment, the odd-numbered Y electrodes-even-numbered X electrodes at t1, the odd-numbered X electrodes-even-numbered Y electrodes at t2, and the odd-numbered X electrodes-odd-numbered electrodes at t3. Discharge is performed between the Y electrodes and between the even-numbered X electrodes and the even-numbered Y electrodes at t4, but in t1 to t4, the order of discharging is arbitrary.

In the above-described first embodiment, the pulse applied to the Y electrode during the first and second discharges is a blunt pulse in which the voltage change amount per unit time changes. Such a pulse waveform has a capacitance C formed between electrodes by connecting a resistor R to a switching element that outputs a pulse.
It can be easily obtained by configuring the RC circuit in combination with. And the curve of this dull pulse is
It is determined by the time constant defined by RC.

However, when the blunt pulse is used, the amount of voltage change per unit time changes with rising or falling, so that the discharge intensity varies depending on when the discharge is started. There's a problem. Therefore, it is possible to realize a very weak discharge when the discharge is started in the vicinity where the pulse starts to saturate at the set voltage, but the discharge is relatively early stage due to, for example, variations in the characteristics of the discharge cell, That is, if the discharge is started at the time when the rise or fall of the pulse is relatively steep, strong discharge may occur and a large amount of wall charges may be formed.

FIG. 4 is a waveform diagram showing the second embodiment of the present invention. In this embodiment, the pulse applied to the Y electrode during the first and second discharges is a triangular wave having a constant voltage change amount per unit time. According to the present embodiment, although the circuit configuration for producing the triangular wave is slightly more complicated than that of the first embodiment, since the slope of the pulse is constant, it is possible to reliably generate a weak discharge. .

FIG. 5 is a waveform diagram showing the third embodiment of the present invention, showing the final pulse of the sustain discharge period in the previous subfield and the reset period in the next subfield. In this embodiment, the pulse applied to the Y electrode during the first and second discharges is a blunt pulse in which the amount of voltage change per unit time changes.
This is the same as the embodiment. However, in this embodiment, a sufficient time is allowed from the fall of the final sustain pulse in the sustain discharge period of the previous subfield to the pulse application in the reset period of the next subfield.

When the sustain discharge is generated by the application of the sustain pulse, a predetermined amount of wall charge is accumulated when the discharge is completed.
Then, when a certain amount of time has passed from the end of the discharge, the formed wall charges start neutralizing with the space charges existing in the discharge space. Therefore, if the reset discharge is performed after a sufficient time has elapsed from the application of the final sustain pulse, the wall charges remaining at the end of the sustain discharge period can be erased to some extent. As a result, the subsequent reset discharge
This can be performed in a state where the residual wall charges are less, and stable reset discharge can be performed. The time t from the falling edge of the last sustain pulse to the start of the next reset discharge
1 is suitably longer than at least 1 μs, preferably 10 μs.

Further, in this embodiment, during the first discharge in the reset period, the negative polarity pulse to the X electrode and the positive polarity pulse to the Y electrode are applied at different timings. .

When a negative pulse to the X electrode and a positive pulse to the Y electrode are applied at the same time as in the first embodiment, strong discharge may occur despite the use of the dull pulse. There is. Therefore, in this embodiment, the negative pulse to the X electrode and the negative pulse to the Y electrode are applied at different timings.

As described above, the negative pulse applied to the X electrode during the first discharge has the effect of erasing the wall charges remaining on the address electrodes. In that case, as the wall charges on the address electrodes are erased, positive wall charges are formed on the X electrodes to which the negative polarity pulse is applied. When the positive second pulse is applied to the Y electrode in this state, the effective voltage between the X and Y electrodes decreases, and strong discharge can be prevented. For the purpose of simply preventing the strong discharge, there is a method of lowering the negative polarity voltage applied to the X electrode. In this case, however, sufficient erase discharge with the address electrode should be performed. Is difficult to do, which is not preferable.

The delay time t2 from the pulse application to the X electrode to the pulse application to the Y electrode is at least 5 μs.
It is appropriate to set the degree.

FIG. 6 is a waveform diagram showing a fourth embodiment of the present invention, showing only the waveform of the Y electrode during the reset period. The pulse applied to the Y electrode is a blunt pulse in which the amount of voltage change per unit time changes.

In the above-described first to third embodiments, when the second discharge is performed subsequent to the first discharge, the potential of the Y electrode, which has reached Vwy, is once lowered to 0 V at once, and then, The pulse for the second discharge was applied. However, when the Y electrode potential drops to 0V,
Positive pulse application to the X electrode and Y in association with the second discharge
When the negative pulse is applied to the electrodes at the same time, a high voltage is applied at a time between the electrodes, which may cause strong discharge.

Therefore, in the example of FIG. 6A in this embodiment, the pulse for the second discharge is immediately applied without lowering the Y electrode potential to 0V.
By doing so, it is possible to prevent a high voltage from being applied between the electrodes at once, so that it is possible to avoid strong discharge.

However, the example of FIG. 6A has a problem that the time required for the second discharge becomes long.
This is because the potential of the Y electrode is dropped from Vwy to -Vey by using a blunt pulse. Secondly
In order to reduce the time required for the second discharge, the amount of voltage change per unit time must be increased, the discharge scale in the second discharge increases, and the contrast decreases.

The example of FIG. 6 (b) corresponds to the first to third embodiments and FIG.
This corresponds to an intermediate point from the example in (a). That is, Vw
The Y electrode potential reaching y is once lowered to a potential higher than 0 V (for example, about 20 V), and then a negative pulse composed of a blunt pulse is applied.

For example, the Y electrode whose electrode potential has reached Vwy is once lowered to Vs by connecting it to the power supply Vs for sustain discharge, and the power recovery circuit connected to the Y electrode is used. A method of lowering the Y electrode potential to a predetermined potential can be easily adopted. The power recovery circuit connects an inductor to the Y electrode (or X electrode) to form a series resonance circuit together with the panel capacitance, and recovers and reuses the sustain voltage Vs applied to the electrode.
In the sustain discharge period, the sustain voltage Vs is alternately applied between the X and Y electrodes, but this operation is equivalent to charging and discharging the panel capacitance formed between the X and Y electrodes. . The power recovery circuit is for effectively utilizing this charge / discharge current, and is essential for reducing the power consumption of the PDP. By using this power recovery circuit, the Y electrode potential can be lowered without adding a new circuit.

After the Y electrode potential is lowered to a predetermined potential, it is connected to a normal obtuse waveform circuit. As a result, in this example, it is possible to shorten the time required for the second discharge without causing a strong discharge and increasing the amount of voltage change per unit time.

FIG. 7 is a waveform diagram showing the fifth embodiment of the present invention. In the present embodiment, the potential reached by the Y electrode at the end of the second discharge is set higher than the scan pulse potential −Vy.

Since the blunt pulse applied to the Y electrode during the second discharge has a negative polarity, positive wall charges are formed on the Y electrode. At this time, in the above-described first to fourth embodiments, since the Y electrode potential was lowered to −Vy which is the potential of the scanning pulse, the wall charges formed were relatively large. In the subsequent address period, a negative scan pulse is applied to the Y electrode. However, if positive wall charges remain at this time, the effective voltage of the scan pulse is lowered, and the address discharge is performed. Could hinder the stable effectiveness of the. On the contrary, when the reaching potential of the Y electrode at the end of the second discharge is too high (for example, the non-selection potential of the Y electrode −Vsc in the address period), negative wall charges are formed on the Y electrode. In this case, when the negative scanning pulse is applied to the Y electrode, the negative wall charges are superposed, and there is a possibility that even the cells to which the address pulse is not applied may be discharged.

In the present embodiment, the reaching potential of the Y electrode at the end of the second discharge is set between the selection potential −Vy and the non-selection potential −Vsc of the Y electrode in the address period to enable stable address discharge. There is. Alternatively, the voltage applied to the address pulse can be lowered if a drive margin similar to that in the conventional case can be obtained. The reaching potential of the Y electrode is equal to the selection potential of the Y electrode during the address period.
It is appropriate to set the amount of increase ΔV from Vy within the range of 0 <ΔV <20V, preferably about 10V.

FIG. 8 is a diagram showing the structure of a frame in the sixth embodiment of the present invention, and FIG. 9 is a waveform diagram showing the same embodiment. This embodiment is common to the first embodiment in that the field reset period described in FIG. 2 is provided,
The feature is that a field reset charge adjustment period is further provided prior to the field reset period.

At the end of the first field or the second field, the state of charge in each cell is various. this is,
This is because the discharge state of each field differs depending on the cell. If, at the start of the field reset period, wall charges having the opposite polarity to the applied pulse for the field reset remain, the effective voltage of the applied pulse is lowered, and stable field reset becomes difficult. . For example, in the example of FIG. 3, when positive wall charges (or negative wall charges on the X2 electrode) remain on the Y1 electrode,
The effective voltage applied between the Y1-X2 electrodes is reduced, and stable discharge becomes impossible.

In this embodiment, a field reset charge adjustment period is provided prior to the field reset period, and wall charges of the same polarity are positively formed with respect to the pulse applied during the field reset period. .

FIG. 9 is a concrete waveform diagram. In the field reset charge adjustment period, first, a negative pulse is applied to the X1 electrode and a positive pulse is applied to the Y1 electrode. The sum of the voltage Vwx applied to the X1 electrode and the voltage Vwy applied to the Y1 electrode exceeds the discharge start voltage of the cells, and discharge is started in all cells. At this time, since the pulse applied to the Y1 electrode is a blunt pulse in which the amount of voltage change per unit time changes, this discharge becomes a weak discharge like the first discharge in the reset period, and the reduction in contrast can be suppressed. Due to this entire surface discharge, negative wall charges are accumulated on the Y1 electrode. However, the amount of wall charges accumulated here is large, and when the field reset period is continued as it is, the discharge becomes too large due to the superposition of wall charges. Therefore, a negative erase pulse is continuously applied to the Y1 electrode. , Adjust the amount of accumulated wall charge. This negative pulse is also a blunt pulse in which the amount of voltage change per unit time changes.

As a result, at the end of the field reset charge adjustment period, an appropriate amount of negative wall charges has been accumulated. By shifting to the field reset period in this state, the formed wall charges are superposed on the applied pulse, and the field reset can be surely executed.

[0075]

According to the present invention, it is possible to suppress a decrease in contrast, and it is possible to surely perform reset discharge and subsequent erase discharge on all display lines. As a result, the state of all cells can be surely made uniform during the reset period, stable address discharge can be realized, and erroneous display can be prevented.

[Brief description of drawings]

FIG. 1 is a waveform diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing the structure of a frame according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram showing a field reset in the first embodiment of the present invention.

FIG. 4 is a waveform diagram showing a second embodiment of the present invention.

FIG. 5 is a waveform diagram showing a third embodiment of the present invention.

FIG. 6 is a waveform diagram showing a fourth embodiment of the present invention.

FIG. 7 is a waveform diagram showing a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a frame structure according to a sixth embodiment of the present invention.

FIG. 9 is a waveform diagram showing a sixth embodiment of the present invention.

FIG. 10 is a schematic configuration diagram of a surface discharge type PDP.

11 is a sectional view taken along the address electrode A1 of the PDP of FIG.

12 is a diagram showing the structure of a frame in the PDP of FIG.

13 is a waveform diagram showing a conventional driving method in the PDP of FIG.

[Explanation of symbols]

1 PDP 2 Partition 3 Front substrate 4 Back substrate X1, X2, X3 ..., Y1, Y2, Y3 ... Sustain discharge electrodes A1, A2, A3 ... Address electrodes L1, L2, L3 ... Display line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/28 E K (72) Inventor Yoshikazu Kanazawa 4-chome Ueodachu, Nakahara-ku, Kanagawa Prefecture No. 1 No. 1 F term in Fujitsu Limited (reference) 5C080 AA05 BB05 DD03 EE29 HH04 HH05 HH07 JJ04 JJ06

Claims (10)

[Claims] 1. A plasma display in which a plurality of parallel first and second electrodes are arranged adjacent to each other, and a plurality of third electrodes are arranged so as to intersect the first and second electrodes. A method for driving a panel, comprising: a first field for displaying by discharge between each second electrode and one first electrode adjacent to each second electrode; and each second electrode And a second field for displaying by discharge between the other first electrodes adjacent to the respective second electrodes are temporally separated from each other, and the first and second fields are Plasma having a reset period, an address period, and a sustain discharge period, respectively, and applying a pulse whose applied voltage value changes with the passage of time to generate discharge in the reset period. How to drive the display panel Law. 2. A discharge is generated by applying the pulse, and then a second pulse whose applied voltage value changes with the lapse of time is further applied to perform the erase discharge. Item 2. A method for driving a plasma display panel according to item 1. 3. In the address period of the first field, a pulse of a first polarity is applied to the one first electrode and a pulse of a second polarity is applied to the other first electrode. In this state, a scanning pulse having a second polarity is sequentially applied to the second electrode, and a pulse having a first polarity is applied to the other first electrode in the address period of the second field,
The plasma display panel according to claim 1, wherein the second polarity scanning pulse is sequentially applied to the second electrode while the second polarity pulse is applied to the one first electrode. Driving method. 4. A plasma display in which a plurality of parallel first and second electrodes are arranged adjacent to each other, and a plurality of third electrodes are arranged so as to intersect the first and second electrodes. A method for driving a panel, comprising: a first field for displaying by discharge between each second electrode and one first electrode adjacent to each second electrode; and each second electrode And a second field for displaying by discharge between the other first electrodes adjacent to the respective second electrodes are temporally separated from each other, and the first and second fields are Each of the plurality of subfields has a field reset period for performing discharge for erasing wall charges remaining at the end of the previous field, and a plurality of subfields, each of the plurality of subfields having a reset period, an address period, and a sustain discharge. Including period and And a method for driving a plasma display panel, the method comprising: 5. The field reset period is a period for discharging between even-numbered first electrodes and odd-numbered second electrodes, and an odd-numbered first electrode and even-numbered second electrode. Between the odd-numbered first electrode and the odd-numbered second electrode, and between the even-numbered first electrode and the even-numbered second electrode The method for driving a plasma display panel according to claim 4, further comprising: a period during which discharge is performed by discharge. 6. Each of the discharges in the field reset period is performed by applying a pulse between the electrodes to perform the reset discharge, and then using the potential difference between the wall charges themselves formed by the reset discharge with the potential of each electrode being the same potential. The driving method of the plasma display panel according to claim 5, wherein the self-erasing discharge is accompanied. 7. The first and second fields have, prior to the field reset period, a field reset charge adjustment period for forming wall charges superimposed on discharge in the field reset period. The method for driving the plasma display panel according to claim 4. 8. The field reset charge adjustment period includes a step of applying a first pulse whose applied voltage value changes with the passage of time to generate a discharge, and a wall formed by the first pulse. 8. The method of driving a plasma display panel according to claim 7, further comprising the step of applying a second pulse whose applied voltage value changes with the lapse of time in order to adjust the amount of charge. 9. A plurality of parallel first and second electrodes are arranged adjacent to each other, and a plurality of third electrodes are arranged so as to intersect the first and second electrodes,
A driving method of a plasma display panel having a reset period, an address period, and a sustain discharge period, wherein a display line is formed adjacent to each second electrode and paired with the second electrode in the address period. The first polarity pulse is applied to the first electrode and the second electrode is adjacent to each second electrode and forms a non-display line with the second electrode.
With the pulse of the second polarity applied to the electrodes of the
A method of driving a plasma display panel, wherein a scanning pulse of the second polarity is sequentially applied to the electrodes of the. 10. The plasma according to claim 9, wherein after the sequential scanning pulse is applied to each odd-numbered second electrode, the sequential scanning pulse is applied to each even-numbered second electrode. Display panel driving method.