JP2004094281A - Driving method of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method of a plasma display panel in which a deterioration in contrast due to reset discharge is suppressed, or in which reset discharge and erase discharge are surely induced without deteriorating contrast and stable address discharge can be achieved. <P>SOLUTION: The method performs the reset discharge, the address discharge for writing display data and sustain discharge for performing light emitting display according to the written display data, the reset discharge includes a first discharge generated by a first pulse of which the impressed voltage value is changed in a first direction according to a lapse of time and a second discharge generated by a second pulse of which the impressed voltage value is changed in a second direction according to the lapse of time, and the second pulse is impressed after rising the first pulse. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a driving method of a plasma display panel (PDP).

PDP is a self-luminous display device, has good visibility, is thin and can display a large screen, and is therefore attracting attention as a next-generation display device replacing CRT. In particular, since the surface discharge AC type PDP can have a large screen, it is expected to be a display device compatible with high-quality digital broadcasting, and a higher image quality than a CRT is required.

Higher image quality includes higher definition, higher gradation, higher brightness, higher contrast, and the like. Higher definition is achieved by reducing the pixel pitch, and higher gradation is achieved by increasing the number of subfields in a frame. In addition, higher brightness can be achieved by increasing the amount of visible light obtained from a constant power or by increasing the number of sustain discharges. Further, higher contrast can be achieved by reducing the reflectance of extraneous light on the surface of the display panel or by reducing light emission during black display that does not contribute to display light emission.

FIG. 10 is a schematic configuration diagram of a surface discharge type PDP, which shows a configuration of a PDP of a type that has been applied by the present applicant and that performs display between all sustain discharge electrodes. (JP-A-9-160525)
PDP 1 includes sustain discharge electrodes X1 to X3 and Y1 to Y3 arranged in parallel on one substrate, and address electrodes A1 to A4 formed on the other substrate and intersecting the sustain discharge electrodes. Are arranged in parallel with the address electrodes and are formed by partition walls 2 for partitioning a discharge space. Discharge cells are respectively formed in regions defined by the sustain discharge electrodes adjacent to each other and the address electrodes crossing the sustain discharge electrodes, and a phosphor for obtaining visible light is provided. A gas for causing discharge is sealed between the two substrates. In this figure, for the sake of simplicity, the number of sustain discharge electrodes is three and the number of address electrodes is four.

In the PDP having this configuration, each of the sustain discharge electrodes can perform the sustain discharge between the sustain discharge electrodes on both sides thereof, so that all the gaps (L1 to L5) between all the electrodes become display lines. For example, the X1 electrode and the Y1 electrode form a display line L1, and the Y1 electrode and the X2 electrode form a display line L2.

FIG. 11 is a cross-sectional view along the address electrodes of the PDP of FIG. 10, wherein 3 indicates a front substrate, 4 indicates a rear substrate, and D1 to D3 indicate discharge between the electrodes. Specifically, discharge D1 can be caused by applying a voltage between the Y1 electrode and the X1 electrode. In addition, a discharge D2 can be generated by applying a voltage between the Y1 electrode and the X2 electrode, and a discharge D3 can be generated between the X2 electrode and the Y2 electrode. By utilizing one electrode for display on both sides in this manner, it is possible to achieve higher definition by reducing the number of electrodes and to reduce the number of drive circuits for those electrodes.

FIG. 12 is a diagram showing the structure of a frame in the PDP of FIG. One frame is composed of two fields, a first field and a second field. In the first field, display is performed on odd-numbered display lines (L1, L3, L5), and in the second field, display is performed on display lines (L2, L4) in even-numbered rows, thereby displaying one screen. Make up. Each field is composed of a plurality of sub-fields having a predetermined luminance ratio, and the sub-fields are selectively illuminated according to the display data to express a gradation which is a difference in luminance for each pixel. are doing. Each subfield is maintained on the basis of the reset period for equalizing the state of the cell which is different depending on the display state in the immediately preceding subfield, the address period for writing new display data, and the written display data. It is composed of a sustain discharge period for performing light emission display by discharge.

FIG. 13 is a waveform diagram showing a conventional driving method in the PDP of FIG. 10, and shows an arbitrary subfield in the first field.

In the reset period, a reset pulse having a voltage Vw exceeding the discharge start voltage is applied to all the X electrodes, and a discharge is started between adjacent X electrodes. As a result, the first discharge (reset discharge) is performed in all the display lines (L1 to L5), and wall charges by positive ions and electrons are formed in the discharge cells. Next, when the reset pulse is removed and each electrode is kept at the same potential, a second discharge (self-erasing discharge) is generated again by a potential difference caused by the wall charges formed on the electrodes. At this time, since the electrodes are at the same potential, positive ions and electrons formed by the discharge recombine in the discharge space, and the wall charges disappear. This discharge makes it possible to make the amount of wall charges in all display cells substantially uniform. (Equalization of wall charge distribution)
Next, in the address period, a scanning pulse composed of the voltage -Vy is sequentially applied from the Y1 electrode. At the same time, an address pulse consisting of a voltage Va is applied to the address electrode according to the display data, and an address discharge is started. At this time, a pulse consisting of the voltage Vx is supplementarily applied to the X1 electrode, which is an electrode pair for performing display on the Y1 electrode in the first field, and the discharge generated between the address electrode and the Y1 electrode is: The transition is made between the X1 electrode and the Y1 electrode. As a result, wall charges required to start the sustain discharge are formed near the X1 electrode and the Y1 electrode. On the other hand, the voltage of the X2 electrode, which is an electrode pair forming a line on which no display is performed, is maintained at 0 V, thereby preventing discharge from occurring on the X2 electrode side. Similarly, address discharge is sequentially performed on the odd-numbered Y electrodes.

After the address discharge by the odd-numbered Y electrodes is completed, a scan pulse is applied to the Y2 electrodes. At this time, a pulse composed of the voltage Vx is similarly applied to the X2 electrode, which is an electrode pair for performing display with respect to the Y2 electrode, and the X3 electrode (not shown) is maintained at 0 V like the X1 electrode. Similarly, the address discharge is sequentially performed on the even-numbered Y electrodes, and the address discharge is performed on the odd display rows of the entire screen.

(4) Then, the sustain discharge period starts, and a sustain pulse composed of the voltage Vs is alternately applied to the X electrode and the Y electrode. At this time, by setting the phase of the sustain pulse so that the potential difference between the electrode pairs of the lines not performing display is 0 V, discharge is prevented from occurring in non-display lines. For example, a sustain pulse having a different phase is applied to each of the pair of the X1 electrode and the Y1 electrode for displaying in the first field, but the sustain pulse is applied between the Y1 electrode and the X2 electrode, which are the electrode pair of the non-display line. It has the same phase. Thus, display in one subfield is performed.

In FIG. 13, Vs is a voltage required for performing sustain discharge, and is usually set to about 170 V. Further, Vw is set to about 350 V as a voltage exceeding the discharge starting voltage, -Vy as a scanning pulse is set to about -150 V, and address pulse Va is set to about 60 V. The sum of the absolute values of Va and Vy is set to be equal to or higher than the discharge starting voltage between the address electrode and the Y electrode. Vx is about 50 V, and is set to a value at which the discharge between the address electrode and the Y electrode shifts to the X electrode side to form a sufficient wall charge.
JP-A-8-160910 JP-A-9-160525 JP-A-8-212930 JP-A-8-275091 USP 5,745,086

However, in the conventional driving method, in order to perform the reset discharge, a sufficient voltage pulse Vw exceeding the discharge starting voltage in the discharge cell is applied, and a strong discharge occurs. The light emission generated by this discharge is background light which is not related to the original image display, and as a result, the contrast has been reduced.

In addition, in the case of the above-mentioned driving method in which all of the sustain discharge electrodes are used as display lines, it has become clear that reset discharge may not be stably generated in all discharge cells. That is, a discharge is caused in all display lines by a reset pulse applied to all X electrodes. However, there is a possibility that a discharge does not occur in some cells due to a variation in discharge start time of each discharge cell. is there.

In FIG. 11, when attention is paid to the X2 electrode, it is assumed that the discharge D2 between the X2 electrode and the Y1 electrode has occurred first. When the charges generated by the discharge start to accumulate near the electrodes, a reverse bias is applied by the wall charges, and the effective voltage to the discharge space decreases. Specifically, wall charges due to electrons are formed on the X2 electrode side, and the effective voltage of the Vw voltage applied to the electrode to the discharge space is reduced. If the decrease in the effective voltage precedes the start of the discharge between the X2 electrode and the Y2 electrode, the reset period may end without the discharge between the X2 electrode and the Y2 electrode. If the reset discharge is not performed in some of the discharge cells, the state of the cells cannot be made uniform, and the address discharge in the discharge cells cannot be stably generated, resulting in an erroneous display.

  Even if the reset discharge can be generated in all the cells, the subsequent self-erasing discharge may not be generated stably. That is, since the self-erasing discharge is caused by the potential difference between the wall charges formed by the reset discharge, the self-erasing discharge is often smaller than the reset discharge. Therefore, depending on the characteristic variations of the individual discharge cells, the self-erasing discharge does not occur, and the wall charges formed by the reset discharge remain as they are. Alternatively, there is a possibility that the self-erasing discharge does not occur because sufficient wall charges are not formed at the end of the reset discharge. As a result, in the discharge cells in which the erasure discharge has not been performed, the subsequent address discharge is not performed normally, causing an erroneous display.

(4) As a method for solving these problems, it is conceivable to raise the voltage of the reset pulse to cause more reliable discharge in all cells. However, a further increase in the discharge voltage further increases the above-mentioned background light emission and deteriorates the contrast.

{Circle around (4)} If the transition to the address period occurs with the wall charges remaining in the discharge cells due to the above-described causes, another problem will occur. As described above, in the address period, the voltage Vx is applied to the X electrodes forming the display lines, and the X electrodes forming the non-display lines are maintained at 0 V, thereby preventing the occurrence of address discharge. However, if unnecessary wall charges remain, discharge may occur even in a non-display line.

{For example, in FIG. 11, a scanning pulse consisting of a voltage -Vy is applied to the Y1 electrode, and an address pulse consisting of the voltage Va is applied to the address electrode to perform an address discharge. At this time, since the voltage Vx is applied to the X1 electrode, the discharge shifts to the discharge between the Y1 electrode and the X1 electrode, and the discharge D1 is performed. At this time, the X2 electrode adjacent to the Y1 electrode is maintained at a voltage of 0 V, and the generation of the discharge D2 can be avoided normally. However, the discharge D2 may be generated due to the bias of the residual charges due to the uncertainty of the reset discharge. As a result, wall charges of negative polarity are accumulated on the X2 electrode, and the next address discharge D3 to be performed is affected. The erroneous discharge due to the non-display electrode may also occur due to a variation in the discharge start voltage for each discharge cell.

維持 Further, the sustain discharge in each subfield may spread due to the sustain discharge voltage Vs and the cell structure. Referring to FIG. 6, when the sustain discharge is performed between the electrodes X1 and Y1 and between the electrodes X2 and Y2, a certain amount of wall charge is accumulated between the electrodes Y1 and X2. These are erased during the reset period of each subfield, and a part of them, particularly, wall charges formed on the address electrode side may remain without being erased. This wall charge has no effect in the field where display is performed between the electrodes X1 and Y1 and between the electrodes X2 and Y2, but makes the address discharge unstable in the next field where display is performed between the electrodes Y1 and X2. Cause.

The present invention provides a driving method of a plasma display panel capable of suppressing a decrease in contrast due to a reset discharge or reliably performing a reset discharge and an erasing discharge without causing a decrease in contrast, and realizing a stable address discharge. The purpose is to do.

In order to achieve the above object, a driving method of a plasma display panel according to the present invention includes a reset discharge, an address discharge for writing display data, and a sustain discharge for performing light emission display based on the written display data. The method of driving a plasma display panel according to claim 1, wherein the reset discharge includes: a first discharge generated by a first pulse in which an applied voltage value changes in a first direction with time; Accordingly, a second discharge generated by a second pulse whose applied voltage value changes in a second direction is included, and the second pulse is applied after the first pulse falls.

At this time, the electrode potential that has reached the first potential due to the application of the first pulse falls to a third potential that is higher than the second potential that is the electrode potential before the application of the first pulse. After that, the second pulse may be applied, or the electrode potential reaching the first potential by the application of the first pulse may be changed to the electrode potential before the application of the first pulse. After falling to a certain second potential, the second pulse may be applied.

According to the present invention, since the weak discharge can be performed at the time of the reset discharge, the amount of light emission is small, and the contrast is not significantly reduced despite the execution of the reset discharge.

This effect is not limited to the method of mainly performing display between all the electrodes described in the specification of the present application, but the conventional PDP in which one display line is formed between a pair of sustain discharge electrodes. Even if it is applied, it can be obtained.

FIG. 1 is a waveform chart showing a first embodiment of the present invention. FIG. 1 shows waveforms of an address electrode, an X1 electrode, a Y1 electrode, an X2 electrode, and a Y2 electrode in an arbitrary subfield in a first field for displaying an odd-numbered line, and shows a reset period, an address period, and a sustain discharge, respectively. And a period. In the following description, the X1 and X2 electrodes are referred to as X electrodes, the Y1 and Y2 electrodes are referred to as Y electrodes, and all of them are referred to as sustain discharge electrodes.

(4) In the reset period, positive and negative pulses are applied to the sustain discharge electrodes after the address electrodes are set to 0V. That is, a pulse consisting of the voltage -Vwx is applied to the X electrode, and a pulse consisting of the voltage Vwy is applied to the Y electrode. At this time, the pulse applied to the Y electrode is a blunt pulse whose voltage change amount per unit time changes and reaches the voltage Vwy. This causes a weak first discharge between the X electrode and the Y electrode.

When a conventional rectangular wave Vw is applied as the applied voltage, a strong discharge is generated in accordance with the difference Vw-Vf from the discharge start voltage Vf in the discharge cell, and excessive wall charges are formed to affect adjacent discharge cells. Will be given. However, by using the blunt pulse, each discharge cell starts discharging when the applied voltage exceeds the discharge starting voltage Vf of each discharge cell, so that the generated discharge is only weak and the amount of wall charges formed is small. Will also be slight. As a result, even if a reset discharge in a certain discharge cell precedes, it does not affect an adjacent discharge cell. Further, since the discharge is weak, the background light emission is also small.

(4) Subsequently, a pulse consisting of the voltage Vex is applied to the X electrode, and a pulse consisting of the voltage -Vey is applied to the Y electrode. At this time, the pulse applied to the Y electrode is a blunt pulse whose voltage change amount per unit time changes to reach the voltage -Vey. As a result, a second discharge occurs, and the wall charges formed by the immediately preceding discharge are erased.

When the self-erasing discharge is used as in the related art, the discharge may not occur depending on the amount of the formed wall charges or the characteristics of the discharge cell. However, in the present invention, the discharge is forcibly performed by applying the voltage of Vex + Vey. , The erasure discharge is reliably performed. Furthermore, since the applied pulse has a blunt waveform, the discharge becomes weak and the contrast does not deteriorate. Further, by setting Vex + Vey to a voltage slightly lower than the discharge start voltage Vf, the erasing discharge is performed by superimposing a small wall charge generated by the first discharge.

The sustain discharge is basically performed between the X and Y electrodes, and positive polarity wall charges are formed on the address electrodes maintained at a potential lower than the sustain discharge voltage Vs during the sustain discharge. . In the first discharge of this embodiment, since a pulse of negative polarity is applied to the X electrode, a discharge also occurs between the address and the X electrode in a form superimposed on the wall charges remaining on the address electrode, and the address electrode is discharged. The wall charges remaining near the upper part of the X electrode are erased. In the subsequent second discharge, since a pulse of negative polarity is applied to the Y electrode, the wall charges remaining in the vicinity of the address electrode above the Y electrode are similarly erased.

(4) Next, in the address period, a scan pulse is sequentially applied to the Y electrodes to perform an address discharge. Focusing on the X electrode, the voltage Vx is applied to the X electrode forming a display line, which is paired with the Y electrode to which the scan pulse is applied, as in the related art, and the address discharge is performed. On the other hand, a voltage of -Vux is applied to the X electrode constituting the non-display line, and the potential difference from the Y electrode is reduced to prevent the occurrence of address discharge in the non-display line. It is the same as in the related art that the address discharge is performed by sequentially applying the scan pulse to the odd-numbered Y electrodes and then applying the scan pulse to the even-numbered Y electrodes. .

(4) When the address period ends, a sustain discharge period starts, and a sustain pulse is alternately applied to the X electrode and the Y electrode, and the sustain discharge is repeated in the cells that have undergone the address discharge in the address period. At this time, as in the conventional case, the phase of the sustain discharge pulse is set so that the sustain discharge does not occur in the non-display line.

In FIG. 1, the sum of the absolute values of -Vwx and Vwy during the reset period is set to a value exceeding the firing voltage between the X electrode and the Y electrode. For example, -Vwx is -130V, and Vwy is 220V. In the subsequent erasing discharge, for example, Vex is 60 V and -Vey is -160 V. In the address period, Va is, for example, 60 V, -Vy of the scanning pulse is, for example, -150 V, Vx of the X electrode is, for example, 50 V, -Vux is, for example, -80 V, and Vs of the sustain pulse is, for example, 170 V. Further, Vex and Vx and -Vey and -Vy may be set to the same voltage, whereby the circuit can be shared and the circuit scale can be reduced.

FIG. 2 is a diagram showing a configuration of a frame according to the first embodiment of the present invention. The difference from the one shown in FIG. 7 is that a field reset period is provided at the start of each field. The field reset period is for erasing wall charges remaining on the address electrode side when switching fields.

FIG. 3 is a waveform chart showing a field reset in the first embodiment of the present invention. At time t1, a voltage of -Vy is applied to the Y1 electrode and Vs is applied to the X2 electrode, and a discharge occurs to form wall charges. Thereafter, when the pulse is removed and the electrode potentials are maintained at the same potential, a self-erasing discharge occurs due to the potential difference between the formed wall charges and the wall charges are erased. Similarly, from time t2 to t4, the reset discharge is sequentially performed between all the electrodes in four times, and the wall charges are surely erased. In the present embodiment, between the odd-numbered Y electrode and the even-numbered X electrode at t1, between the odd-numbered X electrode and the even-numbered Y electrode at t2, and at the time t3, between the odd-numbered X electrode and the odd-numbered X electrode. Although the discharge is performed between the Y electrodes and between the even-numbered X electrode and the even-numbered Y electrode at t4, the order in which the discharge is performed at t1 to t4 is arbitrary.

In the first embodiment, the pulse applied to the Y electrode at the time of the first and second discharges is a blunt pulse in which the amount of voltage change per unit time changes. Such a pulse waveform can be easily obtained by connecting a resistor R to a switching element that outputs a pulse, and configuring an RC circuit in combination with a capacitance C formed between the electrodes. The curve of the dull pulse is determined by a time constant defined by RC.

However, when a blunt pulse is used, the voltage change amount per unit time changes with the rise or fall, so that there is a problem that the discharge intensity differs depending on at which point the discharge starts. . For this reason, when the discharge starts in the vicinity where the pulse starts to saturate to the set voltage, it is possible to realize a very weak discharge. That is, if the discharge is started at a point where the rising or falling of the pulse is relatively steep, a strong discharge occurs, and a large amount of wall charges may be formed.

FIG. 4 is a waveform chart showing a second embodiment of the present invention. In this embodiment, the pulse applied to the Y electrode at the time of the first and second discharges is a triangular wave having a constant voltage change per unit time. According to the present embodiment, although the circuit configuration for generating a triangular wave is slightly more complicated than that of the first embodiment, since the pulse gradient is constant, it is possible to reliably generate a weak discharge. .

FIG. 5 is a waveform diagram showing the third embodiment of the present invention, and shows the last pulse of the sustain discharge period in the previous subfield and the reset period in the next subfield. In the present embodiment, the pulse applied to the Y electrode at the time of the first and second discharges is a blunt pulse in which the amount of voltage change per unit time changes, and this point is common to the first embodiment. However, in the present embodiment, a sufficient time is allowed from the fall of the last sustain pulse in the sustain discharge period of the previous subfield to the application of the pulse in the reset period of the next subfield.

(4) When a sustain discharge is generated by application of the sustain pulse, a predetermined amount of wall charges is accumulated at the end of the discharge. Then, after a certain period of time has elapsed from the end of the discharge, the formed wall charges start neutralizing with the space charges existing in the discharge space. Therefore, if the reset discharge is performed after a sufficient time has elapsed from the application of the final sustain pulse, it is possible to erase the wall charges remaining at the end of the sustain discharge period to some extent. As a result, the subsequent reset discharge can be performed with less residual wall charge, and stable reset discharge can be performed. It is appropriate that the time t1 from the fall of the last sustain pulse to the start of the next reset discharge is at least longer than 1 μs, preferably 10 μs.

Also, in this embodiment, during the first discharge in the reset period, a negative pulse to the X electrode and a positive pulse to the Y electrode are applied with different timings.

(4) When a negative pulse to the X electrode and a positive pulse to the Y electrode are simultaneously applied as in the first embodiment, a strong discharge may occur even though a blunt pulse is used. Therefore, in this embodiment, a negative pulse to the X electrode and a negative pulse to the Y electrode are applied with different timings.

As described above, the negative pulse applied to the X electrode at the time of the first discharge has the effect of erasing wall charges remaining on the address electrode. As the wall charges on the address electrodes are erased, positive wall charges are formed on the X electrodes to which the negative pulse is applied. When a second pulse of positive polarity is applied to the Y electrode in this state, the effective voltage between the X and Y electrodes decreases, and strong discharge can be prevented. In order to simply prevent strong discharge, there is a method of lowering the negative voltage applied to the X electrode. In this case, it is necessary to perform sufficient erasing discharge between the address electrode and the memory cell. Is not preferable because it becomes difficult.

(4) It is appropriate that the delay time t2 from the pulse application to the X electrode to the pulse application to the Y electrode is at least about 5 μs.

FIG. 6 is a waveform diagram showing the fourth embodiment of the present invention, and shows only the waveform of the Y electrode during the reset period. The pulse applied to the Y electrode is a dull pulse in which the amount of voltage change per unit time changes.

In the above-described first to third embodiments, when the second discharge is performed following the first discharge, the potential of the Y electrode that has reached Vwy is once dropped to 0 V once, and then the second discharge is performed. A pulse for discharging was applied. However, if the fall of the potential of the Y electrode to 0 V, the application of a positive pulse to the X electrode, and the application of a negative pulse to the Y electrode associated with the second discharge are performed at the same time, the gap between the electrodes at one time Since a high voltage is applied, strong discharge may occur.

Therefore, in the example of FIG. 6A in this embodiment, a pulse for the second discharge is immediately applied without lowering the Y electrode potential to 0V. By doing so, it is possible to prevent a high voltage from being applied at once between the electrodes, so that strong discharge can be avoided.

However, in the example of FIG. 6A, there is a problem that the time required for the second discharge becomes longer. This is because the potential of the Y electrode is dropped from Vwy to -Vey using a blunt pulse. If the time required for the second discharge is to be shortened, the amount of voltage change per unit time must be increased, and the discharge scale in the second discharge increases, resulting in a decrease in contrast.

6 (b) corresponds to an intermediate point between the first to third embodiments and the example of FIG. 6 (a). That is, after the Y electrode potential reaching Vwy is once reduced to a potential higher than 0 V (for example, about 20 V), a negative pulse composed of a blunt pulse is applied.

For example, by connecting a Y electrode whose electrode potential has reached Vwy to a power source Vs for sustain discharge, the potential is temporarily lowered to Vs, and then a predetermined potential is used by using a power recovery circuit connected to the Y electrode. It is possible to easily adopt a method of lowering the potential of the Y electrode up to that. The power recovery circuit connects an inductor to the Y electrode (or X electrode) to form a series resonance circuit together with the panel capacitance, and recovers and reuses the sustain voltage Vs applied to the electrode. During the sustain discharge period, the sustain voltage Vs is alternately applied between the X and Y electrodes. This operation is equivalent to charging and discharging the panel capacitance formed between the X and Y electrodes. . The power recovery circuit is for effectively utilizing the charge / discharge current, and is indispensable for reducing the power consumption of the PDP. By using this power recovery circuit, it is possible to lower the Y electrode potential without adding a new circuit.

{Circle around (4)} After the potential of the Y electrode is lowered to a predetermined potential, the circuit is connected to a normal obtuse wave circuit. As a result, in the present example, it is possible to reduce the time required for the second discharge without generating a strong discharge or increasing the amount of voltage change per unit time.

FIG. 7 is a waveform chart showing a fifth embodiment of the present invention. In this embodiment, the potential reached by the Y electrode at the end of the second discharge is set higher than -Vy which is the potential of the scanning pulse.

(4) Since the blunt pulse applied to the Y electrode at the time of the second discharge has a negative polarity, a positive wall charge is formed on the Y electrode. At this time, in the above-described first to fourth embodiments, since the Y electrode potential was lowered to −Vy which is the potential of the scanning pulse, the wall charges formed were relatively large. In the subsequent address period, a scan pulse of negative polarity is applied to the Y electrode. At this time, if positive wall charges remain, the effective voltage of the scan pulse is reduced and the address discharge is performed. Could hinder the stable performance of Conversely, if the potential reached by the Y electrode at the end of the second discharge is too high (for example, the non-selection potential of the Y electrode in the address period -Vsc), negative wall charges will be formed on the Y electrode. In this case, when a negative scanning pulse is applied to the Y electrode, a negative wall charge is superimposed, and a discharge may occur even in a cell to which no address pulse is applied.

In the present embodiment, the potential reached by the Y electrode at the end of the second discharge is between the selection potential -Vy and the non-selection potential -Vsc of the Y electrode during the address period, thereby enabling stable address discharge. Alternatively, if a drive margin equivalent to that of the related art can be obtained, the applied voltage of the address pulse can be reduced. The potential reached by the Y electrode is appropriately set so that the increase ΔV from the selection potential −Vy of the Y electrode during the address period is in the range of 0 <ΔV <20V, preferably about 10V.

FIG. 8 is a diagram showing the configuration of a frame in the sixth embodiment of the present invention, and FIG. 9 is a waveform diagram showing the sixth embodiment. This embodiment is common to the first embodiment in that the field reset period described with reference to FIG. 2 is provided, but is characterized in that a field reset charge adjustment period is further provided prior to the field reset period. is there.

At the end of the first field or the second field, the state of charge in each cell varies. This is because the discharge state of each field differs depending on the cell. If wall charges of the opposite polarity to the applied pulse for the field reset remain at the start of the field reset period, the effective voltage of the applied pulse is reduced, and stable field reset becomes difficult. . For example, in the example of FIG. 3, when a positive wall charge remains on the Y1 electrode (or a negative wall charge on the X2 electrode), the effective voltage applied between the Y1 and X2 electrodes decreases. , And a stable discharge becomes impossible.

In the present embodiment, a field reset charge adjustment period is provided prior to the field reset period, and wall charges of the same polarity are actively formed with respect to a pulse applied in the field reset period.

FIG. 9 is a specific waveform diagram. In the field reset charge adjustment period, first, a negative pulse is applied to the X1 electrode, and a positive pulse is applied to the Y1 electrode. The sum of the voltage Vwx applied to the X1 electrode and the voltage Vwy applied to the Y1 electrode exceeds the discharge start voltage of the cell, and discharge is started in all cells. At this time, since the pulse applied to the Y1 electrode is a blunt pulse in which the amount of voltage change per unit time changes, this discharge becomes a weak discharge similarly to the first discharge in the reset period, and a decrease in contrast can be suppressed. Due to this full-surface discharge, negative wall charges are accumulated on the Y1 electrode. However, the wall charges accumulated here are large, and if the process proceeds to the field reset period as it is, the discharge becomes too large due to the superposition of the wall charges. Therefore, a negative erase pulse is continuously applied to the Y1 electrode. Adjust the amount of accumulated wall charge. This negative pulse is also a dull pulse in which the amount of voltage change per unit time changes.

As a result, at the end of the field reset charge adjustment period, an appropriate amount of negative wall charges is accumulated. By shifting to the field reset period in this state, the formed wall charges are superimposed on the applied pulse, and the field reset can be executed reliably.

According to the present invention, it is possible to suppress a decrease in contrast and to surely perform a reset discharge and a subsequent erasing discharge on all display lines. As a result, the state of all cells can be reliably made uniform during the reset period, stable address discharge can be realized, and erroneous display can be prevented.

FIG. 4 is a waveform chart showing the first embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of a frame according to the first embodiment of the present invention. FIG. 4 is a waveform chart showing a field reset in the first embodiment of the present invention. FIG. 6 is a waveform chart showing a second embodiment of the present invention. FIG. 9 is a waveform chart showing a third embodiment of the present invention. FIG. 11 is a waveform chart showing a fourth embodiment of the present invention. FIG. 11 is a waveform chart showing a fifth embodiment of the present invention. It is a figure showing the frame composition in a 6th example of the present invention. FIG. 14 is a waveform chart showing a sixth embodiment of the present invention. It is a schematic structure figure of a surface discharge type PDP. FIG. 11 is a cross-sectional view of the PDP of FIG. 10 taken along an address electrode A1. FIG. 11 is a diagram showing a configuration of a frame in the PDP of FIG. 10. 11 is a waveform chart showing a conventional driving method in the PDP of FIG.

Explanation of reference numerals

1 PDP
2 Partition wall 3 Front substrate 4 Back substrate X1, X2, X3 ..., Y1, Y2, Y3 ... Sustain discharge electrodes A1, A2, A3 ... Address electrodes L1, L2, L3 ... Display lines

Claims (6)

A reset discharge, an address discharge for writing display data, and a driving method of a plasma display panel for performing a sustain discharge for performing light emission display based on the written display data,
The reset discharge includes a first discharge generated by a first pulse in which an applied voltage value changes in a first direction with time, and an applied voltage value changes in a second direction with time. A second discharge caused by a second pulse
The method of driving a plasma display panel, wherein the second pulse is applied after the first pulse falls. After the electrode potential that has reached the first potential by the application of the first pulse falls to a third potential that is higher than the second potential that is the electrode potential before the first pulse application, The method according to claim 1, wherein the second pulse is applied. Applying the second pulse after lowering the electrode potential that has reached the first potential by the application of the first pulse to a second potential that is an electrode potential before the application of the first pulse; The method of driving a plasma display panel according to claim 1, wherein: A reset discharge, an address discharge for writing display data, and a driving method of a plasma display panel for performing a sustain discharge for performing light emission display based on the written display data,
The reset discharge includes a first discharge generated by a first pulse in which an applied voltage value changes in a first direction with time, and an applied voltage value changes in a second direction with time. A second discharge caused by a second pulse
Before dropping the electrode potential that has reached the first potential by the application of the first pulse to a second potential that is the electrode potential before the application of the first pulse, applying the second pulse;
A driving method of a plasma display panel, wherein an electrode potential reached by application of the second pulse is lower than the second potential. A plurality of parallel first and second electrodes are arranged adjacent to each other, and a plurality of third electrodes are arranged so as to cross the first and second electrodes. Address discharge for writing, and a driving method of a plasma display panel performing a sustain discharge for performing a light emitting display based on the written display data,
The reset discharge includes a first discharge generated by a first pulse in which an applied voltage value changes in a first direction with time, and an applied voltage value changes in a second direction with time. A second discharge caused by a second pulse
In the first discharge, in a state where the potential of the first electrode is maintained lower than the electrode potential before the first pulse is applied, the first discharge increases from the electrode potential before the first pulse is applied. A method for driving a plasma display panel, wherein the method is performed by applying one pulse to the second electrode. A reset discharge, an address discharge for writing display data, and a driving method of a plasma display panel for performing a sustain discharge for performing light emission display based on the written display data,
The reset discharge includes a first discharge generated by a first pulse whose applied voltage value changes over time and a second discharge generated by a second pulse whose applied voltage value changes over time. Including discharge
The first pulse is a pulse having a first polarity with respect to the electrode potential before the first pulse is applied, and the second pulse is a pulse with respect to the electrode potential before the first pulse is applied. A method for driving a plasma display panel, wherein the pulse has a second polarity.