JP3821832B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a plasma display panel (PDP).

  The PDP is a self-luminous display device, has good visibility, and is thin and capable of displaying a large screen. Therefore, the PDP is attracting attention as a next-generation display device that replaces the CRT. In particular, since the surface discharge AC type PDP can have a large screen, there is an increasing expectation as a display device compatible with high-definition digital broadcasting, and a higher image quality than CRT is required.

  High image quality includes high definition, high gradation, high brightness, and high contrast. High definition is achieved by reducing the pixel pitch, and high gradation is achieved by increasing the number of subfields in the frame. Further, the increase in luminance is achieved by increasing the amount of visible light obtained from a certain power and increasing the number of sustain discharges. Further increase in contrast is achieved by reducing the reflectance of external light on the surface of the display panel and reducing light emission during black display that does not contribute to display light emission.

FIG. 10 is a schematic configuration diagram of a surface discharge type PDP, and shows a configuration of a PDP of a method for displaying between all sustain discharge electrodes already filed by the present applicant. (Japanese Patent Laid-Open No. 9-160525)
PDP 1 includes sustain discharge electrodes X1 to X3 and Y1 to Y3 arranged in parallel on one substrate, and address electrodes A1 to A4 formed on the other substrate so as to intersect the sustain discharge electrodes. The barrier ribs 2 are arranged in parallel to the address electrodes and partition the discharge space. Discharge cells are respectively formed in regions defined by the sustain discharge electrodes adjacent to each other and the address electrodes crossing the sustain discharge electrodes, and a phosphor for obtaining visible light is provided. A gas for causing discharge is sealed between the substrates. In this figure, for the sake of simplicity, three sustain discharge electrodes are provided and four address electrodes are provided.

  In the PDP having this configuration, each of the sustain discharge electrodes can perform a sustain discharge between the sustain discharge electrodes on both sides thereof, and therefore all the gaps (L1 to L5) between all the electrodes become display lines. For example, the X1 electrode and the Y1 electrode form the display line L1, and the Y1 electrode and the X2 electrode form the display line L2.

  FIG. 11 is a cross-sectional view taken along the address electrode of the PDP in FIG. 10, wherein 3 is a front substrate, 4 is a back substrate, and D1 to D3 are discharges between the electrodes. Specifically, the discharge D1 can be caused by applying a voltage between the Y1 electrode and the X1 electrode. Further, a discharge D2 can be caused by applying a voltage between the Y1 electrode and the X2 electrode, and similarly, a discharge D3 can be caused by the X2 electrode and the Y2 electrode. By utilizing one electrode for display on both sides in this way, it is possible to achieve high definition by reducing the number of electrodes and to reduce the drive circuits for these electrodes.

  FIG. 12 is a diagram showing a frame configuration in the PDP of FIG. One frame is composed of two fields, a first field and a second field. In the first field, display is performed on odd-numbered display lines (L1, L3, L5), and in the second field, display is performed on even-numbered display lines (L2, L4), thereby displaying one screen. It is composed. Each field is composed of a plurality of subfields having a predetermined luminance ratio. By selectively emitting light according to the display data, the subfields express gradations that are different in luminance for each pixel. is doing. Each subfield is maintained based on a reset period for making the state of cells different depending on the display state in the immediately preceding subfield uniform, an address period for writing new display data, and the written display data. It is comprised by the sustain discharge period which performs the light emission display by discharge.

  FIG. 13 is a waveform diagram showing a conventional driving method in the PDP of FIG. 10, and shows an arbitrary subfield in the first field.

In the reset period, a reset pulse composed of a voltage Vw exceeding the discharge start voltage is applied to all X electrodes, and discharge is started between adjacent Y electrodes. As a result, the first discharge (reset discharge) is performed in all the display lines (L1 to L5), and wall charges due to positive ions and electrons are formed in the discharge cells. Next, when the reset pulse is removed and each electrode is held at the same potential, a second discharge (self-erasing discharge) is generated again due to a potential difference caused by the wall charge itself formed on the electrode. At this time, since each electrode is at the same potential, positive ions and electrons formed by discharge are recombined in the discharge space, and wall charges disappear. By this discharge, the wall charge amount in all display cells can be made substantially uniform. (Uniform wall charge distribution)
Next, in the address period, a scan pulse having a voltage −Vy is sequentially applied from the Y1 electrode. At the same time, an address pulse consisting of a voltage Va is applied to the address electrodes in accordance with display data, and address discharge is started. At that time, a pulse composed of the voltage Vx is applied to the X1 electrode, which is an electrode pair for displaying the Y1 electrode in the first field, so that the discharge generated between the address electrode and the Y1 electrode is Transition between the X1 electrode and the Y1 electrode. Thereby, wall charges necessary for the start of the sustain discharge are formed in the vicinity of the X1 electrode and the Y1 electrode. On the other hand, the voltage of the X2 electrode, which is an electrode pair that forms a line that does not perform display, is maintained at 0 V, thereby preventing discharge from occurring on the X2 electrode side. Similarly, first, address discharge is sequentially performed on odd-numbered Y electrodes.

  After the address discharge by the odd-numbered Y electrode is completed, a scan pulse is applied to the Y2 electrode. At this time, a pulse composed of the voltage Vx is similarly applied to the X2 electrode which is an electrode pair for performing display with respect to the Y2 electrode, and the X3 electrode (not shown) is maintained at 0 V similarly to the X1 electrode. Similarly, the address discharge is sequentially performed on the even-numbered Y electrodes, and the address discharge is performed on the odd display rows of the entire screen.

  Next, in the sustain discharge period, a sustain pulse composed of the voltage Vs is alternately applied to the X electrode and the Y electrode. At this time, the phase of the sustain pulse is set so that the potential difference between the electrode pairs of the lines that are not displayed is 0 V, thereby preventing discharge from occurring on the non-display lines. For example, sustain pulses having different phases are applied to the pair of X1 electrode and Y1 electrode that perform display in the first field, but the sustain pulse is not applied between the Y1 electrode and X2 electrode that are electrode pairs of the non-display line. It becomes the same phase. In this way, display in one subfield is performed.

In FIG. 13, Vs is a voltage necessary for sustaining discharge, and is usually set to about 170V. Further, Vw is set to about 350 V as a voltage exceeding the discharge start voltage, -Vy which is a scanning pulse is set to about -150 V, and address pulse Va is set to about 60 V. Note that the sum of the absolute values of Va and Vy is set to be equal to or higher than the discharge start voltage between the address electrode and the Y electrode. Vx is about 50 V, and is set to a value at which discharge between the address electrode and the Y electrode shifts to the X electrode side to form a sufficient wall charge.
WO97 / 20301

  However, in the conventional driving method, in order to perform the reset discharge, a sufficient voltage pulse Vw exceeding the discharge start voltage in the discharge cell is applied, and a strong discharge is generated. The light emission generated by this discharge is background light emission unrelated to the original image display, resulting in a decrease in contrast.

  In particular, in the case of the above-described driving method using all the sustain discharge electrodes as display lines, it has become clear that the reset discharge may not be stably generated in all the discharge cells. In other words, a discharge is caused in all display lines by a reset pulse applied to all X electrodes, but there is a possibility that some cells may not be discharged due to variations in the discharge start time of each discharge cell. is there.

  When attention is paid to the X2 electrode in FIG. 11, it is assumed that the discharge D2 between the X2 electrode and the Y1 electrode has occurred first. When the charge generated by the discharge starts to accumulate in the vicinity of the electrode, a reverse bias due to the wall charge is applied, and the effective voltage with respect to the discharge space decreases. Specifically, wall charges due to electrons are formed on the X2 electrode side, and the effective voltage of the Vw voltage applied to the electrode to the discharge space is lowered. When the decrease in effective voltage precedes the start of discharge between the X2 electrode and the Y2 electrode, there is a possibility that the reset period ends without discharging between the X2 electrode and the Y2 electrode. If the reset discharge is not performed in some of the discharge cells, the state of the cells cannot be made uniform, and the address discharge in the discharge cells cannot be caused stably, resulting in erroneous display.

  Even if the reset discharge can occur in all the cells, the subsequent self-erasing discharge may not be stably generated. That is, since the self-erasing discharge is caused by the potential difference between the wall charges formed by the reset discharge, it is often smaller than the reset discharge. For this reason, depending on the variation in characteristics of the individual discharge cells, the wall charge formed by the reset discharge remains as it is without self-erasing discharge. Alternatively, there is a possibility that self-erase discharge does not occur because sufficient wall charges are not formed at the end of reset discharge. As a result, in the discharge cells in which the erasing discharge is not performed, the subsequent address discharge is not normally performed, causing erroneous display.

  As a method for solving these problems, it is conceivable that the voltage of the reset pulse is increased to cause discharge more reliably in all cells. However, the further increase of the discharge voltage further increases the above-mentioned background light emission and deteriorates the contrast.

  Furthermore, when the address period is entered with the wall charges remaining in the discharge cells due to the above-described causes, another problem occurs. As described above, in the address period, the voltage Vx is applied to the X electrode constituting the display line, and the X electrode constituting the non-display line is kept at 0 V, thereby preventing the address discharge. However, if unnecessary wall charges remain, discharge may occur even in non-display lines.

  For example, in FIG. 11, a scan pulse composed of a voltage -Vy is applied to the Y1 electrode, and an address pulse composed of a voltage Va is applied to the address electrode to perform address discharge. At that time, since the voltage Vx is applied to the X1 electrode, the process proceeds to the discharge between the Y1 electrode and the X1 electrode, and the discharge D1 is performed. At this time, the X2 electrode adjacent to the Y1 electrode is maintained at a voltage of 0 V, and the occurrence of the discharge D2 should be avoided. However, there is a case where the discharge D2 is generated due to the bias of the residual charge due to the uncertainty of the reset discharge. As a result, negative wall charges are accumulated on the X2 electrode, and the next address discharge D3 is affected. Note that this erroneous discharge due to the non-display electrode may also occur due to variations in the discharge start voltage for each discharge cell.

  Further, the sustain discharge in each subfield may spread due to the sustain discharge voltage Vs or the cell structure. Referring to FIG. 6, when a sustain discharge is performed between the electrodes X1 and Y1 and between the electrodes X2 and Y2, some wall charges are accumulated between the electrodes Y1 and X2. These are erased during the reset period of each subfield, but some of the wall charges formed particularly on the address electrode side may remain without being erased. This wall charge does not affect the field displaying between the electrodes X1-Y1 and between the electrodes X2-Y2, but makes the address discharge unstable in the next field displaying between the electrodes Y1-X2. Cause.

  The present invention provides a driving method of a plasma display panel that can realize a stable address discharge by suppressing reset discharge and erasure discharge without suppressing a decrease in contrast due to reset discharge or without accompanying a decrease in contrast. The purpose is to do.

  In the driving method of the plasma display panel according to claim 1, a plurality of parallel first and second electrodes are arranged adjacent to each other, and the third electrode is arranged to intersect the first and second electrodes. A method of driving a plasma display panel, comprising a plurality of electrodes, wherein discharge cells are defined in the crossing region of each electrode, and having a reset period, an address period, and a sustain discharge period. A positive first pulse whose applied voltage value increases with the passage of time is applied to the first electrode and a negative pulse is applied to the first electrode between the first and second electrodes. A step of generating a first discharge, and then applying a second pulse whose applied voltage value decreases with time to the second electrode, and applying a second pulse between the first and second electrodes. Discharge To include a step of generating.

  In the present invention according to the first aspect, since the weak discharge can be performed at the time of the reset discharge, the light emission amount is small, and the contrast is not greatly reduced even though the reset discharge is performed. Further, the subsequent erasing discharge is not self-erasing discharge, but is performed by applying a pulse whose applied voltage value changes with the passage of time. Therefore, the erasing discharge is performed regardless of variations in the characteristics of the discharge cells and the remaining wall charge. be able to. Further, since the discharge is weak, the amount of emitted light is small and the contrast is not greatly reduced.

  These actions are not limited to the method of performing display between all the electrodes, which is mainly described in the present specification, but the conventional PDP in which one display line is configured between a pair of sustain discharge electrodes. Even when applied to the above, it is obtained.

  In the present invention according to claim 1, since the second pulse is applied so as to be superimposed on the wall charge formed by the first discharge, reliable erasing discharge can be performed using the potential of the wall charge. Further, by applying a negative pulse to the first electrode during the first discharge, the wall charges remaining on the address electrode at the end of the sustain discharge process in the previous subfield can be erased.

  In the plasma display panel driving method according to the second aspect, the pulse relating to the first discharge is applied after a period exceeding at least 1 μs from the end of the sustain discharge period.

  In the present invention according to claim 2, the residual wall charge can be reduced prior to the reset discharge.

  4. The method of driving a plasma display panel according to claim 3, wherein, in the first discharge, the negative polarity to the first electrode is applied prior to the positive first pulse applied to the second electrode. Apply a pulse.

  According to the third aspect of the present invention, the wall charges remaining on the address electrodes can be erased, and the first discharge can be prevented from becoming a strong discharge.

  In the method for driving a plasma display panel according to claim 4, the first and second pulses whose applied voltage value changes with the passage of time are blunt pulses whose voltage change amount per unit time changes.

  In the method for driving a plasma display panel according to claim 5, the first and second pulses whose applied voltage value changes with the passage of time are triangular waves whose voltage change amount per unit time is constant.

  In the present invention according to claim 4, if the discharge start timing varies depending on the state of the discharge cell, there is a possibility that the intensity of the discharge may differ, but this can be realized with a relatively simple circuit configuration. is there.

  On the other hand, in the present invention according to claim 5, although the circuit configuration is somewhat complicated, it is possible to reliably perform weak discharge in all the discharge cells.

  According to the present invention, it is possible to suppress a decrease in contrast, and it is possible to reliably perform reset discharge and subsequent erase discharge on all display lines. As a result, the state of all the cells can be made uniform uniformly in the reset period, stable address discharge can be realized, and erroneous display can be prevented.

  FIG. 1 is a waveform diagram showing a first embodiment of the present invention. FIG. 1 shows waveforms of an address electrode, an X1 electrode, a Y1 electrode, an X2 electrode, and a Y2 electrode in an arbitrary subfield in the first field for displaying odd lines. The reset period, the address period, and the sustain discharge, respectively. It consists of a period. In the following description, the X1 electrode and the X2 electrode are referred to as an X electrode, the Y1 electrode and the Y2 electrode are referred to as a Y electrode, and they are all referred to as a sustain discharge electrode.

  In the reset period, the address electrode is set to 0 V, and positive and negative pulses are applied to the sustain discharge electrode. That is, a pulse composed of the voltage -Vwx is applied to the X electrode, and a pulse composed of the voltage Vwy is applied to the Y electrode. At this time, the pulse applied to the Y electrode is a blunt pulse that reaches the voltage Vwy while changing the amount of voltage change per unit time. As a result, a weak first discharge is performed between the X electrode and the Y electrode.

  When the conventional rectangular wave Vw is applied as the applied voltage, a strong discharge is generated according to the difference Vw−Vf from the discharge start voltage Vf in the discharge cell, and an excessive wall charge is formed, affecting the adjacent discharge cell. Will be given. However, by using the blunt pulse, each discharge cell starts discharge when the applied voltage exceeds the discharge start voltage Vf for each discharge cell, so that the generated discharge is only weak, and the amount of wall charges formed It will be a little. As a result, even if a reset discharge in a certain discharge cell precedes, it does not affect adjacent discharge cells. Further, since the discharge is weak, the background light emission is also reduced.

  Subsequently, a pulse composed of the voltage Vex is applied to the X electrode, and a pulse composed of the voltage −Vey is applied to the Y electrode. At this time, the pulse applied to the Y electrode is a blunt pulse that reaches the voltage −Vey while the amount of voltage change per unit time changes. Thereby, the second discharge occurs, and the wall charges formed by the immediately preceding discharge are erased.

  When self-erasing discharge is used as in the prior art, there is a situation in which discharge does not occur depending on the amount of wall charge formed or the characteristics of the discharge cell. In the present invention, however, the discharge is forcibly applied by applying a voltage of Vex + Vey Therefore, the erase discharge is surely performed. Further, since the applied pulse has a dull waveform, the discharge is weak and does not deteriorate the contrast. Further, by setting Vex + Vey to a voltage that is slightly lower than the discharge start voltage Vf, the erasure discharge is performed by superimposing slight wall charges generated by the first discharge.

  The sustain discharge is basically performed between the XY electrodes, but a positive polarity wall charge is formed on the address electrode maintained at a potential lower than the sustain discharge voltage Vs during that time. . In the first discharge of this embodiment, since a negative pulse is applied to the X electrode, a discharge is also generated between the address and the X electrode in a form superimposed on the wall charge remaining on the address electrode. The wall charges remaining in the vicinity of the upper portion of the X electrode are erased. In the subsequent second discharge, since the negative pulse is applied to the Y electrode, the wall charges remaining in the vicinity of the Y electrode above the address electrode are similarly erased.

  Next, in the address period, scan pulses are sequentially applied to the Y electrodes to perform address discharge. Paying attention to the X electrode, the voltage Vx is applied to the X electrode that forms a display line in a pair with the Y electrode to which the scanning pulse is applied, and address discharge is performed as in the conventional case. On the other hand, a voltage consisting of -Vux is applied to the X electrode constituting the non-display line, and the potential difference from the Y electrode is reduced to prevent the address discharge from occurring in the non-display line. It is the same as in the prior art to apply address discharge by sequentially applying scan pulses to even-numbered Y electrodes after applying address discharge by sequentially applying scan pulses to odd-numbered Y electrodes. .

  When the address period ends, a sustain discharge period starts and sustain pulses are alternately applied to the X electrode and the Y electrode, and the sustain discharge is repeated in the cells in which the address discharge was performed in the address period. At this time, the phase of the sustain discharge pulse is set so that the sustain discharge does not occur in the non-display line as in the conventional case.

  In FIG. 1, the sum of the absolute values of -Vwx and Vwy in the reset period is set to a value exceeding the discharge start voltage between the X electrode and the Y electrode. For example, -Vwx is -130V and Vwy is 220V. In the subsequent erasing discharge, for example, Vex is 60V and -Vey is -160V. Further, Va in the address period is, for example, 60V, -Vy in the scan pulse is, for example, -150V, Vx of the X electrode is, for example, 50V, -Vux is, for example, -80V, and Vs of the sustain pulse is, for example, 170V. Further, Vex and Vx, and -Vey and -Vy may be set to the same voltage, which makes it possible to share a circuit and reduce the circuit scale.

  FIG. 2 is a diagram showing a frame configuration in the first embodiment of the present invention. The difference from that shown in FIG. 7 is that a field reset period is provided at the start of each field. The field reset period is for erasing wall charges remaining on the address electrode side during field switching.

  FIG. 3 is a waveform diagram showing field reset in the first embodiment of the present invention. At time t1, a voltage composed of -Vy is applied to the Y1 electrode and Vs is applied to the X2 electrode, causing a discharge, and wall charges are formed. Thereafter, when the pulse is removed and the respective electrode potentials are held at the same potential, self-erasing discharge occurs due to the potential difference between the formed wall charges themselves, and the wall charges are erased. Similarly, from time t2 to t4, reset discharge is sequentially performed between all the electrodes divided into four times, and the wall charges are surely erased. In this embodiment, the odd-numbered Y electrode and the even-numbered X electrode are t1 at t1, the odd-numbered X electrode to the even-numbered Y electrode at t2, and the odd-numbered X electrode to odd-numbered at t3. The discharge is performed between the Y electrodes and between the even-numbered X electrode and the even-numbered Y electrode at t4, but the order in which the discharge is performed from t1 to t4 is arbitrary.

  In the first embodiment described above, the pulse applied to the Y electrode during the first and second discharges is a blunt pulse in which the amount of voltage change per unit time changes. Such a pulse waveform can be easily obtained by connecting a resistor R to a switching element that outputs a pulse, and configuring an RC circuit in combination with a capacitance C formed between the electrodes. The dull pulse curve is determined by a time constant defined by RC.

  However, when using a blunt pulse, the amount of change in voltage per unit time changes with rising or falling, so there is a problem that the intensity of the discharge varies depending on when the discharge starts. . For this reason, it is possible to realize a very weak discharge when the discharge is started in the vicinity where the pulse starts to saturate the set voltage.For example, the discharge is relatively early due to variations in the characteristics of the discharge cells, That is, when the discharge is started at a time when the rise or fall of the pulse is relatively steep, a strong discharge may occur and a large amount of wall charges may be formed.

  FIG. 4 is a waveform diagram showing a second embodiment of the present invention. In the present embodiment, the pulse applied to the Y electrode during the first and second discharges is a triangular wave with a constant voltage change amount per unit time. According to the present embodiment, the circuit configuration for producing the triangular wave is somewhat complicated as compared with the first embodiment, but the pulse gradient is constant, so that a weak discharge can surely occur. .

  FIG. 5 is a waveform diagram showing the third embodiment of the present invention, and shows the last pulse of the sustain discharge period in the previous subfield and the reset period in the next subfield. In the present embodiment, the pulse applied to the Y electrode during the first and second discharges is a blunt pulse in which the amount of voltage change per unit time changes, and this point is common to the first embodiment. However, in this embodiment, a sufficient time is allowed from the falling of the last sustain pulse in the sustain discharge period of the previous subfield to the pulse application in the reset period of the next subfield.

  When a sustain discharge is generated by the application of the sustain pulse, a predetermined amount of wall charges is accumulated with the end of the discharge. When a certain amount of time elapses from the end of the discharge, the formed wall charges start to neutralize with the space charges existing in the discharge space. Therefore, if the reset discharge is performed after a sufficient time has elapsed from the application of the final sustain pulse, the wall charges remaining at the end of the sustain discharge period can be erased to some extent. As a result, the subsequent reset discharge can be carried out with less residual wall charges, and a stable reset discharge is possible. The time t1 from the last sustain pulse falling to the start of the next reset discharge is suitably at least longer than 1 μs, preferably 10 μs.

  In the present embodiment, in the first discharge in the reset period, a negative pulse to the X electrode and a positive pulse to the Y electrode are applied at different timings.

  When a negative pulse to the X electrode and a positive pulse to the Y electrode are applied simultaneously as in the first embodiment, strong discharge may occur despite the use of a blunt pulse. Therefore, in this embodiment, the negative pulse to the X electrode and the negative pulse to the Y electrode are applied at different timings.

  As described above, the negative pulse applied to the X electrode during the first discharge has the effect of erasing the wall charges remaining on the address electrode, but this erasing discharge is preceded. As the wall charges on the address electrode are erased, positive wall charges are formed on the X electrode to which the negative polarity pulse is applied. When a positive second pulse is applied to the Y electrode in this state, the effective voltage between the XY electrodes is lowered, and strong discharge can be prevented. If it is simply to prevent strong discharge, there is a method of reducing the negative voltage applied to the X electrode, but in this case, sufficient erasing discharge is performed with the address electrode. Is not preferable because it becomes difficult.

  It is appropriate that the delay time t2 from the pulse application to the X electrode to the pulse application to the Y electrode is at least about 5 μs.

  FIG. 6 is a waveform diagram showing the fourth embodiment of the present invention, and shows only the waveform of the Y electrode in the reset period. The pulse applied to the Y electrode is a dull pulse in which the amount of voltage change per unit time changes.

  In the first to third embodiments described above, when the second discharge is performed subsequent to the first discharge, the potential of the Y electrode that has reached Vwy is once lowered to 0 V, and then the second discharge is performed. A pulse for discharging was applied. However, if the fall of the Y electrode potential to 0 V and the application of the positive pulse to the X electrode and the negative pulse to the Y electrode accompanying the second discharge are performed simultaneously, the electrodes are simultaneously removed between the electrodes. Since a high voltage is applied, strong discharge may occur.

  Therefore, in the example of FIG. 6A in this embodiment, the pulse for the second discharge is immediately applied without reducing the Y electrode potential to 0V. By doing so, it is possible to prevent a high voltage from being applied between the electrodes at a time, so that a strong discharge can be avoided.

  However, in the example of FIG. 6A, there is a problem that the time required for the second discharge becomes long. This is because the potential of the Y electrode is decreased from Vwy to -Vey using a blunt pulse. If the time required for the second discharge is to be shortened, the amount of voltage change per unit time must be increased, and the discharge scale in the second discharge increases, resulting in a decrease in contrast.

  The example of FIG. 6B corresponds to an intermediate between the first to third embodiments and the example of FIG. That is, the Y electrode potential reaching Vwy is once lowered to a potential higher than 0 V (for example, about 20 V), and then a negative pulse composed of a blunt pulse is applied.

  For example, the Y electrode whose electrode potential has reached Vwy is temporarily lowered to Vs by connecting to the power source Vs for sustain discharge, and further, a predetermined potential is obtained using a power recovery circuit connected to the Y electrode. A technique of lowering the Y electrode potential can be easily adopted. In the power recovery circuit, an inductor is connected to the Y electrode (or X electrode) to form a series resonance circuit together with the panel capacitance, and the sustain voltage Vs applied to the electrode is recovered and reused. In the sustain discharge period, the sustain voltage Vs is alternately applied between the XY electrodes. This operation is equivalent to charging / discharging the panel capacitance formed between the XY electrodes. . The power recovery circuit is for effectively using the charge / discharge current, and is indispensable for reducing the power consumption of the PDP. By using this power recovery circuit, it is possible to reduce the Y electrode potential without adding a new circuit.

  Then, after the Y electrode potential is lowered to a predetermined potential, it is connected to a normal obtuse wave circuit. As a result, in this example, the time required for the second discharge can be shortened without causing a strong discharge or increasing the amount of voltage change per unit time.

  FIG. 7 is a waveform diagram showing a fifth embodiment of the present invention. In this embodiment, the potential reached by the Y electrode at the end of the second discharge is set higher than −Vy, which is the potential of the scanning pulse.

  Since the blunt pulse applied to the Y electrode during the second discharge has a negative polarity, positive wall charges are formed on the Y electrode. At this time, in the first to fourth embodiments described above, since the Y electrode potential was lowered to −Vy, which is the potential of the scanning pulse, the wall charges formed were relatively large. In the subsequent address period, a negative scan pulse is applied to the Y electrode. However, if positive wall charges remain at this time, the effective voltage of the scan pulse is lowered, and address discharge is performed. There is a possibility that the stable effectiveness of the On the contrary, when the potential reached by the Y electrode at the end of the second discharge is too high (for example, the non-selection potential −Vsc of the Y electrode in the address period), negative wall charges are formed on the Y electrode. In this case, when a negative scanning pulse is applied to the Y electrode, negative wall charges are superimposed, and there is a possibility that a cell without an address pulse is also discharged.

  In this embodiment, the arrival potential of the Y electrode at the end of the second discharge is set between the selection potential -Vy and the non-selection potential -Vsc of the Y electrode in the address period, thereby enabling stable address discharge. Alternatively, the applied voltage of the address pulse can be reduced if a drive margin comparable to that of the conventional case is obtained. The arrival potential of the Y electrode is appropriately set so that the increase ΔV from the selection potential −Vy of the Y electrode in the address period is in the range of 0 <ΔV <20V, preferably about 10V.

  FIG. 8 is a diagram showing a frame configuration in the sixth embodiment of the present invention, and FIG. 9 is a waveform diagram showing the same embodiment. This embodiment is common to the first embodiment in that the field reset period described with reference to FIG. 2 is provided, but is characterized in that a field reset charge adjustment period is further provided prior to the field reset period. is there.

  At the end of the first field or the second field, the state of charge in each cell varies. This is because the discharge state for each field differs depending on the cell. If wall charges having a polarity opposite to the applied pulse for field reset remain at the start of the field reset period, the effective voltage of the applied pulse will be reduced, making stable field reset difficult. . For example, in the example of FIG. 3, when positive wall charges (or negative wall charges on the X2 electrode) remain on the Y1 electrode, the effective voltage applied between the Y1 and X2 electrodes decreases. , Stable discharge becomes impossible.

  In this embodiment, a field reset charge adjustment period is provided prior to the field reset period, and wall charges having the same polarity are actively formed with respect to pulses applied in the field reset period.

  FIG. 9 is a specific waveform diagram. In the field reset charge adjustment period, first, a negative pulse is applied to the X1 electrode, and a positive pulse is applied to the Y1 electrode. The sum of the voltage Vwx applied to the X1 electrode and the voltage Vwy applied to the Y1 electrode exceeds the discharge start voltage of the cell, and discharge in all cells is started. At this time, since the pulse applied to the Y1 electrode is a dull pulse in which the amount of voltage change per unit time changes, this discharge becomes a weak discharge like the first discharge in the reset period, and the reduction in contrast can be suppressed. Due to this overall discharge, negative wall charges are accumulated on the Y1 electrode. However, the wall charge accumulated here is a large amount, and when it is shifted to the field reset period as it is, the discharge becomes too large due to the superposition of the wall charge, so that a negative erase pulse is continuously applied to the Y1 electrode. Adjust the amount of accumulated wall charge. This negative pulse is also a dull pulse in which the amount of voltage change per unit time changes.

  As a result, an appropriate amount of negative wall charges is accumulated at the end of the field reset charge adjustment period. By shifting to the field reset period in this state, the formed wall charges are superimposed on the applied pulse, and the field reset can be surely executed.

It is a wave form diagram which shows 1st Example of this invention. It is a figure which shows the structure of the flame | frame in 1st Example of this invention. It is a wave form diagram which shows the field reset in 1st Example of this invention. It is a wave form diagram which shows 2nd Example of this invention. It is a wave form diagram which shows 3rd Example of this invention. It is a wave form diagram which shows 4th Example of this invention. It is a wave form diagram which shows 5th Example of this invention. It is a figure which shows the flame | frame structure in 6th Example of this invention. It is a wave form diagram which shows 6th Example of this invention. It is a schematic block diagram of surface discharge type PDP. FIG. 11 is a cross-sectional view taken along the address electrode A1 of the PDP of FIG. It is a figure which shows the structure of the flame | frame in PDP of FIG. It is a wave form diagram which shows the conventional drive method in PDP of FIG.

Explanation of symbols

1 PDP
2 Partition 3 Front substrate 4 Back substrate X1, X2, X3..., Y1, Y2, Y3... Sustain discharge electrodes A1, A2, A3... Address electrodes L1, L2, L3.

Claims (3)

A plurality of parallel first and second electrodes are disposed adjacent to each other, and a plurality of third electrodes are disposed so as to intersect the first and second electrodes. A method for driving a plasma display panel, wherein a discharge cell is defined, and includes a reset period, an address period, and a sustain discharge period, wherein the reset period includes:
Applying a positive first pulse whose applied voltage value increases with time to the second electrode and applying a negative pulse to the first electrode, the first and second A step of generating a first discharge between the electrodes, and then applying a second pulse whose applied voltage value decreases with the passage of time to the second electrode, between the first and second electrodes in viewing including the step of generating the second discharge,
The method of driving a plasma display panel, wherein the first pulse has a smaller voltage change amount per unit time when reaching the maximum potential than a voltage change amount per unit time at the start of application .   2. The method of driving a plasma display panel according to claim 1, wherein a pulse relating to the first discharge is applied after a period exceeding at least 1 [mu] s from the end of the sustain discharge period.   The negative pulse to the first electrode is applied to the first discharge prior to the positive first pulse to be applied to the second electrode in the first discharge. A driving method of the plasma display panel as described.

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