KR20050113845A - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

In the plasma display device, a driving waveform is applied to the scan electrode while the sustain electrode is biased to the ground voltage to perform a reset operation, an address operation, and a sustain discharge operation. Then, the driving board driving the sustain electrode can be removed. When the sustain electrode is biased to the ground voltage, a low voltage is applied to the scan electrode in the reset period, so that the potential caused by the wall charge of the scan electrode may be higher than the potential caused by the wall charge of the address electrode. In this case, if the rising waveform is applied in the reset period, strong discharge may occur between the address electrode and the scan electrode, so that the address electrode is biased to a constant voltage when the rising waveform is applied. In addition, in the falling period of the reset period, the voltage of the scan electrode is gradually decreased at a voltage of 0 V or less to set the falling slope of the scan electrode gently. This can prevent strong discharge in the reset period.

Description

Plasma display device and plasma display panel driving method {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of a plasma display panel. As shown in FIG. 1, the plasma display panel includes two insulating substrates 1 and 2 facing each other apart from each other. A plurality of scan electrodes 3a and sustain electrodes 3b are formed in pairs and in parallel on the insulating substrate 1, and the scan electrodes 3a and the sustain electrodes 3b are formed of the dielectric layer 4 and the protective film 5. Covered with. A plurality of address electrodes 6 are formed on the glass substrate 2, and the address electrodes 6 are covered with the insulating layer 7. The partition 8 is formed on the insulating layer 7 between the two address electrodes 6. In addition, the phosphor 9 is formed on the surface of the insulating layer 7 and on both sides of the partition 8. The insulating substrates 1 and 2 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 3a, the address electrode 6, the sustain electrode 3b, and the address electrode 6 are orthogonal to each other. The discharge space at the intersection of the address electrode 6 and the pair of scan electrode 3a and sustain electrode 3b forms a discharge cell (hereinafter referred to as a "cell") 12.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrodes and the sustain driving board for driving the sustain electrodes must be separately. As such, when the driving board is separately present, there is a problem in that the driving board is mounted on the chassis base, and the unit cost increases due to the two driving boards.

Therefore, a method of integrating two driving boards into one to form one end of the scan electrode and extending one end of the sustaining electrode to connect to the integrated board has been proposed. However, when the two driving boards are integrated in this manner, there is a problem in that an impedance component formed from a long extended sustain electrode becomes large.

An object of the present invention is to provide a plasma display device having an integrated board capable of driving a scan electrode and a sustain electrode. It is another object of the present invention to provide a driving waveform suitable for an integrated board.

In order to solve this problem, the present invention applies a drive waveform to the scan electrode while the sustain electrode is biased at a constant voltage.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method includes gradually increasing a voltage of the second electrode from a second voltage to a third voltage while biasing the first electrode to a first voltage in a reset period of at least one subfield, and Gradually decreasing the voltage of the second electrode from the negative fourth voltage to the fifth voltage while biasing the first electrode to the first voltage. At this time, the fourth voltage is substantially higher than the voltage corresponding to the sum of twice the voltage and the third voltage.

The voltage of the third electrode may be in a positive voltage state in a period in which the voltage of the second electrode is at least a part of the increase of the voltage to the third voltage, and the voltage of the second electrode increases to the third voltage. The voltage of the third electrode may be biased to the sixth voltage in at least part of the period.

In this driving circuit, the first electrode is biased to the first voltage in an address period and a sustain period, and the first voltage is a ground voltage.

According to another aspect of the present invention, a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and And a driving board configured to apply a driving waveform for displaying an image by the plasma display panel to the second electrode and the third electrode and to bias the first electrode to a first voltage while the image is displayed. A plasma display device including a chassis base facing a display panel is provided. In this apparatus, the driving board gradually increases the voltage of the second electrode from the second voltage to the third voltage in the reset period of at least one subfield, and then increases the voltage of the second electrode to the negative fourth voltage. And gradually reduce the voltage of the third electrode to a fifth voltage, and set the voltage of the third electrode to a positive voltage state during a period of at least a part of the period of decreasing the voltage of the second electrode to the fifth voltage. The absolute value of the fourth voltage is smaller than the absolute value of the sum of voltages corresponding to twice the third voltage and the fifth voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic conceptual view of a plasma display panel according to an exemplary embodiment of the present invention. 4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

As shown in FIG. 2, the plasma display device includes a plasma display panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 10 and coupled to the plasma display panel 10. The front and rear cases 30 and 40 are disposed at the front of the plasma display panel 10 and the rear of the chassis base 20, respectively, and are combined with the plasma display panel 10 and the chassis base 20 to form a plasma display device. Form.

Referring to FIG. 3, the plasma display panel 10 includes a plurality of address electrodes A1 to Am extending in the vertical direction, a plurality of scan electrodes Y1 to Yn extending in the horizontal direction, and a plurality of sustain electrodes X1 to Xn). The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 10 includes an insulating substrate on which sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and an insulating substrate on which address electrodes A1 to Am are arranged. The two insulating substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. . At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a cell (12 in FIG. 1).

As shown in FIG. 4, boards 100 to 500 necessary for driving the plasma display panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively, and may be formed of a single board or a plurality of boards. In FIG. 4, the plasma display apparatus for dual driving is described as an example. However, in the case of the single driving, the address buffer board 100 is disposed at any one of the upper and lower portions of the chassis base 20. The address buffer board 100 receives an address driving control signal from the image processing and control board 400 and applies a voltage for selecting a discharge cell to be displayed to each address electrode A1 to Am.

The scan drive board 200 is disposed on the left side of the chassis base 20, the scan drive board 200 is electrically connected to the scan electrodes Y1 to Yn via the scan buffer board 300, and the sustain electrode. (X1 to Xn) are biased at a constant voltage. The scan buffer board 300 applies a voltage for sequentially selecting the scan electrodes Y1 to Yn in the address period to the scan electrodes Y1 to Yn. The scan driving board 200 receives a driving signal from the image processing and control board 400 and applies a driving voltage to the scan electrodes Y1 to Yn. In FIG. 4, the scan driving board 200 and the scan buffer board 300 are disposed on the left side of the chassis base 20, but may be disposed on the right side of the chassis base 20. In addition, the scan buffer board 300 may be integrally formed with the scan driving board 200.

The image processing and control board 400 receives an image signal from the outside to generate a control signal for driving the address electrodes A1 to Am and a control signal for driving the scan and sustain electrodes Y1 to Yn and X1 to Xn. Each is applied to the address driving board 100 and the scan driving board 200. The power board 500 supplies power for driving the plasma display device. The image processing and control board 400 and the power board 500 may be disposed in the center of the chassis base 20.

Next, a driving waveform of the plasma display panel according to the first embodiment of the present invention will be described with reference to FIG. 5.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention. Hereinafter, for convenience, a scan electrode (hereinafter referred to as "Y electrode"), a sustain electrode (hereinafter referred to as "X electrode") and an address electrode (hereinafter referred to as "A electrode") which form one cell are applied. Only driving waveforms will be described. In the driving waveform of FIG. 5, the voltage applied to the Y electrode is supplied from the scan driving board 200 and the scan buffer board 300, and the voltage applied to the A electrode is supplied from the address buffer board 100. In addition, since the X electrode is biased by the reference voltage (the ground voltage in FIG. 5), the description of the voltage applied to the X electrode is omitted.

5, one subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

In the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is maintained at the reference voltage (0 V in FIG. 5). In FIG. 5, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 5, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage higher than the voltage applied to the Y electrode in the sustain period, and is lower than the discharge start voltage between the Y electrode and the X electrode.

Subsequently, in the falling period of the reset period, the voltage of the Y electrode is gradually decreased from the Vs voltage to the Vnf voltage while the A electrode is maintained at the reference voltage. Then, a slight discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, so that the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode The charge is erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

Next, to select a cell to be turned on in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. In order to perform this operation, the scan buffer board 300 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. When one Y electrode is selected, the address buffer board 100 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.

Specifically, first, a scan pulse of the VscL voltage is applied to the scan electrodes of the first row (Y1 in FIG. 3) and an address pulse of the Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode (Y2 in FIG. 3) of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

In this address period, the VscL voltage is generally set at a level equal to or lower than the Vnf voltage and the Va voltage is set at a level higher than the reference voltage. For example, the reason why the address discharge occurs in the cell when the Va voltage is applied when the VscL voltage and the Vnf voltage are the same will be described. When the voltage Vnf is applied in the reset period, the sum of the wall voltage between the A and Y electrodes and the external voltage Vnf between the A and Y electrodes is determined by the discharge start voltage Vfay between the A and Y electrodes. do. However, when 0 V is applied to the A electrode and a VscL (= Vnf) voltage is applied to the Y electrode in the address period, a discharge may occur because a Vfay voltage is formed between the A electrode and the Y electrode. Since the time is longer than the width of the scan pulse and the address pulse, no discharge occurs. However, when Va voltage is applied to the A electrode and VscL (= Vnf) voltage is applied to the Y electrode, a voltage higher than the Vfay voltage is formed between the A electrode and the Y electrode, and the discharge delay time is shorter than the width of the scan pulse. This can happen. At this time, the VscL voltage may be set to a voltage lower than the Vnf voltage so that address discharge occurs better.

Next, in the cell where the address discharge occurred in the address period, the wall voltage Vwxy of the Y electrode with respect to the X electrode was formed with a high voltage. In the sustain period, the Y electrode and the X electrode were first applied with a pulse having a Vs voltage to the Y electrode. It causes maintenance discharge between them. At this time, the voltage Vs is set to be lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, and the voltage (Vs + Vwxy) is lower than the voltage Vfxy. As a result of the sustain discharge, (-) wall charges are formed on the Y electrode and (+) wall charges are formed on the X electrode and the A electrode, so that the wall voltage Vfyx of the X electrode with respect to the Y electrode is formed at a high voltage.

Then, since the wall voltage Vfyx of the X electrode with respect to the Y electrode was formed at a high voltage, a sustain discharge was generated between the Y electrode and the X electrode by applying a pulse having a voltage of -Vs to the Y electrode. As a result, positive wall charges are formed on the Y electrode, negative wall charges are formed on the X electrode and the A electrode, and a sustain discharge can occur when the Vs voltage is applied to the Y electrode. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. .

As described above, in the first embodiment of the present invention, the reset operation, the address operation, and the sustain discharge operation may be performed only by the driving waveform applied to the Y electrode while the X electrode is biased to the reference voltage. Therefore, the driving board driving the X electrode can be removed, and only the biasing of the X electrode to the reference voltage is required.

Referring to FIG. 5, in the first embodiment of the present invention, the final voltage applied to the Y electrode in the falling period of the reset period is set to the Vnf voltage, and as described above, the final voltage Vnf is determined between the Y electrode and the X electrode. The voltage near the discharge start voltage. In general, since the discharge start voltage Vfay between the Y electrode and the A electrode is lower than the discharge start voltage Vfxy between the Y electrode and the X electrode, the potential of the Y electrode due to the wall charge at the final voltage Vnf in the falling period. Is higher than the A electrode, the wall voltage of the Y electrode with respect to the A electrode can be set to a positive voltage. Since the sustain discharge does not occur in the cell which does not have address discharge, the reset period of the next subfield is performed while maintaining the wall charge state. In the cell in this state, the wall voltage of the Y electrode for the A electrode is higher than the wall voltage of the Y electrode for the X electrode, so that the voltage between the A electrode and the Y electrode increases when the voltage of the Y electrode increases in the rising period of the reset period. After a certain period of time passes after the discharge start voltage Vfay is exceeded, the voltage between the X electrode and the Y electrode exceeds the discharge start voltage Vfay.

In the rising period of the reset period, since a high voltage is applied to the Y electrode, the Y electrode serves as an anode, and the A and X electrodes serve as a cathode. The discharge in the cell is determined by the amount of secondary electrons emitted from the cathode when the cation strikes the cathode. It is called a process. In general, in the plasma display panel, the A electrode is covered with a phosphor for color expression, while the X electrode and the Y electrode are covered with a material having a high secondary electron emission coefficient such as a protective film of MgO component for efficiency of sustain discharge. However, in the rising period, even if the voltage between the A electrode and the Y electrode exceeds the discharge start voltage Vfay, since the A electrode covered with the phosphor acts as a cathode, the discharge is delayed between the A electrode and the Y electrode. When the actual discharge occurs between the A electrode and the Y electrode due to the discharge delay, the voltage between the A electrode and the Y electrode is higher than the discharge start voltage Vfay. Therefore, such a high voltage may cause a strong discharge rather than a weak discharge between the A electrode and the Y electrode. Such strong discharges also cause strong discharges between the X electrodes and the Y electrodes, so that a larger amount of wall charges are formed in the cell than the wall charges generated in the normal rising period, and a large amount of priming particles can be produced.

Then, a strong discharge may occur due to a large amount of wall charges and priming particles in the falling period, and thus, wall charges may not be sufficiently erased between the X electrode and the Y electrode as shown in FIG. 6. In the cell in this state, a high wall voltage is formed between the X electrode and the Y electrode even after the end of the reset period, and even if an address discharge does not occur due to this wall voltage, erroneous discharge may occur between the X electrode and the Y electrode in the sustain period. An embodiment capable of preventing such a discharging will be described in detail with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

Referring to FIG. 7, the driving waveform according to the second embodiment of the present invention is the same as that of the first embodiment except for biasing the A electrode to a constant voltage in the rising period of the reset period.

Specifically, in the rising period of the reset period, the voltage of the Y electrode is gradually increased from the Vs voltage to the Vset voltage while the A electrode is biased to a constant voltage (voltage higher than the reference voltage). In this case, when the Va voltage is used as the bias voltage of the A electrode as illustrated in FIG. 7, an additional power source may not be used. When the voltage of the Y electrode is increased while the voltage of the A electrode is biased to the Va voltage, the voltage between the A electrode and the Y electrode is smaller than that of the first embodiment so that the voltage between the X electrode and the Y electrode is smaller than the A and Y electrodes. The discharge start voltage is exceeded before the voltage in between. Then, a weak discharge occurs first between the X electrode and the Y electrode, and the voltage between the A electrode and the Y electrode exceeds the discharge start voltage while the priming particles are formed by the weak discharge. The priming particles reduce the discharge delay between the A electrode and the Y electrode, so that the weak discharge is performed without generating the strong discharge as described above, thereby forming a desired amount of wall charge. Therefore, weak discharge does not occur even in the falling period of the reset period, and thus, the false discharge in the sustain period can be prevented.

In FIG. 7, the A electrode is biased to a constant voltage during the rising period. Alternatively, the A electrode may be biased to the constant voltage only at the beginning of the rising period. As described above, in order to prevent the strong discharge from occurring in the rising period, it is necessary to prevent the voltage between the A and Y electrodes from exceeding the discharge start voltage before the voltage between the X and Y electrodes. It can also be biased at a constant voltage. That is, after weak discharge occurs between the A electrode and the Y electrode, the voltage of the A electrode can be set back to the reference voltage.

In addition, the voltage of the A electrode may be gradually increased. If the voltage of the A electrode increases as the voltage of the Y electrode increases in the rising period, the voltage between the A electrode and the Y electrode is lower than when the A electrode voltage is biased to the reference voltage. Weak discharge may occur first. The period for increasing the voltage of the A electrode may be part of the rising period or the whole of the rising period. It is also possible to float the A electrode without increasing the voltage of the A electrode. Since the capacitance component is formed by the A electrode and the Y electrode, when the A electrode is floated when the voltage of the Y electrode increases, the voltage of the A electrode also increases along with the voltage of the Y electrode. Therefore, the same effect as in the second embodiment of FIG. 7 can be achieved. The floating period of the A electrode may be part of the rising period or the whole of the rising period.

In FIG. 7, the discharge of the A electrode is increased by increasing the voltage of the A electrode than the reference voltage in the rising period, but alternatively, the slope of the decreasing voltage of the Y electrode in the falling period may be adjusted. Hereinafter, this embodiment will be described with reference to FIGS. 8 and 10.

FIG. 8 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention, and FIG. 9 is a diagram showing a wall charge state of a cell after the rise period ends. 10 is a driving waveform diagram of a plasma display panel according to a fourth exemplary embodiment of the present invention.

As shown in FIG. 8, the driving waveform according to the third embodiment of the present invention is different from the second embodiment except that the voltage at which the voltage of the Y electrode starts to decrease in the falling period of the reset period is less than or equal to the Vs voltage. same.

In general, the weaker the discharge occurs in the cell, the slower the slope of the voltage of the electrode that changes gradually over time. Therefore, when the falling start voltage of the Y electrode is set to a low voltage as in the third embodiment, the falling slope of the Y electrode can be set more gently in a given falling period. Then, even when the strong discharge occurs in the rising period, the strong discharge can be prevented because the voltage of the Y electrode changes at a slower speed than in the first embodiment. In this case, an additional power source may not be used when the falling start voltage of the Y electrode is set to the reference voltage (0V).

For example, when the falling start voltage of the Y electrode is 0 V, the difference between the voltage applied to the X electrode and the Y electrode from the outside at the time of falling of the Y electrode and the difference of the voltage applied to the A electrode and the Y electrode are all 0 V and thus discharged. This does not happen. At this time, when the voltage drops directly from the high Vset voltage to the 0V voltage, self-erasing discharge occurs. Thus, at least once between the falling start voltage of the Y electrode at the Vset voltage, a voltage between the falling start voltage of the Y electrode at the Vset voltage is applied to the Y electrode. At this time, when the Vs voltage is applied, no additional power supply is required. Next, when the voltage of the Y electrode gradually decreases from 0V, weak discharge occurs when the difference between the wall voltage formed in the cell and the voltage applied from the outside exceeds the discharge start voltage, so that the wall charge can be set.

The driving waveform according to the fourth exemplary embodiment of FIG. 10 is the same as that of the third exemplary embodiment of FIG. 8 except that the falling start voltage of the Y electrode starts at 0V or less.

Generally, when the rising period ends, the wall charge states of the Y electrode and the X electrode are shown in FIG. 9. At this time, the wall voltage due to the wall charge between the Y electrode and the X electrode is as shown in Equation 1 below.

Where Vw is the wall voltage between the Y electrode and the X electrode and Vfxy is the discharge start voltage between the Y electrode and the X electrode.

In addition, assuming that the falling start voltage of the Y electrode is lowered to a Vn voltage of 0 V or less, discharge should occur when the voltage of the Y electrode is less than or equal to the Vn voltage. That is, the sum of the applied voltage Vn and the wall voltage between the Y electrode and the X electrode must be smaller than the discharge start voltage between the Y electrode and the X electrode so that the discharge between the Y electrode and the X electrode does not occur at the time of applying the Vn voltage. That is, Equation 2 must be satisfied.

When Equation 1 is applied to Equation 2, Vn is determined in a range in which Vn satisfies Equation 3 in a range where no discharge occurs between the Y electrode and the X electrode.

On the other hand, in general, since all types of discharge cells must be initialized in the reset period, the difference between the highest voltage and the lowest voltage applied during the reset period is set to 2Vfxy or more. That is, in order to generate discharge in all the discharge cells, between the scan electrode and the address electrode, Since voltage fluctuations as much as the voltage must be applied, Equation 4 must be satisfied.

As described above, since the magnitude of the Vnf voltage, which is the final voltage in the falling period, is set near the discharge start voltage Vfxy, the Vset voltage satisfies Equation 5 below.

Therefore, the Vset voltage may be set as in Equation 6 below.

Therefore, when Equation 6 is applied to Equation 3, the Vn voltage can be set to a negative voltage.

In addition, since the magnitude of the Vnf voltage, which is the final voltage of the falling period, is set to be near the discharge start voltage Vfxy between the Y electrode and the X electrode as described above, Equation 3 may be expressed as Equation 7 below. Therefore, the Vn voltage can lower the start voltage of the falling slope of the Y electrode to a range that satisfies Equation (7).

That is, the falling start voltage of the Y electrode may be determined within the range in which the Vn voltage satisfies the expression (4). If the voltage drops directly from Vset voltage to Vn voltage, self-erasing may cause discharge. That is, at least one voltage between the falling start voltage Vn of the Y electrode at the Vset voltage is applied to the Y electrode to prevent discharge due to self-erasing. At this time, the voltage of the Y electrode can be gradually decreased to the Vnf voltage after the voltage of the Y electrode is gradually reduced from the voltage of Vset to Vs → 0V → Vn in the falling period, and the voltage of the Y electrode is reduced to Vset voltage →. After gradually decreasing the voltage from Vs to Vn, the voltage of the Y electrode can be gradually decreased to the voltage Vnf. At this time, if the Vn voltage is set to 0V, no additional power supply is required.

As described above, when the falling start voltage of the Y electrode is set to 0 V or less, the falling slope of the Y electrode becomes more gentle than in the third embodiment. Therefore, the strong discharge in the falling period of the reset period can be prevented and the falling period can be reduced.

As described above, according to the exemplary embodiment of the present invention, since the driving waveform is applied only to the Y electrode while the X electrode is biased to a predetermined voltage, the reset operation, the address operation, and the sustain discharge operation can be performed. The board can be removed. In addition, since the pulse for sustain discharge is supplied only from the scan driving board 300, the impedance in the path to which the sustain discharge pulse is applied may be constant.

In addition, the reset periods of the plurality of subfields forming one field may be formed as rising periods and falling periods. Alternatively, the reset period of some of the subfields may be formed only in the fall period, which will be described below in detail with reference to FIG. 11.

11 is a driving waveform diagram of a plasma display panel according to a fifth exemplary embodiment of the present invention. In FIG. 11, only two subfields of the plurality of subfields are illustrated, and for convenience, the two subfields are illustrated as first and second subfields, respectively. In FIG. 11, the reset period of the first subfield consists of a rising period and a falling period, and the reset period of the second subfield consists of a falling period.

Referring to FIG. 11, the first subfield has the same shape as the driving waveform of FIG. 10. Next, in the reset period of the second subfield, the voltage of the Y electrode is gradually decreased to the Vnf voltage while the sustain discharge pulse of the Vs voltage is applied to the Y electrode in the sustain period of the first subfield. That is, as described above, the second subfield is configured to have a falling period as a reset period.

At this time, when sustain discharge occurs in the sustain period of the first subfield, since negative (−) wall charges are formed on the Y electrode and positive (+) wall charges are formed on the X electrode and the A electrode, the voltage of the Y electrode gradually decreases. When the discharge start voltage is exceeded together with the wall voltage formed in the cell, weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the Y electrode is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield ends in the falling period of the first subfield. It becomes substantially the same as the later wall charge state.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, discharge does not occur when the voltage of the Y electrode decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen. That is, since no discharge occurs in other subfields when displaying the black gradation, the contrast ratio can be increased.

10 and 11 show that the voltage of the A electrode is biased by the Va voltage in the rising period, but the voltage of the A electrode may not be biased in the rising period. That is, since the falling start voltage of the Y electrode can be lowered to 0 V or less in the falling period, even if a strong discharge occurs in the rising period, the strong discharge can be prevented because the voltage of the Y electrode changes at a slow speed in the falling period.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the driving waveform is applied only to the scan electrode while the sustain electrode is biased at a constant voltage, the board for driving the sustain electrode can be removed. In other words, it is possible to implement an integrated board that is substantially driven by only one board, thereby reducing the unit cost.

In the case where the scan electrode and the sustain electrode are implemented as the respective driving boards, since the driving waveforms in the reset period and the address period are mainly supplied from the scan driving board, impedances formed in the scan driving board and the sustain driving board are different. Accordingly, the sustain discharge pulse applied to the scan electrode and the sustain discharge pulse applied to the sustain electrode in the sustain period may be different. However, according to the present invention, since the pulse for sustain discharge is supplied only from the scan driving board, the impedance is always constant.

In addition, by setting the start voltage of the falling slope to a negative voltage in the rising period and setting the falling slope gently, the strong discharge in the reset period can be prevented and the reset period can be shortened.

1 is a partial perspective view of a plasma display panel.

2 is an exploded perspective view of a plasma display device according to an exemplary embodiment of the present invention.

3 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a chassis base according to an embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

6 is a diagram showing the wall charge state of a cell when a strong discharge occurs in the reset period.

7 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

8 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

FIG. 9 is a diagram illustrating a wall charge state of a cell after the rising period of FIG. 8 ends.

10 and 11 are driving waveform diagrams according to the fourth and fifth exemplary embodiments of the present invention, respectively.

Claims (10)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In the reset period of at least one subfield, Gradually increasing the voltage of the second electrode from a second voltage to a third voltage while biasing the first electrode to a first voltage, and Gradually decreasing the voltage of the second electrode from the negative fourth voltage to the fifth voltage while biasing the first electrode to the first voltage; Method of driving a plasma display panel comprising a. The method of claim 1, And wherein the fourth voltage is substantially higher than a voltage corresponding to twice the sum of the fifth voltage and the third voltage. The method of claim 1, And driving the voltage of the third electrode to a positive voltage state during a period in which the voltage of the second electrode is at least a part of the increase to the third voltage. The method of claim 3, wherein And biasing the voltage of the third electrode to the sixth voltage in a period during which the voltage of the second electrode is at least a part of the increase to the third voltage. The method according to any one of claims 1 to 4, And the first electrode is biased to the first voltage in an address period and a sustain period. The method of claim 5, And the first voltage is a ground voltage. The method of claim 6, And the fourth voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and And a driving board configured to apply a driving waveform for displaying an image by the plasma display panel to the second electrode and the third electrode and to bias the first electrode to a first voltage while the image is displayed. Chassis base facing display panel Including; The driving board gradually increases the voltage of the second electrode from the second voltage to the third voltage from the second voltage to the third voltage in the reset period of at least one subfield, and then increases the voltage of the second electrode from the negative fourth voltage to the fifth voltage. Gradually decrease to And the voltage of the third electrode is in a positive voltage state during a period in which the voltage of the second electrode is at least part of a period in which the voltage of the second electrode decreases to the fifth voltage. The method of claim 8, The absolute value of the fourth voltage is less than the absolute value of the sum of the voltage corresponding to twice the third voltage and the fifth voltage. The method according to claim 8 or 9, And the first voltage is a ground voltage.