KR100561346B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

In the method of driving a plasma display panel according to the present invention, a plurality of subfields are assigned to the first electrode and the second electrode in a sustain period in which sustain discharge pulses for sustain discharge are alternately applied to the first electrode and the second electrode. According to the number of sustain discharge pulses applied to the divided into a plurality of groups including a first group and a second group, in the subfield of the first group, the last sustain discharge pulse applied to the first electrode is the first The inductor is electrically connected to an electrode through resonance of the capacitive load, and in the second group of subfields, the last sustain discharge pulse applied to the first electrode is applied without the resonance. This has the effect of reducing the address discharge delay in the next subfield.

PDP, electrode, resonance, scan voltage, address, discharge, power recovery circuit

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 and 3 are driving waveform diagrams of the plasma display panel according to the first and second embodiments of the present invention.

4 is a diagram showing the result of the last sustain discharge pulse of the sustain electrode generated by turning the power recovery circuit ON or OFF on the address discharge delay.

5 is a view showing a sustain discharge driving circuit according to an embodiment of the present invention.

6A and 6B are diagrams illustrating current paths in respective modes in the driving circuit of FIG. 5 for generating a last sustain discharge pulse applied to a sustain electrode in the driving waveform of FIG. 2 according to an exemplary embodiment of the present invention.

The present invention relates to a method for driving a plasma display panel (PDP).

In the AC plasma display panel, scan electrodes and holding electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

According to the method of driving the plasma display panel, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cell.

In the address period, a scan pulse and an address pulse are applied to the scan electrode Y and the address electrode, respectively, to generate an address discharge between the scan electrode Y and the address electrode A to select a cell to be turned on.

In general, a discharge performed by applying a voltage between two electrodes is delayed in time than when a voltage is applied, thereby causing a discharge. In particular, since the address discharge has to be performed within a width of the constant scan pulse and the address pulse, a problem occurs in that the discharge does not occur when the discharge delay time is longer than the width of the scan pulse and the address pulse.

 SUMMARY OF THE INVENTION The present invention has been made in an effort to solve such a conventional problem, and to provide a method of driving a plasma display panel capable of generating stable address discharge by shortening an address discharge delay time.

According to an aspect of the present invention, a frame includes a plurality of sub electrodes in a plasma display panel including a plurality of first electrodes and a plurality of second electrodes, the capacitive load being formed by the first electrode and the second electrode. A method of driving by dividing into fields is provided. The driving method includes alternately applying a sustain discharge pulse for sustain discharge to the first electrode and the second electrode in a sustain period, wherein the plurality of subfields are applied to the first electrode and the second electrode. According to the number of sustain discharge pulses applied to the electrode divided into a plurality of groups including a first group and a second group, in the subfield of the first group, the last sustain discharge pulse applied to the first electrode is The inductor electrically connected to one electrode and the capacitive load are applied through resonance, and in the second group of subfields, the last sustain discharge pulse applied to the first electrode is applied without the resonance. At this time, the group may be divided from 17 total sustain discharge pulses applied to the first electrode and the second electrode.

And the number of sustain discharge pulses of the subfield having the largest number of sustain discharge pulses among the subfields of the first group is less than the number of sustain discharge pulses of the subfield having the smallest number of sustain discharge pulses among the subfields of the second group, The last sustain discharge pulse is applied to the second electrode in the sustain period of each subfield. In this case, the first electrode is a sustain electrode, and the second electrode is a scan electrode.

According to another aspect of the present invention, a plasma display panel including a plurality of scan electrodes and a plurality of sustain electrodes, wherein a capacitive load is formed by the scan electrodes and the sustain electrodes, and one frame in the plasma display panel A plasma display device is provided that includes a driving circuit that is divided into a plurality of subfields including a reset period, an address period, and a sustain period, and applies a driving voltage to the scan electrode and the sustain electrode. In this case, the driving circuit alternately applies a sustain discharge pulse of a first voltage for sustain discharge to the scan electrode and the sustain electrode in a sustain period of a first subfield among the plurality of subfields, According to the weight of one subfield, the voltage change time of the sustain electrode is varied in the sustain discharge pulse last applied to the sustain electrode in the sustain period of the first subfield.

And when the time when the subfield weight is the first weight is changed from the sustain discharge pulse last applied to the sustain electrode to the first voltage, the subfield weight is a second weight greater than the first weight. The first voltage is longer than the time changed from the sustain discharge pulse last applied to the sustain electrode to the first voltage, and when the subfield weight is the first weight, the first voltage is maintained at the sustain discharge pulse last applied to the sustain electrode. The time for which the subfield weight is the second weight greater than the first weight is shorter than the time for maintaining the first voltage in the sustain discharge pulse last applied to the sustain electrode. In this case, the total number of sustain discharges in the subfield may be 17 at the boundary between the first weight and the second weight.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The sustain electrodes X1 to Xn are formed corresponding to the scan electrodes Y1 to Yn, and generally have one end connected to each other in common. The plasma display panel 100 includes a glass substrate (not shown) in which the sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a glass substrate (not shown) in which the address electrodes A1 to Am are arranged. Is done. The two glass substrates are disposed to face each other so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an address electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode.

The scan electrode driver 500 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode.

Hereinafter, the driving waveforms applied to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn in each subfield will be described with reference to FIGS. 2 and 3. In the following description, a discharge cell formed by one address electrode, a sustain electrode, and a scan electrode is described. In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

2 and 3 are driving waveform diagrams of the plasma display panel according to the first and second embodiments of the present invention. In FIG. 2 and FIG. 3, only two subfields of the plurality of subfields are illustrated and represented as a first subfield and a second subfield, respectively. The reset period of the first subfield is shown as consisting of a rising period and a falling period, and the reset period of the second subfield is shown as being a falling period. The number of sustain discharge pulses of the first subfield illustrated in FIG. 2 is assumed to be less than the number of sustain discharge pulses of the second subfield illustrated in FIG. 3.

As shown in Figs. 2 and 3, each subfield is composed of a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

First, referring to FIG. 2, in the rising period of the reset period of the first subfield, a rising waveform that increases from the Vs voltage to the Vset voltage is applied to the scan electrode Y while the sustain electrode X is maintained at 0V. Then, a weak reset discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively, and negative wall charges are accumulated on the scan electrode Y, and the address electrode A and the sustain electrode are accumulated. Positive wall charges accumulate on the electrode X.

In the falling period of the reset period of the first subfield, a falling waveform of decreasing from the voltage Vs to the voltage Vnf is applied to the scan electrode Y while the sustain electrode X is maintained at the Ve voltage. Then, while the voltage of the scan electrode Y decreases, a weak reset discharge occurs between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A, and thus the scan electrode ( The negative wall charges formed on Y) and the positive wall charges formed on the sustain electrode X and the address electrode A are erased.

Next, in order to select a cell to be turned on in the address period of the first subfield, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the scan electrode Y and the address electrode A, respectively. The unselected scan electrode Y is biased to a VscH voltage higher than the VscL voltage, and a reference voltage is applied to the address electrode of the cell that is not turned on. Then, the address discharge occurs due to the difference between the address voltage Va and the scan voltage VscL and the wall voltage caused by the wall charges formed on the address electrode A and the scan electrode Y. As a result, a positive wall charge is formed at the scan electrode Y, and a negative wall charge is formed at the sustain electrode X. In addition, a negative wall charge is also formed on the address electrode A. FIG.

Subsequently, in the sustain period of the first subfield, the sustain discharge pulse of the Vs voltage is applied to the scan electrode Y and the sustain electrode X in order. Then, when the wall voltage is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period, the discharge is generated at the scan electrode Y and the sustain electrode X by the wall voltage and the Vs voltage. Happens. Thereafter, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X are repeated the number of times corresponding to the weight indicated by the corresponding subfield. do.

In this manner, when the sustain period of the first subfield ends, the second subfield starts. In the reset period of the second subfield, the reset period of the second subfield is performed only in the falling period. In the reset period of the second subfield, the sustain discharge pulse of the Vs voltage is applied to the scan electrode Y in the sustain period of the first subfield. The voltage at the electrode Y is gradually reduced to the voltage Vnf.

At this time, when sustain discharge has occurred in the sustain period of the first subfield, negative (-) wall charges are formed on the scan electrode (Y), and positive (+) wall charges are formed on the sustain electrode (X) and the address electrode (A). When the discharge start voltage is exceeded with the wall voltage formed in the cell while the voltage of the scan electrode Y is gradually decreasing, the weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the scan electrode Y is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield is equal to that of the first subfield. It becomes substantially the same as the wall charge state after the end of the falling period.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, no discharge occurs when the voltage of the scan electrode Y decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained as it is.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen.

The address period and the sustain period of the second subfield are the same as the first subfield, except that the sustain discharge pulse of the voltage Vs is applied to the scan electrode Y and the sustain electrode X in the sustain period of the second subfield. The difference is that the two subfields are alternately applied as many times as the number corresponding to the weight to be displayed.

At this time, when the subfield weight is low, the number of sustain discharge pulses applied in the sustain period is small, so that many priming particles are not generated by the discharge. On the contrary, when the subfield weight is high, the number of sustain discharge pulses applied during the sustain period is large, and thus priming particles are generated by the discharge.

In general, since the discharge space between the scan electrode and the sustain electrode, the surface where the address electrode is formed, and the surface where the scan and sustain electrode are formed acts as a capacitive load (hereinafter referred to as a panel capacitor), capacitance exists in the panel. . Therefore, in order to apply the waveform for sustain discharge, reactive power is required in addition to the power for sustain discharge. Therefore, the sustain discharge driving circuit of the plasma display panel generally includes a power recovery circuit for recovering and reusing reactive power. The power recovery circuit is a method of recovering and reusing reactive power by using a resonance of a capacitive load and an inductor, and there are circuits proposed by L.F.Weber (US Pat. Nos. 4,866,349 and 5,081,400) as such power recovery circuits.

At this time, the last sustain discharge pulse is applied to the sustain electrode X in the sustain period of the subfield having a small number of sustain discharge pulses through a power recovery circuit, and the sustain electrode X of the sustain period of the subfield having a large number of sustain discharge pulses. ), The last sustain discharge pulse is applied without going through the power recovery circuit.

That is, in applying the sustain discharge pulse in the sustain period, the last sustain discharge pulse is applied to the sustain electrode X in different ways for each subfield according to the number of sustain discharge pulses. That is, the last sustain discharge pulse is applied to the sustain electrode X of the subfield having a small number of sustain discharge pulses (less discharge priming) as shown in FIG. 2 through a power recovery circuit, and as shown in FIG. The last sustain discharge pulse is applied to the sustain electrode X of the subfield (which has a large amount of discharge priming) through the power recovery circuit. At this time, the last sustain discharge pulse in the sustain period of one subfield is applied to the scan electrode (Y).

Hereinafter, as shown in the driving waveforms according to the first and second exemplary embodiments of the present invention, the reason why the last sustain discharge pulse is different for each subfield is different in the sustain electrode X according to the number of sustain discharge pulses. It will be described in detail.

As described above, the discharge performed by applying a voltage between the two electrodes is delayed in time than when the voltage is applied, the discharge occurs. In particular, since the address discharge has to be performed within the widths of the scan pulse and the address pulse, the address discharge is greatly influenced by the discharge delay time. Since the address discharge is determined by the wall voltage due to the wall charges formed in the discharge space after the end of the reset period, the address discharge delay is affected by the wall charge state after the end of the reset period. Since the wall charge state after the end of the reset period is determined according to the wall charge state since the last sustain discharge of the immediately preceding subfield, the address discharge delay is also affected by the wall charge state of the immediately preceding subfield.

4 is a diagram showing the result of the last sustain discharge pulse of the sustain electrode generated by turning the power recovery circuit ON or OFF on the address discharge delay.

First, in order to obtain such a measurement result, while changing the total number of sustain discharge pulses in the sustain period, the last sustain discharge pulse of the sustain electrode is divided into the case where the power recovery circuit is used and the case where the power recovery circuit is not used. Measure the address discharge delay. In FIG. 4, a is a case where the last sustain discharge pulse is applied to the sustain electrode X through the power recovery circuit, and b is a case where the last sustain discharge pulse is applied to the sustain electrode X without passing through the power recovery circuit. will be.

As shown in Fig. 4, when the number of sustain discharge pulses is small (discharge priming is relatively small), the last sustain discharge pulse is applied to the sustain electrode through the power recovery circuit to the sustain electrode without passing through the power recovery circuit. When the address discharge delay is smaller than when the last sustain discharge pulse is applied and the number of sustain discharge pulses is large, the last sustain discharge pulse is applied to the sustain electrode through the power recovery circuit instead of through the power recovery circuit. It can be seen that the address discharge delay appears smaller than when the sustain discharge pulse is applied.

Therefore, the plurality of subfields are divided into a plurality of groups according to the total number of sustain discharge pulses in each subfield (in FIG. 4, the number of sustain discharge pulses is divided into subfields of the first and second groups based on 17). By applying the last sustain discharge pulses of the sustain electrodes differently to the subfields of each group, the address discharge delay can be shortened and stable address discharge can be generated.

Hereinafter, a sustain discharge driving circuit for generating a sustain discharge pulse last applied to the sustain electrode in accordance with the number of sustain discharge pulses in each subfield will be described in detail with reference to FIGS. 5 to 6B.

5 is a view showing a sustain discharge driving circuit according to an embodiment of the present invention. The switching element used in FIG. 5 is illustrated as an n-channel transistor, and may be made of a field effect transistor (FET) having a body diode, and may be made of another switching element having the same or similar function. In FIG. 5, the capacitive component formed by the sustain electrode X and the scan electrode Y is illustrated as a panel capacitor Cp for convenience.

As shown in FIG. 5, the sustain discharge driving circuit according to the embodiment of the present invention includes a power recovery circuit 410 and a sustain voltage supply unit 320.

The power recovery circuit 410 includes switching elements Xr and Xf, an inductor L, diodes D ₁ and D ₂ , and a capacitor C ₁ . The power recovery capacitor C1 is electrically connected between the drain of the switching element Xr and the source of the switching element Xf, and diodes D1 and D2 are connected in series to the switching elements Xr and Xf, respectively. . One end of the inductor L is electrically connected between a contact between the diodes D1 and D2 and a contact between the switching elements Xs and Xg of the sustain voltage driver 420, and a panel capacitor is connected to the other end of the inductor L. Cp) is connected in series. The diode D1 is for setting a rising path for increasing the voltage of the panel capacitor Cp when the switching element Xr has a body diode. The diode D2 is for setting a falling path for lowering the voltage of the panel capacitor Cp when the switching element Xf has a body diode. At this time, if the switching (Xr, Xf) does not have a body diode, the diode (D1, D2) may be removed. The connected power recovery circuit 410 is connected to the voltage of the panel capacitor (Cp) Vs It charges to voltage or discharges to ground voltage.

In the power recovery circuit 310, the order of connection between the inductor L, the diode D1 and the switching element Xr may be changed, and likewise between the inductor L, the diode D2 and the switching element Xf. The order of connections can also be changed.

The sustain voltage supply unit 420 is connected between the power recovery circuit 410 and the panel capacitor Cp, and includes two switching elements Xa and Xg. The switching element Xa is connected between the power supply supplying the sustain discharge pulse voltage Vs and the panel capacitor Cp, and the switching element Xg is connected between the power supply supplying the ground voltage and the panel capacitor Cp. It is connected. These switching elements Xa and Xg are connected to the panel capacitor Cp by Vs. Supply voltage and ground voltage respectively.

Next, an operation of the sustain discharge driving circuit for generating the last sustain discharge pulse of the sustain electrode in the drive waveform according to the embodiment of the present invention will be described with reference to FIGS. 6A to 6B.

As described above, the last sustain discharge pulse is applied to the sustain electrode through the power recovery circuit in the first subfield where the number of sustain discharge pulses is small, and the sustain electrode is not passed through the power recovery circuit in the second subfield where the number of sustain discharge pulses is large. Apply the last sustain discharge pulse to.

First, the operation of the sustain discharge driving circuit for generating the last sustain discharge pulse applied to the sustain electrode in the sustain period of the first subfield will be described.

6A and 6B are diagrams illustrating current paths in respective modes in the driving circuit of FIG. 5 for generating a last sustain discharge pulse applied to a sustain electrode in the driving waveform of FIG. 2 according to an exemplary embodiment of the present invention.

Before the start of mode 1 (M1), the switching element (Xg) is turned on so that the voltage across the panel is maintained at 0V, and the capacitor (C1) is half the voltage (Vs /) of the externally applied voltage (Vs). It is assumed that 2) is precharged, and the last sustain discharge pulse is applied to the sustain electrode X in the first subfield.

First, in mode 1 M1, the switching element Xr is turned on and the switching element Xg is turned off. Then, as shown in Fig. 6A, a path of the capacitor Cp-the switching element Xr-the diode D1-the inductor L-the panel capacitor Cp is formed (M1). The LC resonant circuit is formed by the path M1, and current is injected into the inductor L and the panel capacitor Cp. The voltage is charged in the panel capacitor Cp, and the voltage of the panel capacitor Cp is Vs. Increases to near voltage.

Next, in the mode 2 M2, the switching device Xs is turned on and the switching device Xr is turned off while the switching device Xr is turned on. Then, as shown in Fig. 6A, a path of the power supply Vs-the switching element Xs-the panel capacitor Cp is formed (M2). This path M2 causes the panel capacitor Cp to Keep the voltage.

Next, in the mode 3 M3, the switching device Xf is turned on and the switching device Xs is turned off while the switching device Xs is turned on. Then, as shown in Fig. 6B, a path of the panel capacitor Cp-inductor L-diode D2-switching element Xf-capacitor C1 is formed (M3). The LC resonant circuit is formed by this path M3, and the voltage charged in the panel capacitor Cp is discharged, so that the voltage of the panel capacitor p _P decreases to near 0V voltage.

Next, in the mode 4 M4, the switching device Xg is turned on and the switching device Xf is turned off while the switching device Xf is turned on. Then, as shown in Fig. 6B, a path of the panel capacitor Cp-the switching element Xg-the power supply 0V is formed (M4). By this path M4, capacitor Cp is 0V Keep the voltage.

As described above, in the sustain period of the first subfield, the last sustain discharge pulse is applied to the sustain electrode X through the resonance of the inductor L and the panel capacitor Cp through the paths M1-M4.

Next, the operation of the sustain discharge driving circuit for generating the last sustain discharge pulse applied to the sustain electrode X in the sustain period of the second subfield will be described in detail with reference to FIG. 7.

7 is a diagram illustrating a current path in each mode in the driving circuit of FIG. 5 for generating a last sustain discharge pulse applied to the sustain electrode in the driving waveform of FIG. 3 according to an exemplary embodiment of the present disclosure. As before, before the start of mode 1 (m1), the switching element (Xg) is turned on so that the voltage across the panel is maintained at 0V, and the capacitor (C1) is half the voltage applied to the externally applied voltage (Vs). It is assumed that (Vs / 2) is precharged, and the last sustain discharge pulse is applied to the sustain electrode X in the second subfield.

As shown in FIG. 7, in the mode 1 m1, the switching element Xs is turned on and the switching element Xg is turned off while the switching element Xg is turned on. Then, a path of the power supply Vs-the switching element Xs-the panel capacitor Cp is formed (m1). Vs to the panel capacitor Cp by this path m1. Apply voltage.

In mode 2 (m2), the switching element Xg is turned on and the switching element Xs is turned off while the switching element Xs is turned on. The path of the panel capacitor Cp-switching element Xg-power supply 0V is then formed (m2). 0V to capacitor Cp by this path m2 Supply the voltage.

In this manner, in the sustain period of the second subfield, the last sustain discharge pulse is applied to the sustain electrode X without resonating the inductor L and the panel capacitor Cp through the paths m1-m2.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the present invention, a plurality of subfields are divided into a plurality of groups according to the total number of sustain discharge pulses in each subfield, and the last sustain discharge pulse of the sustain electrode is recovered in power in a subfield of a group having a small number of total sustain discharge pulses. In the subfield of the group having a large number of total sustain discharge pulses, the last sustain discharge pulse of the sustain electrode is applied to the sustain electrode without passing through the power recovery circuit, thereby shortening the address discharge delay in the next subfield. I can do it.

Claims (10)

In a method of driving a frame divided into a plurality of subfields in a plasma display panel including a plurality of first electrodes and a plurality of second electrodes, the capacitive load being formed by the first electrode and the second electrode. , In the retention period, Alternately applying sustain discharge pulses for sustain discharge to the first electrode and the second electrode; Dividing the plurality of subfields into a plurality of groups including a first group and a second group according to the number of sustain discharge pulses applied to the first electrode and the second electrode, In the subfields of the first group, the last sustain discharge pulse applied to the first electrode is applied through resonance of the inductor electrically connected to the first electrode and the capacitive load, And in the subfields of the second group, the last sustain discharge pulse applied to the first electrode without applying the resonance. The method of claim 1, The number of sustain discharge pulses of the subfield having the largest number of sustain discharge pulses among the subfields of the first group, and the number of sustain discharge pulses of the subfields having the smallest number of sustain discharge pulses among the subfields of the second group. Method of driving. The method of claim 1, The last sustain discharge pulse of the sustain discharge pulses applied to the first electrode and the second electrode in the sustain period is applied to the second electrode. The method of claim 3, wherein And the first electrode is a sustain electrode, and the second electrode is a scan electrode. The method according to any one of claims 1 to 4, 17. A method of driving a plasma display panel, wherein groups are divided by 17 total sustain discharge pulses applied to the first electrode and the second electrode. A plasma display panel including a plurality of scan electrodes and a plurality of sustain electrodes, wherein a capacitive load is formed by the scan electrodes and the sustain electrodes; A driving circuit for dividing one frame into a plurality of subfields including a reset period, an address period, and a sustain period in the plasma display panel, and applying a driving voltage to the scan electrode and the sustain electrode; The drive circuit, In the sustain period of the first subfield among the plurality of subfields, Alternately applying a sustain discharge pulse of a first voltage for sustain discharge to the scan electrode and the sustain electrode, And a voltage change time of the sustain electrode in the sustain discharge pulse last applied to the sustain electrode in the sustain period of the first subfield according to the weight of the first subfield. The method of claim 6, If the time when the subfield weight is the first weight is changed from the sustain discharge pulse last applied to the sustain electrode to the first voltage is the second weight that the subfield weight is greater than the first weight And a change in the sustain voltage from the last sustain pulse applied to the electrode to the first voltage. The method of claim 6, When the subfield weight is the first weight, the holding time when the first voltage is maintained in the sustain discharge pulse last applied to the sustain electrode is the second weight when the subfield weight is greater than the first weight. 10. A plasma display device having a shorter time than a time for maintaining the first voltage in a sustain discharge pulse last applied to an electrode. The method according to claim 7 or 8, The boundary between the first weight and the second weight has a total sustain discharge number of 17 in the subfield. The method of claim 9, The last sustain discharge pulse of the sustain discharge pulses applied to the first electrode and the second electrode in the sustain period is applied to the second electrode.

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