KR100612345B1 - Plasma display device and driving method thereof - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof.

According to the present invention, when the auxiliary reset waveform is used in the subfield, the sustain voltage is applied to a part of the sustain period using hard switching, thereby lengthening the time for which the sustain voltage is applied, thereby making the sustain discharge stable.

Sustained Discharge, Auxiliary Reset, ERC, Hard Switching, Plasma

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a driving waveform diagram when a main reset waveform and an auxiliary reset waveform are used in a plasma display device according to the related art.

2 is a partial perspective view of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a diagram illustrating an electrode array of a plasma display panel according to an exemplary embodiment of the present invention.

4 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating details of waveforms applied in a first section of the sustaining period of FIG. 5.

FIG. 7 is a diagram illustrating details of waveforms applied in a second section of the sustaining period of FIG. 5.

8 is a circuit diagram illustrating a Y electrode driving circuit used in a sustain period of a plasma display device according to an embodiment of the present invention.

9A and 9B illustrate the operation of the circuit of FIG. 8.

The present invention relates to a plasma display device and a driving method thereof.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size.

In general, a plasma display device is driven by dividing one field into a plurality of subfields each having a weight, and a gray level is expressed by a sum of weights according to combinations of subfields to be turned on. Each subfield consists of a reset period, an address period, and a sustain period. The reset period serves to initialize the wall charge in order to stably perform the address discharge through the reset discharge. The address period is a period in which a wall charge is accumulated in cells that are turned on by selecting cells that are turned on and cells that are not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

In general, a large voltage is applied during the reset period because all cells must be initialized in the reset period. Due to such a large voltage, discharge occurs in all cells in the reset period, but even when a screen having a zero gray scale is represented, a reset discharge occurs and a contrast of the screen deteriorates.

Therefore, in order to prevent such a problem, a method of applying the reset waveform only in some subfields is disclosed in US Pat. No. 6,294,875 to Kurata et al.

1 is a driving waveform diagram using a main reset waveform and an auxiliary reset waveform according to the prior art.

The reset waveform used in the first subfield is a main reset waveform, which gradually rises to the Vset voltage and then gradually decreases to the Vnf voltage, and in the first subfield, reset discharge occurs in all discharge cells, and a wall is formed on each electrode. The charge builds up enough.

The reset waveform used in the second subfield is an auxiliary reset waveform, and gradually decreases to a Vnf voltage. The auxiliary reset waveform generates reset discharge only in the discharge cells discharged in the previous subfield and gradually increases the voltage of the waveform. Since it is not applied, less wall charge is accumulated on each electrode.

This mixture of main and secondary reset waveforms can improve the problem of poor contrast.

However, in the case of using the auxiliary reset waveform, since the wall charges are accumulated on the respective electrodes, there is a high possibility that the address discharge is poor when addressing the corresponding discharge cells, so that the discharge cells are sustained and discharged in the sustain period. There was a problem that this case is made unstable.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device and a driving method thereof in which a sustain discharge is stable in a sustain period even when an auxiliary reset waveform is used.

A driving method of a plasma display device according to a feature of the present invention for achieving the above object,

And a plurality of third electrodes formed in a direction crossing the plurality of first electrodes and the second electrode and the first electrode and the second electrode, wherein the discharge cells are formed by the first electrode, the second electrode, and the third electrode. In the plasma display device formed, a method of driving by dividing a field into a plurality of subfields,

At least one subfield of the plurality of subfields has an auxiliary reset period for initializing a discharge cell in which sustain discharge has occurred in a previous subfield,

The sustain period of the subfield having the auxiliary reset period is divided into a first interval and a second interval,

(a) applying a sustain voltage to the first electrode continuously for a first period of time in a first section; And

(b) applying a sustain voltage to the first electrode continuously for a second period of time shorter than the first period.

Plasma display device according to another aspect of the present invention,

In a plasma display device for driving one field divided into a plurality of subfields,

First substrate,

A plurality of first electrodes and second electrodes formed on the first substrate, respectively;

A second substrate facing away from the first substrate,

A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and

A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes;

The driving circuit may divide a sustain period of a subfield having an auxiliary reset period for initializing a discharge cell in which sustain discharge has occurred in a previous subfield into a first period and a second period, and in the first period, the first electrode. The sustain voltage is applied to the first electrode during the first period, and the sustain voltage is applied to the first electrode during the second period shorter than the first period.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge. The weak discharge refers to a discharge weaker than the discharge for addressing in the address period and the sustain discharge in the sustain period.

A plasma display device and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

2 is a partial perspective view of the plasma display panel, and FIG. 3 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the dielectric layer 7. The address electrode 8 and the partition 9 are formed on the dielectric layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the dielectric layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell (hereinafter referred to as a "cell") 12. .

As shown in FIG. 3, the electrode of the plasma display panel has an n × m matrix structure. The address electrodes A1-Am extend in the column direction, and the scan electrodes Y1-Yn and the sustain electrodes X1-Xn are arranged in pairs in the row direction.

4 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display device according to the exemplary embodiment of the present invention includes a plasma display panel 100, an address electrode driver 200, a scan and sustain electrode driver 300, and a controller 400.

The plasma display panel 100 includes a plurality of address electrodes A1-Am extending in the column direction, and a plurality of sustain electrodes X1-Xn and scan electrodes Y1-Yn extending in pairs in the row direction. Include. The sustain electrodes X1-Xn are formed corresponding to the scan electrodes Y1-Yn, and generally have one end connected in common with each other. The plasma display panel 100 includes an insulating substrate (not shown) in which the sustain and scan electrodes X 1 -X n and Y 1 -Y n are arranged, and an insulating substrate (not shown) in which the address electrodes A 1 -A m are arranged. Is done. The two insulating substrates are disposed to face each other so that the scan electrodes Y1-Yn and the address electrodes A1-Am and the sustain electrodes X1-Xn and the address electrodes A1-Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1-Am and the sustain and scan electrodes X1-Xn and Y1-Yn forms a cell.

The controller 400 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one field into a plurality of subfields having respective weights, and a gray level is expressed by a combination of weights of subfields to be turned on. The controller divides and drives one subfield into a reset period, an address period, and a sustain period.

In the reset period, the driving units 200 and 300 apply waveforms for resetting to the address, sustain and scan electrodes A1-Am, X1-Xn, and Y1-Yn to set the cells in an addressable state. This reset period is divided into a reset period for applying a main reset waveform and a reset period for applying an auxiliary reset waveform. Here, the main reset waveform gradually rises from the voltage of Vs to the Vset voltage and then gradually falls to the Vnf voltage, and the auxiliary reset waveform gradually falls from the voltage of Vs to the Vnf voltage.

In this embodiment, a reset period for applying a main reset waveform and a reset period for applying an auxiliary reset waveform are used in combination in each subfield. Preferably, the main reset waveform is applied in the subfield appearing at the beginning of one frame, and the auxiliary reset waveform is applied in the other subfield.

In the address period, the driving units 200 and 300 apply the selection voltages to the scan electrodes Y1-Yn in the order in which the scan electrodes Y1-Yn are selected (for example, sequentially). When the selection driving voltage is applied to each scan electrode by receiving the address driving control signal, an address voltage for selecting a cell to be turned on is applied to each address electrode A1-Am. That is, a cell formed by the scan electrode to which the selection voltage is applied in the address period and the address electrode to which the address voltage is applied when the selection voltage is applied to the scan electrode is selected as the cell to be turned on.

In the sustain period, the scan and sustain driver 300 receives a control signal from the controller 200 and applies a sustain voltage for sustain discharge to the sustain electrodes X1-Xn and the scan electrodes Y1-Yn. In this case, the application of the sustain voltage for sustain discharge uses an energy recovery circuit (ERC).

In the embodiment of the present invention, when the main reset waveform is applied in the reset period of the subfield, the application of the sustain voltage uses ERC. When the auxiliary reset waveform is applied to the reset period of the subfield, the sustain period is divided into a first period and a second period, and in the first period, the sustain voltage is directly applied (hard switched) without using ERC. Lengthen the application time of the voltage.

Next, the driving waveforms applied to the address electrodes A1-Am, sustain electrodes X1-Xn and scan electrodes Y1-Yn in each subfield will be described in detail with reference to FIGS. 5 to 7. The cell formed by one address electrode (hereinafter referred to as "A electrode"), sustain electrode (hereinafter referred to as "X electrode"), and scan electrode (hereinafter referred to as "Y electrode") is referred to below. Explain with.

As shown in Fig. 5, one subfield includes a reset period, an address period, and a sustain period. In the reset period shown in FIG. 5, an auxiliary reset waveform is applied, and the sustain period is divided into a first period and a second period.

First, an auxiliary reset waveform gradually descending from the voltage Vs to the voltage Vnf is applied to the Y electrode in the reset period of the subfield.

The auxiliary reset waveform will be described in detail. The voltage of the Y electrode is decreased from the voltage of Vs to the voltage of Vnf while the A electrode and the X electrode are biased with the reference voltage (where the reference voltage is 0V) and the Ve voltage, respectively. .

At this time, in the discharge cell in which the discharge occurred in the immediately preceding subfield, the weak discharge occurs between the Y electrode and the X electrode while the voltage of the Y electrode decreases, and the weak discharge occurs again between the Y electrode and the A electrode. This erases the negative wall charges of the Y electrode and erases the positive wall charges of the X and A electrodes. In general, the Ve voltage and the Vnf voltage are set such that the wall voltage between the Y electrode and the X electrode is close to 0 V so that a cell which is not selected in the address period does not cause an erroneous discharge in the sustain period. That is, the voltage (Ve-Vnf) is set to about the discharge start voltage Vfxy between the Y electrode and the X electrode.

In the discharge cells in which the discharge did not occur in the immediately preceding subfield, since wall charges are not sufficiently accumulated on each electrode, reset discharge does not occur, and the wall charge state of each electrode is maintained as it is.

Next, in order to select a cell to be turned on while the X electrode is maintained at the Ve voltage in the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes, respectively. The unselected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the address electrode of the cell that is not turned on. At this time, the VscL voltage may be the same as or different from the Vnf voltage.

Specifically, a scan pulse of VscL voltage is applied to one Y electrode and an address pulse of Va voltage is applied to an A electrode located in a cell to be displayed. Then, a discharge occurs between the Y electrode and the A electrode to which the Va voltage is applied, and then a discharge occurs between the Y electrode and the X electrode adjacent to the scan electrode, thereby providing a positive wall charge to the Y electrode, the A electrode and the X electrode. Negative wall charges are formed at each.

However, when the auxiliary reset waveform is used during the reset period, since there is no waveform gradually increasing from the Vs voltage to the Vset voltage as in the main reset waveform of the first subfield shown in FIG. There is not enough wall charge to accumulate. Therefore, in this case, address discharge often occurs incompletely.

In the embodiment of the present invention, when the auxiliary reset waveform is applied to the reset period of the subfield, the sustain period is divided into a first period and a second period, and in the first period, Vs is formed using hard switching as shown in FIG. 6. Voltage is applied, and in the second section, Vs voltage is applied using ERC as shown in FIG. 7.

That is, in the conventional technology, the Vs voltage is always applied in the sustain period using ERC. However, in the embodiment of the present invention, the sustain period is divided into the first and second intervals in the subfield using the auxiliary reset waveform. Apply Vs voltage using hard switching.

When the Vs voltage is applied using hard switching as shown in FIG. 6, the time for which the Vs voltage is maintained is longer as compared with applying the Vs voltage using ERC as shown in FIG. 7.

In this manner, in the sustain period, a sustain discharge pulse having a voltage of Vs is first applied to the Y electrode, and a reference voltage is applied to the X electrode. At this time, the Vs voltage is a voltage capable of causing a discharge between the Y electrode and the X electrode together with the wall voltage formed between the Y electrode and the X electrode by the address discharge. Then, in the cell in which the discharge occurred in the address period, the discharge occurs between the Y electrode and the X electrode. In addition, negative and negative wall charges are accumulated on the Y and X electrodes of the cell in which the sustain discharge has occurred, and negative (-) wall charges are accumulated on the A electrode.

Here, the discharge cell is discharged after a predetermined time while the Vs voltage, which is the sustain voltage, is applied to the electrode. The time between discharges at the time when the Vs voltage is applied is called a discharge delay. The discharge delay becomes longer when the reset discharge or the address discharge is incompletely generated and wall charges are not sufficiently accumulated.

As shown in FIG. 6, when the hard switching is used, the application time of the Vs voltage is long, and when the ERC is used as shown in FIG. 7, the application time of the Vs voltage is short.

Therefore, in the embodiment of the present invention, when the auxiliary reset waveform is used in the reset period, the discharge may occur incompletely in the address period and the wall charges may not be sufficiently accumulated. Therefore, hard switching may be used in the first period of the sustain period. The sustain discharge is made stable by applying the Vs voltage to increase the time for which the Vs voltage is maintained.

The positive and negative wall charges are sufficiently accumulated on the Y and X electrodes of the cell in which the sustain discharge is stably generated, and the positive (+) wall charges are also accumulated on the A electrode, respectively. The sustain discharge is stable even when the Vs voltage is applied.

8 is a circuit diagram illustrating a Y electrode driving circuit used in a sustain period of a plasma display device according to an embodiment of the present invention.

Such a Y driver driving circuit includes an inductor L, switches Sw1-Sw4, diodes D1, D2, and a power recovery capacitor Css. The switches Sw1-Sw4 are generally implemented using transistors. In the switches Sw1 and Sw2 using the transistors, the diodes D1 and D2 are formed in the opposite direction to the body diodes of the switches Sw1 and Sw2 in order to block currents that may be formed by the body diodes.

In the power recovery circuit, the first terminal of the inductor L is electrically connected to the Y electrode of the panel capacitor Cp including the X electrode and the Y electrode, and the second terminal and the power recovery capacitor Css of the inductor L are electrically connected. The first switch (Sw1) for electrically connecting between the first terminal of the () and the second switch (Sw2) for electrically connecting between the second terminal of the inductor and the power recovery capacitor (Css).

In addition, a third switch Sw3 for electrically connecting the contact between the Y electrode and the first terminal of the inductor and the first power supply Vs, and the rear discharge electrode and the first terminal of the inductor L, respectively. And a fourth switch Sw4 that electrically connects between the contact point and the second power source (ground power source). Here, a second power source (ground power supply) is connected to the second terminal of the power recovery capacitor Css, and a voltage corresponding to the voltage Vs / 2 is charged in the capacitor Css.

In the first section of the sustain period, the first and second switches Sw1 and Sw2 remain in an off state, and the third and fourth switches Sw3 and Sw4 are alternately turned on and off so that the reference voltage and Vs are applied to the Y electrode. Apply voltage alternately.

In the second section of the sustain period, as shown in FIGS. 9A and 9B, the Vs voltage is applied to the Y electrode by using the ERC.

In detail, referring to FIG. 9A, the first switch Sw1 is turned on while the fourth switch Sw4 is turned on and the Y electrode is maintained at the reference voltage. Then, a current flows in the inductor L through the paths of the power recovery capacitor Css, the first switch Sw1, the inductor L, the fourth switch Sw4, and the second power source (ground voltage) (1). . The fourth switch Sw4 is turned off while a current flows in the inductor L, thereby resonating between the inductor L and the panel capacitor Cp through the capacitor Css, the first switch Sw1, and the inductor L. Occurs (2). This resonance raises the voltage of the Y electrode to the voltage Vs. Subsequently, the first switch Sw1 is turned off and the third switch Sw3 is turned on to maintain the voltage of the Y electrode at the voltage Vs (③).

Referring to FIG. 9B, the second switch Sw2 is turned on while the voltage of the Y electrode is maintained at the voltage Vs, so that the power source Vs, the third switch Sw3, the inductor L, and the second switch Sw2 are turned on. And a current in a direction opposite to that of FIG. 9A flows through the inductor L through the path of the capacitor Css (④). The third switch Sw3 is turned off while a current flows in the inductor L, and thus the inductor L and the panel capacitor Cp pass through the inductor L, the second switch Sw2, and the capacitor Css. Resonance occurs between (⑤). This resonance causes the voltage of the Y electrode to drop to the reference voltage. Subsequently, the second switch Sw2 is turned off and the fourth switch Sw4 is turned on to maintain the voltage of the Y electrode at the reference voltage (6).

9A and 9B are repeated to apply the sustain discharge pulse to the Y electrode swinging from the Vs voltage to the reference voltage.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, when the auxiliary reset waveform is used in the subfield, the sustain voltage is applied to a part of the sustain period by using hard switching, so that the sustain discharge can be made stable.

Claims (7)

And a plurality of third electrodes formed in a direction crossing the plurality of first electrodes and the second electrode and the first electrode and the second electrode, wherein the discharge cells are formed by the first electrode, the second electrode, and the third electrode. In the plasma display device formed, a method of driving by dividing a field into a plurality of subfields, At least one subfield of the plurality of subfields has an auxiliary reset period for initializing a discharge cell in which sustain discharge has occurred in a previous subfield, The sustain period of the subfield having the auxiliary reset period is divided into a first interval and a second interval, (a) applying a sustain voltage to the first electrode and the second electrode alternately in a first section for a time period of a first period; And (b) in the second section, applying a sustain voltage to the first electrode and the second electrode by LC resonance of an energy recovery circuit for a period of a second period shorter than the first period. Method of driving. delete delete delete In a plasma display device for driving one field divided into a plurality of subfields, First substrate, A plurality of first electrodes and second electrodes formed on the first substrate, respectively; A second substrate facing away from the first substrate, A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes; The driving circuit may divide a sustain period of a subfield having an auxiliary reset period for initializing a discharge cell in which sustain discharge has occurred in a previous subfield into a first period and a second period, and in the first period, the first electrode. And applying a sustain voltage to a second electrode alternately for a time period of a first period, and in a second interval, alternately applying the sustain voltage to the first electrode and a second electrode for a second period of time shorter than the first period. A plasma display device applying a sustain voltage by LC resonance. delete delete

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