KR100521482B1 - A driving method of plasma display panel - Google Patents

Abstract

The method of driving a plasma display panel according to the present invention divides the plurality of scan electrodes into a plurality of groups in an address period, selectively applies a first voltage to a scan group of a first group among the plurality of scan electrodes, and The first voltage is selectively applied to the second group of scan electrodes. The voltage of the address electrode is changed through resonance of the inductor electrically connected to the address electrode and the capacitive load while the first voltage is applied to the scan electrodes of the first group, and then the address voltage is applied to the address electrode. The address voltage is applied to the address electrode without the resonance while the first voltage is applied to the scan electrode of the second group. In this way, low discharge can be prevented in the address period.

Description

A method for driving a plasma display panel {A DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type because the electrode is protected from the impact of ions during discharge.

In such an AC plasma display panel, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a partial perspective view of a typical AC plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 4 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m extend in the column direction and the scan electrode Y in the row direction. _{1 to} Y _n and the sustain electrodes X _{1 to} X _n extend. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

3 is a driving waveform diagram of a conventional plasma display panel.

As shown in FIG. 3, each subfield has a reset period P _r , an address period P _a , and _a sustain period P _s. )

The reset period P _r serves to set up the wall charge to erase the wall charge formed by the previous sustain discharge and to stably perform the next address discharge. An address period (P _a) is turned on to select a cell does not turn on, and the cell is turned on, the panel is a period for performing the operations laying up the wall charges in the cells (the addressed cells). The sustain period P _s is a period in which sustain discharge is performed to actually display an image in the addressed cell.

Conventional plasma In the address period (P _a) in the driving waveform of the display panel, an address period (P _a) in the scan in sequence to the scan electrodes (Y) and the address electrode (A) for selecting discharge cells to be displayed pulses and An address pulse is applied. At this time, the scan pulse is a pulse that selects scan electrode Y by applying V _scL voltage to scan electrode Y sequentially while maintaining the other scan electrode Y at V _scH voltage, and the address pulse is V _scL. voltage is a pulse to be applied to the applied address voltage (V _a) to the address electrode (a) to form a discharge cell to be selected among the discharge cells formed by the scan electrode (Y). In this way, the address discharge by the difference between the voltage (V _a) and a voltage (V _scL) applied to the scan electrode (Y) applied to the address electrode (A) is made.

In general, since the discharge space between the scan electrode and the sustain electrode, the surface where the address electrode is formed, and the surface where the scan and sustain electrode are formed acts as a capacitive load (hereinafter referred to as a panel capacitor), capacitance exists in the panel. . Therefore, in order to apply the waveform for addressing, reactive power is required in addition to the power for addressing. Therefore, the address driving circuit of the plasma display panel generally includes a power recovery circuit for recovering and reusing reactive power. As such a power recovery circuit there is a circuit proposed by L.F.Weber (US Pat. Nos. 4,866,349 and 5,081,400).

The power recovery circuit recovers and reuses reactive power using the resonance of the capacitive load and the inductor. The power recovery circuit recovers and reuses reactive power, but the voltage V _{a is} applied to the address electrode after LC resonance. Is applied to delay the application time of the voltage V _a by the resonance time. Thus, address discharge is formed late. In addition, it is a shorter period of time _a voltage V is applied about the address discharge because the required resonance time. In particular, where scanning is performed behind the scenes, there is no priming, so that address discharge does not occur well, and low discharge may occur.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve such a conventional problem, and to provide a method of driving a plasma display panel that can stably generate an address discharge in an address period.

According to an aspect of the present invention, a plasma display panel including a plurality of scan electrodes and a plurality of address electrodes formed in a direction crossing the scan electrodes and driving a capacitive load formed by the scan electrodes and the address electrodes is driven. A method is provided. The driving method includes a first step of dividing the plurality of scan electrodes into a plurality of groups in an address period, and selectively applying a first voltage to scan electrodes of a first group among the plurality of scan electrodes, and the plurality of scan electrodes. And a second step of selectively applying the first voltage to a scan group of a second group of scan electrodes, wherein the inductor is electrically connected to the address electrode while the first voltage is applied to the scan group of the first group. And after changing the voltage of the address electrode through the resonance of the capacitive load, applying an address voltage to the address electrode, and resonating the address electrode while the first voltage is applied to the scan electrode of the second group. The address voltage is applied without. In addition, while the first voltage is applied to the scan electrodes of the first group, the address is generated through resonance of the inductor electrically connected to the address electrode and the capacitive load after the address voltage is applied to the address electrode. Change the voltage of the electrode, apply the viadress voltage to the address electrode, and apply the address voltage to the address electrode after the address voltage is applied to the address electrode while the first voltage is applied to the scan electrode of the second group. Apply viadress voltage without resonance.

According to another aspect of the invention, the driving method divides the plurality of scan electrodes into a plurality of groups in an address period, and selectively applies a first voltage to the scan electrodes of the first group of the plurality of scan electrodes. And a second step of selectively applying the first voltage to scan electrodes of a second group among the plurality of scan electrodes, wherein the first voltage is applied to the scan electrodes of the first group. While the time for changing the voltage of the address electrode from the viadress voltage to the address voltage changes the voltage of the address electrode from the viadress voltage to the address voltage while the first voltage is applied to the scan electrode of the second group. Longer than time The time for changing the voltage of the address electrode from the address voltage to the viadress voltage while the first voltage is applied to the scan electrodes of the first group is equal to the first voltage of the scan electrodes of the second group. It is longer than the time for changing the voltage of the address electrode from the address voltage to the viadress voltage while it is being applied.

The driving method may include applying the first voltage to the scan electrodes of the first group and then applying the first voltage to the scan electrodes of the second group, and applying the first voltage to the scan electrodes of the first group. The period of holding the address voltage applied to the address electrode while the voltage is applied is greater than the period of holding the address voltage applied to the address electrode while the first voltage is applied to the scan electrode of the second group. short.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. In addition, when a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

The wall charges are charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Hereinafter, a driving apparatus and a driving method thereof of a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. do.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, a plurality of sustain electrodes X1 to Xn arranged in the row direction, and scan electrodes Y1 to Yn.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y driving control signal.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

In the present invention, the plurality of scan electrodes are divided into a plurality of groups, and the address voltages applied to the address electrodes are applied in different ways while the scan voltages are applied to the scan electrodes of each group.

5 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention. In FIG. 5, the description of the reset period and the sustain period will be omitted, and only the address period will be described. The scan period is divided into two groups G1 and G2 according to the order in which the scan voltages are applied to the plurality of scan electrodes. Only the first scan electrode and the j-th scan electrode are shown, and the i-th scan electrode belongs to the group G1 and the j-th scan electrode belongs to the group G2. The scan voltage is applied to the scan electrodes belonging to the group G1 before the group G2.

As shown in FIG. 5, according to an exemplary embodiment of the present invention, an address voltage is applied to an address electrode through a power recovery circuit while a scan voltage is applied to a scan electrode of a first group, and a scan voltage is applied to a scan electrode of a second group. While applied, the address voltage is applied to the address electrode without going through the power recovery circuit.

Referring to FIG. 5, one frame in the driving waveform of the plasma display panel according to an embodiment of the present invention is driven is divided into a plurality of subfields, each subfield is divided into a reset period (P _r), an address period (P _a) and And the holding period P _s . And the reset period includes a rising ramp period and a falling ramp period.

The rising ramp period of the reset period P _r is a period in which wall charges are formed in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period is a part of the wall charges formed in the rising ramp period. This is a period for erasing to facilitate address discharge. The address period Pa is _a period for selecting a discharge cell to cause sustain discharge in the sustain period from among the plurality of discharge cells, and the sustain period P _s is a sustain pulse sequentially applied to the scan electrode Y and the sustain electrode X. in applying to the address period (P _a) is a period during which sustain discharge for selected discharge cells.

In the plasma display panel, a scan / hold driving circuit for applying a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

First, in the rising ramp period of the reset period P _r , the address voltage A and the sustain electrode X are kept at 0 V, and the ramp voltage gradually rising from the V _s voltage to the V _set voltage is applied to the scan electrode Y. Is applied. While this ramp voltage is rising, weak reset discharge occurs in all the discharge cells from the scan electrode Y to the address electrode A and the sustain electrode X, respectively. As a result, negative wall charges are formed on the scan electrode Y, and positive wall charges are formed on the address electrode A and the sustain electrode X at the same time.

In the falling ramp period of the reset period P _r , the ramp voltage gradually falling toward the V _nf voltage from the V _s voltage to the scan electrode Y while maintaining the sustain electrode X at the constant voltage V _e voltage. Is authorized. Then, while this lamp voltage falls, the weak reset discharge occurs again in all the discharge cells. Due to this discharge, the negative wall charges of the scan electrode Y are reduced and the positive wall charges of the sustain electrode X and the address electrode A are erased.

And applying an address period (P _a) in the sustain electrode (X) and the scan voltage (V _scL) in sequence in a holding state to another scan electrode (Y) to V _e voltage V _scH voltage respectively to the scan electrode (Y) The scan electrode Y is selected. And it applies an address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the V _scL voltage is applied to the scan electrode (Y). Then, an address voltage applied to the electrodes (A) (V _a) and the differential, and the address electrode wall by wall charges formed in the (A) and scan electrodes (Y) of the voltage (V _scL) applied to the scan electrode (Y) The address discharge occurs between the address electrode A and the scan electrode Y and between the sustain electrode X and the scan electrode Y by the voltage. As a result, (+) wall charges are formed on the scan electrode (Y) and (-) wall charges are formed on the sustain electrode (X).

And an address period (P _a) a plurality of groups of the plurality of scan electrodes (Y) in (G1, G2) to divide address while the applied V _scL voltage to the scan electrode in the group (G1) of the plurality of scan electrodes (Y) electrodes to apply an address voltage without an address electrode during the resonance is applied _scL V voltage to the scan electrode during applying an address voltage (V _a) by using a resonance, and a plurality of scan electrode group (G2). That is, while the V _scL voltage is applied to the scan electrodes of the group G2, the time taken until the address voltage is applied to the address electrodes is applied to the address electrodes while the V _scL voltage is applied to the scan electrodes of the group G1. It is shorter than the time taken to apply. In this case, while the V _scL voltage is applied to the scan electrodes of the group G2, the address voltage application time of the address electrodes is shortened by the resonance time, and a momentary change occurs to the address voltage, so that the wall charges formed by the reset discharge are changed over time. Discharge can also occur well in cells in the second group that are heavily erased.

Next, in the sustain period P _s , a sustain discharge (sustain) pulse is applied to the scan electrode Y and the sustain electrode X in order. The sustain discharge pulse is a pulse that causes the voltage difference between the scan electrode Y and the sustain electrode X to alternately become a V _s voltage and a -V _s voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at.

Hereinafter, the address driving circuit included in the address driver is assumed in detail with reference to FIG. 6, assuming that the selection voltage V _n applied to the selected scan electrode and the reference voltage applied to the address electrode not selected are ground voltages. Explain.

6 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention. These switching elements used in FIG. 6 may be made of a field effect transistor (FET) having a body diode, and may be made of other switching elements having the same or similar functions.

As illustrated in FIG. 6, an address driving circuit according to an exemplary embodiment of the present invention includes an address power recovery circuit 310, an address voltage supply unit 320, and an address selection circuit 330 _{1 to} 330 _m . The address selection circuits 330 _{1 to} 330 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switching elements A _H and A _L , respectively.

The switching element A _{H is} connected between the power recovery circuit 310 and the address electrodes A ₁ -A _m , and the switching element A _L is connected between the address electrodes A ₁ -A _m and the ground voltage. Thus, the address electrode is selected or not selected by turning on or off the switching elements A _H and A _L. That is, the address period is selected (P _a) and the address electrode is applied is turned on and the switching element (A _H) is turned on at the switching element (A _L) of the ground voltage applied to the address electrode is not selected. Here, the ground voltage applied to the unselected address electrodes is also referred to as a beer dress voltage.

The address voltage supply unit 320 is connected between the address power recovery circuit 310 and the address selection circuits 330 _{1 to} 330 _m , and the address voltage supply unit 320 includes two switching elements A _a and A _g . do. The switching device (A _a) is connected between the switching element (A _H) of the address voltage (V _a) power supply and the address selection circuit (330 ₁ ~330 _m) for supplying the switching element (A _g) is a ground voltage It is connected between the power supply for supplying the switching element (A _H ) of the address selection circuit (330 ₁ ~ 330 _m ). The switching elements A _a and A _g supply the voltage V _a and the ground voltage to the panel capacitor C _P , respectively.

The power recovery circuit 310 includes a switching element _Ar , A _f , an inductor L, a diode D ₁ , D ₂ , and a capacitor C _a . The switching device (A _r) drain and a switching device power recovery capacitor (C _erc) between the source of (A _f) and is electrically coupled to a respective diode to the switching element _{(A r, A f) (} D 1, D ₂ ) are connected in series. And Diodes one end is electrically connected to the inductor (L _erc) of (D _1, D _2), the inductor (L _erc) between the liver between the switching device (A _s, A _g) of the contact and address voltage driver 320 contacts At the other end of the panel capacitor (C _P ) is connected in series. The diode D ₁ is for setting a rising path for increasing the voltage of the panel capacitor C _P when the switching element Y _r has a body diode. The diode D ₂ is for setting a falling path for lowering the voltage of the panel capacitor C _P when the switching element Y _f has a body diode. At this time, if the switching (Y _r , Y _f ) does not have a body diode, the diode (D ₁ , D ₂ ) may be removed.

And the connection order between the power recovery circuit 310, the inductor (L), a diode (D ₁₎ and the switching element (A _r) in may change, as in the inductor (L), a diode (D ₂₎ and switching device (A _The order of connections between _f ) can also be changed.

The connected power recovery circuit 310 charges the voltage of the panel capacitor C _P to the voltage V _a or discharges it to the ground voltage.

Next, an operation of the address driving circuit according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7 to 8. 7 and 8 illustrate only one address selection circuit for convenience of description, and a capacitive component formed by the address electrode A and the scan electrode Y is illustrated as a panel capacitor. As described above, the ground voltage is applied to the scan electrode Y side of the panel capacitor.

As described above, according to the present invention, the LC resonance is applied while the scan voltage is applied to the first electrode and the scan voltage is applied to the address electrode while the scan voltage is applied to the scan electrode of the first group. The address voltage is applied to the address electrode without passing through.

First, an operation of the address driving circuit for generating an address pulse applied to the address electrode while the scan voltage is applied to the first group of scan electrodes will be described in detail with reference to FIGS. 7A and 7D.

7A and 7B are diagrams illustrating current paths in respective modes of the driving circuit of FIG. 6 for generating an address voltage applied to an address electrode while a scan voltage is applied to the first group of scan electrodes in FIG. 5. Before the start of mode 1, the switching elements A _g and A _H are conducted so that the voltage across the panel (V _P ) is maintained at 0 V, and the capacitor C _a is applied to 1 / of the externally applied voltage (V _a ). Assume that two voltages (V _a / 2) are charged in advance.

First, in mode 1, the switching element A _r is turned on and the switching element A _g is turned off while the switching element A _H is turned on. Then, as shown in FIG. 7A, the path M1 of the capacitor C _a -the switching element A _r -the diode D ₁ -the inductor L-the switching element A _H -the panel capacitor C _P is shown. Is formed. Voltage is formed in the LC resonance circuit by the path (M1) and the current in the inductor (L) and the panel capacitor (C _P) injection, the voltage charged in the panel capacitor (C _P) the panel capacitor (C _P) is Increase to near the voltage V _a .

Next, in mode 2, the switching device A _a is turned on and the switching device A _r is turned off while the switching devices A _H and A _r are turned on. Then, as shown in Figure 7a, the power (V _a) - the switching device _{(A a)} - the switching device (A _H) - the path (M2) of the panel capacitor (C _P) is formed. This path M1 causes the panel capacitor C _P to maintain the voltage V _a .

Next, in mode 3, the switching element A _f is turned on and the switching element A _a is turned off while the switching elements A _H and A _a are turned on. Then, as shown in FIG. 8B, the path M3 of the panel capacitor C _P -the switching element A _H -the inductor L-the diode D ₂ , the switching element A _f , and the capacitor C _a is obtained. Is formed. The LC resonance circuit is formed by the path (M3) is a discharge voltage that is charged in the panel capacitor (C _P) decreases to near the 0V voltage is the voltage of the panel capacitor (C _P).

Next, in mode 4, the switching device A _g is turned on and the switching device A _f is turned off while the switching devices A _H and A _f are turned on. Then, as shown in Fig. 8B, the path M4 of the panel capacitor C _P -switching element A _H -switching element A _g -power source 0V is formed. By this path M4, capacitor C _P is 0V Keep the voltage.

Thus, through the resonance of the inductor (L) and the panel capacitor address electrode while the scan voltage to the scan electrodes of the first group is there via a line _{(M1-M4) (C P} ) and applies an address voltage (V _a) .

Next, while the scan voltage is applied to the last scan electrode of the first group, the address voltage V _a is applied to the address electrode A through the path M-M4 and then to the first scan electrode of the second group. The operation of the address driving circuit for generating an address pulse applied to the address electrode A while the scan voltage is applied will be described in detail with reference to Figs. 8A to 8B.

8A and 8B are diagrams illustrating a current path in each mode of the driving circuit of FIG. 6 for generating an address voltage applied to an address electrode while a scan voltage is applied to a scan electrode of a second group in FIG. 5. As before, before the start of mode 1, the switching elements A _g and A _H are conducting so that the voltage across the panel V _P is maintained at 0V.

First, as shown in FIG. 8A, in mode 1, the switching element A _a is turned on while the switching element A _H is turned on. Then, as shown in Figure 8a, the power (V _a) - the switching device _{(A a)} - the switching device (A _H) - the panel capacitor is formed with a path _(P C) (m1). This path supplies the V _a voltage to the panel capacitor C _P.

As shown in FIG. 8B, in mode 2, the switching element A _g is turned on and the switching element A _a is turned off while the switching elements A _H and A _a are turned on. Then, as shown in Fig. 9B, a path of the panel capacitor C _P -switching element A _H -switching element A _g -power source 0 V is formed (m2). 0V to capacitor C _P by this path (m2) Supply the voltage.

Thus, to apply the address voltage (V _a) to the address electrode without using a resonator via a line (m1-m2) while applying a scan voltage to the scan electrodes of the second group. This makes possible to apply the voltage V _a to the address electrode (A) as soon and may cause a stable discharge in the second group because the longer the period V _a voltage holding a reduced a lot of wall charges formed by the reset discharge.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, there is an effect that the low discharge generated due to poor address discharge in the address period can be eliminated.

1 is a schematic partial perspective view of an AC plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

6 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

7A to 7B are diagrams illustrating current paths in respective modes of the driving circuit of FIG. 6 for generating an address voltage applied to an address electrode while a scan voltage is applied to the first group of scan electrodes in FIG. 5.

8A to 8B are diagrams illustrating current paths in respective modes of the driving circuit of FIG. 6 for generating an address voltage applied to an address electrode while a scan voltage is applied to a scan group of a second group in FIG. 5.

Claims (7)

A method of driving a plasma display panel comprising a plurality of scan electrodes and a plurality of address electrodes formed in a direction crossing the scan electrodes, wherein a capacitive load is formed by the scan electrodes and the address electrodes. In the address period, Dividing the plurality of scan electrodes into a plurality of groups, A first step of selectively applying a first voltage to scan electrodes of a first group among the plurality of scan electrodes, and A second step of selectively applying the first voltage to a second group of scan electrodes of the plurality of scan electrodes, While the first voltage is applied to the scan electrodes of the first group, an address voltage is applied to the address electrode after changing the voltage of the address electrode through resonance of the inductor electrically connected to the address electrode and the capacitive load. and, And applying the address voltage to the address electrode without the resonance while the first voltage is applied to the second group of scan electrodes. The method of claim 1, While the first voltage is applied to the scan electrodes of the first group, after the address voltage is applied to the address electrode, the inductor electrically connected to the address electrode and resonance of the capacitive load are connected to each other. Change a voltage and apply a beer dress voltage to the address electrode; And applying a viadress voltage to the address electrode without the resonance after the address voltage is applied to the address electrode while the first voltage is applied to the scan electrodes of the second group. A method of driving a plasma display panel comprising a plurality of scan electrodes and a plurality of address electrodes formed in a direction crossing the scan electrodes, wherein a capacitive load is formed by the scan electrodes and the address electrodes. In the address period, Dividing the plurality of scan electrodes into a plurality of groups, A first step of selectively applying a first voltage to scan electrodes of a first group among the plurality of scan electrodes, and A second step of selectively applying the first voltage to a second group of scan electrodes of the plurality of scan electrodes, The time for changing the voltage of the address electrode from the viadress voltage to the address voltage while the first voltage is applied to the scan electrodes of the first group, And driving the voltage of the address electrode from the viadress voltage to the address voltage while the first voltage is applied to the scan electrodes of the second group. The method of claim 3, wherein The time for changing the voltage of the address electrode from the address voltage to the viadress voltage while the first voltage is applied to the scan electrodes of the first group, And changing the voltage of the address electrode from the address voltage to the viadress voltage while the first voltage is applied to the scan electrodes of the second group. The method according to any one of claims 1 to 4, And applying the first voltage to the scan electrodes of the first group and then applying the first voltage to the scan electrodes of the second group. The method according to any one of claims 1 to 4, The period of maintaining the address voltage applied to the address electrode while the first voltage is applied to the scan electrodes of the first group is the address electrode while the first voltage is applied to the scan electrodes of the second group. A method of driving a plasma display panel that is shorter than a period of maintaining the address voltage applied to the. The method according to any one of claims 1 to 4, While the first voltage is applied to the scan electrodes of the second group, the address voltage is supplied to the address electrode by turning on a first switch electrically connected between the first power supply for supplying the address voltage and the address electrode. and, While the first voltage is applied to the scan electrodes of the second group, driving of the plasma display panel to turn on a second switch electrically connected between the inductor and the second power supply to supply the address voltage to the address electrode. Way.