KR100560516B1 - Driving method and apparatus of plasma display panel - Google Patents

Abstract

The present invention removes the switching element connected to the ground voltage in the address driving circuit including a power recovery circuit, and adds only a low capacitance diode and the switching element without using a separate independent power supply switching for applying the address voltage in a bootstrap operation Drive the device. In this way, the resonance for raising and lowering the electrode voltage can be formed as one transistor, and the transistor for applying the ground voltage to the address electrode can be removed.

PDP, Address, Power Recovery, Capacitor, Pattern, Switching

Description

Driving method of plasma display device and plasma display panel {DRIVING METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

1 is a partial perspective view of an AC plasma display panel.

2 shows an electrode arrangement diagram of a plasma display panel.

3 is a schematic conceptual diagram of a plasma display device according to a first embodiment of the present invention.

4 is a diagram illustrating an address driving circuit according to a first embodiment of the present invention.

FIG. 5 is a schematic diagram of the address driving circuit of FIG. 4.

6 is a conceptual diagram of a dot on / off pattern.

7 is a conceptual diagram of a line on / off pattern.

8 is a conceptual diagram of a full white pattern.

9 is a driving timing diagram of the power recovery circuit of FIG. 5 for showing a dot on / off pattern.

10A to 10H are diagrams illustrating current paths in respective modes of the address driving circuit of FIG. 5 according to the driving timing of FIG. 9.

FIG. 11 is a driving timing diagram of the power recovery circuit of FIG. 5 for illustrating a full white pattern.

12A to 12D are diagrams illustrating current paths in respective modes of the address driving circuit of FIG. 5 according to the driving timing of FIG. 11.

13 is an address driving circuit diagram including the gate driving circuit of the switching device according to the second embodiment of the present invention.

14 is an address driving circuit diagram including the gate driving circuit of the switching device according to the third embodiment of the present invention.

The present invention relates to a driving circuit of a plasma display panel (PDP), and more particularly to an address driving circuit for applying an addressing voltage.

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the discharge space of the electrode is exposed without being insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistor for limiting the current must be inserted. On the other hand, the AC plasma display panel has a merit that the current is limited by the formation of a capacitance component because the dielectric layer covers the electrode, and the life is longer than that of the direct current type since the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, a scan electrode 4 and a sustain electrode 5 covered with a dielectric layer 2 and a protective film 3 are arranged in parallel on the glass substrate 1 (the lower side in FIG. 1). do. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are provided. The partition 9 is formed on the insulator layer 7 between the adjacent address electrodes 8 in parallel with the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The glass substrates 1 and 6 are disposed to face the discharge electrode 11 so that the address electrode 8 is orthogonal to the scan electrode 4 and the sustain electrode 5. The discharge space at the intersection of the scan electrode 4 and the sustain electrode 5 paired with the address electrode 8 forms the discharge cell 12.

2 shows an electrode arrangement diagram of a plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A _{1 to} A _m extend in the column direction and the scan electrode Y in the row direction. _{1 to} Y _n and the sustain electrodes X _{1 to} X _n extend. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, the driving method of the AC plasma display panel includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period is a wall charge on a cell (addressed cell) that is turned on to distinguish a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on the addressed cell is applied by applying a sustain discharge voltage pulse.

In the address period, since the discharge space between the surface where the address electrode is formed and the surface where the scan and sustain electrodes are formed serves as a capacitive load (hereinafter referred to as a "panel capacitor"), a capacitance component is present in the panel. Therefore, in order to apply the waveform for addressing to the address electrode, in addition to the power for address discharge, a lot of reactive power for generating a predetermined voltage in the panel capacitor is required. When the power consumption is high due to the reactive power, the load of the driving IC of the address electrode may increase to generate heat, and thus the driving IC may be destroyed. Thus, a power recovery circuit for recovering and reusing reactive power is common in the address driving IC. Used as As such a power recovery circuit, L.F. There is a circuit proposed by Weber (US Pat. Nos. 4,866,349 and 5,081,400).

The use of such a power recovery circuit can limit the power consumption to a certain level when displaying an image with a high power consumption, but the power recovery circuit is operated to increase the power consumption even when a low power consumption image is displayed. There is a problem. That is, in the display pattern in which all the discharge cells are turned on, the voltage required for addressing must be continuously applied to the address electrode. In the conventional power recovery circuit, even in this case, the power recovery operation is continued by the turn-on operation of the switching element connected to the ground voltage. There is a problem that the power consumption is increased. In addition, the conventional power recovery circuit does not change the voltage of the panel capacitor to a desired voltage due to switching loss of the transistor or parasitic components of the circuit, and thus has a problem in that power consumption is increased due to hard switching of the switching element.

In addition, a conventional power recovery circuit includes a switch for generating a resonance current for raising the voltage of the panel capacitor, a switch for generating a resonance current for decreasing the voltage of the panel capacitor, a switch for supplying an address voltage to the panel capacitor, and a panel. Since four switches for supplying the ground voltage to the capacitor and two diodes for forming the resonance path are necessary, the cost of the power recovery circuit is expensive.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an address driving circuit capable of reducing power consumption of a plasma display panel. In addition, the present invention is to reduce the cost of the address drive circuit as its technical problem.

According to an aspect of the present invention, a plasma display device includes a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode. ; A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode to which a second voltage is applied from among the plurality of second electrodes; And a first driving circuit electrically connected to the first ends of the plurality of selection circuits and applying the second voltage to a second electrode selected by the selection circuit.

The first driving circuit,

A first capacitor; A first transistor electrically connected to a first end of the selection circuit and a second end electrically connected to the first end of the capacitor; An inductor electrically connected between a first end of the selection circuit and a first end of the first transistor or between a second end of the first transistor and a first end of the first capacitor; A second transistor having a first end electrically connected to a first end of the selection circuit and a second end electrically connected to a power supply for supplying the second voltage; Connected to a control terminal of the second transistor to control an on-off operation of the second transistor, charge a voltage for driving the second transistor, and a first end is electrically connected to the first end of the second transistor A gate driving circuit comprising a second capacitor; And a switch electrically connected between the first end of the second capacitor and a third power supply for supplying a third voltage.

In this case, the second transistor is preferably an n-channel (nMOS) transistor.

In the method of driving a plasma display panel according to an aspect of the present invention, a plurality of first electrodes and a plurality of second electrodes are formed, a capacitive load is formed by the first electrode and the second electrode, and an output terminal is formed of the first electrode. An inductor electrically connected to a first end of a selection circuit electrically connected to a first electrode, and a first end electrically connected to a first end of the selection circuit to supply a first voltage to the first electrode selected by the selection circuit And a driving circuit including a first transistor configured to charge a voltage for driving the first transistor and a first terminal electrically connected to the first terminal of the first transistor. As

The driving method,

Charging an electric charge to the capacitor; Discharging a current in a first direction through the inductor to reduce a voltage of a first electrode selected by the selection circuit among the plurality of first electrodes; Reselecting a first electrode to which the first voltage is applied from the plurality of first electrodes through the selection circuit; Increasing the voltage of the selected first electrode to a current in a second direction opposite to the first direction formed through the inductor after the current in the first direction becomes 0A; And turning on the first transistor to apply the first voltage to the selected first electrode.

The current in the first direction is formed by a second transistor electrically connected to the inductor, the current in the second direction is formed by a diode formed in parallel to the second transistor, and the path in which the capacitor is charged and the first The current in two directions is separated.

The driving circuit further includes a switch electrically connected to the first end of the capacitor, and turns on the switch to charge the capacitor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

In the present invention, the expression of maintaining the voltage indicates that even if the potential difference between two specific points changes over time, the change is within an allowable range in the design or the cause of the change is due to parasitic components that are ignored in the design practice of those skilled in the art. Include cases by.

A plasma display device, a driving device and a driving method of the plasma display panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a schematic conceptual diagram of a plasma display device according to a first embodiment of the present invention.

As shown in FIG. 3, the plasma display device according to the first embodiment of the present invention includes a plasma display panel 100, an address driver 200, a scan / hold driver 300, and a controller 400. In FIG. 3, the scan and sustain driver 300 is illustrated as one block. However, the scan and sustain driver 300 is generally formed separately from the scan driver and the sustain driver.

The plasma display panel 100 includes a plurality of column address electrode extending in a direction (A ₁ ~A _m), the plurality of scan electrodes extending yirumyeonseo in pairs in the row direction (Y ₁ ~Y _n) and a plurality of sustain electrodes ( X _{1 to} X _n ). The address driver 200 applies an address signal for selecting a discharge cell to be displayed to receive the address driving control signal from the controller 400 to the address electrodes (A ₁ ~A _m). The scan / hold driver 300 receives the sustain discharge control signal from the controller 400 and alternately inputs a sustain discharge pulse to the scan electrodes Y _{1 to} Y _n and the sustain electrodes X _{1 to} X _n to discharge cells selected. Perform a maintenance discharge on. The control unit 400 receives an image signal from the outside, generates an address driving control signal and a sustain discharge control signal, and applies them to the address driver 200 and the scan / sustain driver 300, respectively.

The address driver 200, the scan / sustain driver 300, and the controller 400 are generally manufactured in the form of a printed circuit board (PCB) and mounted on a chassis base (not shown). The chassis base is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 100 so as to be coupled to the plasma display panel 100.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and a discharge cell to be discharged is selected among the plurality of discharge cells in an address period of each subfield. At this time, in order to select the discharge cells, in the address period, the scan voltage is sequentially applied to the scan electrodes, and the scan electrodes to which the scan voltage is not applied are biased with a positive voltage. An address (hereinafter referred to as an "address voltage") is applied to an address electrode passing through the discharge cell to be selected from among the plurality of discharge cells formed by the scan electrode to which the scan voltage is applied, and the address is not selected. A reference voltage is applied to the electrode. In general, the address voltage uses a positive voltage and the scan voltage uses a ground voltage or a negative voltage, so that discharge occurs at an address electrode to which the address voltage is applied and a scan electrode to which the scan voltage is applied, thereby selecting the corresponding discharge cell. And ground voltage is often used as a reference voltage.

Hereinafter, an address driving circuit included in the address driver 200 will be described with reference to FIG. 4, assuming a scan voltage applied to the selected scan electrode and a reference voltage applied to the non-selected address electrode as ground voltages.

4 is a diagram illustrating an address driving circuit according to a first embodiment of the present invention.

As shown in Fig. 4, the address driving circuit according to the first embodiment of the present invention includes a power recovery circuit 210 and a plurality of address selection circuits 220 _{1 to} 220 _m . The address selection circuits 220 _{1 to} 220 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switching elements A _H and A _L for driving and grounding, respectively. A field effect transistor having a body diode may be used as the switching elements A _H and A _L , and may be made of other switching elements having the same or similar functions. In FIG. 4, switching elements A _H and A _{L are} illustrated as n-channel MOSFETs, and body diodes are formed in the switching elements A _H and A _L from a source to a drain direction. A first terminal (drain) of the second terminal (source) to a power recovery circuit 210 is connected to the address electrodes (A ₁ ~A _m), driving the switching element (A _H) of the driving switching element (A _H) address voltage (V _a) is supplied from the power recovery circuit 210 is transmitted to the address electrodes (a ₁ ~A _m) when turned on. The ground switching element A _L has a first terminal (drain) connected to the address electrodes A ₁ -A _m , and a second terminal (source) connected to a reference voltage (ground voltage in FIG. 4). When A _L is turned on, the ground voltage is transmitted to the address electrodes A _{1 to} A _m . In principle, since the driving switching element A _H and the ground switching element A _L are not turned on at the same time, it can usually be considered as a switching switch.

As described above, both switching elements A _H and A _{L of the} address selection circuits 220 _{1 to} 220 _m respectively connected to the address electrodes A _{1 to} A _m are turned on or turned off by the control signal, thereby causing the address electrodes A to be turned off. ₁ ~A _m) an address voltage (V _a) or the ground voltage is applied to the. That is, the drive switching element (A _H) during the address period is turned on and the addressing voltage (V _a) is applied to the address electrode is selected and the ground switching element (A _L) is turned on, the ground voltage is applied to the address electrode is selected (Not selected).

The power recovery circuit 210 includes a switching element A _a , A _erc , an inductor L, a diode D _g , and a capacitor C ₁ , C ₂ . The switching elements A _a and A _erc may be made of a field effect transistor having a body diode, or may be made of other switching elements having the same or similar functions. In FIG. 4, the switching elements A _a and A _{erc are} illustrated as n-channel MOSFETs, and the body diodes are formed in the switching elements A _a and A _erc in the direction from the source to the drain, respectively. The first terminal (drain) of the switching element A _a is connected to a power supply (or a power supply line) V _a for supplying the address voltage V _a , and the second terminal (source) is an address select circuit 220 _1- . 220 _m ) is connected to the first terminal of the drive switching element A _H. Also it can be connected to a diode (D _a) in the same direction of the body diode is formed on the switching element (A _a) between the power supply (V _a) and the address selecting circuit.

The first terminal of the inductor L is connected to the first terminal of the driving switching element A _H of the address selection circuit 220 _{1 to} 220 _m , and the first terminal (drain) of the switching element A _erc is It is connected to the second terminal of (L). The contact of the capacitor (C _1, C ₂₎ is the power (V _a) and are connected in series to between a ground voltage, a second terminal (source) of the capacitor (C _1, C ₂₎ of the switching device (A _erc) It is connected. At this time, the connection order between the inductor L and the switching element A _erc may be changed. The diode D _g has a cathode connected to the first terminal of the driving switching element A _H of the address selection circuit 220 _{1 to} 220 _m , and an anode connected to the ground voltage.

Although Figure 4 shows that as one of the power recovery circuit 210 connected to the address selection circuit (220 ₁ ~220 _m), address selection circuit for each group by dividing the (220 ₁ ~220 _m) into groups The power recovery circuit 210 may be connected. In the Figure 4 but in series connection between the capacitors (C _1, C ₂₎ a power supply for supplying an address voltage (V _a) (V _a) and the ground voltage, it is also possible to remove the capacitor (C _1).

Next, the operation of the address driving circuit according to the first embodiment of the present invention will be described with reference to FIGS. 5 to 12D. 5 to 12D, in order to distinguish the direction of the current flowing through the inductor L, the direction of the current flowing from the first terminal to the second terminal of the inductor L is defined as "positive direction" and the inductor L The direction of the current flowing from the second terminal to the first terminal is defined as "negative direction". In addition, since the threshold voltage of the semiconductor element (switching element, diode) is very low compared to the discharge voltage below, the threshold voltage is regarded as 0V and approximated.

FIG. 5 is a schematic diagram of the address driving circuit of FIG. 4.

In FIG. 5, only two adjacent address selection circuits 220 _2i-1 and 220 _2i are illustrated for convenience of description, and capacitive components formed by the address electrode and the scan electrode are illustrated as panel capacitors C _p1 and C _p2 . . As described above, the ground voltage is applied to the scan electrode side of the panel capacitor.

5, the power recovery circuit 210 is connected to the panel capacitors C _p1 and C _p2 through the driving switching elements A _H1 and A _H2 of the address selection circuits 220 _2i-1 and 220 _2i . The ground switching elements A _L1 and A _{L2 of the} address selection circuits 220 _2i-1 and 220 _2i are connected to a ground voltage. The panel capacitor C _p1 is a capacitive component formed by the address electrode A _2i-1 and the scan electrode, and the panel capacitor C _p2 is a capacitive component formed by the address electrode A _2i and the scan electrode. to be.

In the following, the relationship between the contrast (on / off) pattern displayed on the screen and the address signal waveform in one subfield will be described along with the operation of the address driving circuit by taking the representative pattern shown in FIGS. 6 to 8 as an example. Such representative patterns include a dot on / off pattern, a line on / off pattern, and an address selection circuit, in which the switching state of the address selection circuits 220 _{1 to} 220 _m is large. there is a full white pattern without a change of the switching state (full white pattern) of the (220 ₁ ~220 _m).

6 to 8 are conceptual views of a dot on / off pattern, a line on / off pattern, and a full white pattern, respectively.

This pattern is determined by the switching of the address selection circuits 220 _{1 to} 220 _m , and the driving timings of the switching elements A _a and A _erc of the power recovery circuit 210 are the same even when implementing any pattern. The change in the switching state of the address selection circuit means that the turn-on / turn-off operations of both switching elements A _H and A _L of the address selection circuit are repeated when the scan electrodes are sequentially selected. That is, when the scan electrodes are sequentially selected, when the address voltage and the ground voltage are alternately applied to the address electrodes, a large change in the switching state of the address selection circuit occurs.

First, the dot on / off pattern shown in FIG. 6 sequentially processes the odd-numbered address electrodes A ₁ and A ₃ and the even-numbered address electrodes when the scan electrodes Y ₁ , Y ₂ , Y ₃ , and Y ₄ are sequentially selected. A ₂ and A ₄ ) are light and dark display patterns generated by alternately applying an address voltage. For example, when the first scan electrode Y ₁ is selected, an address voltage is applied only to the odd address electrodes A ₁ and A ₃ so that the odd column of the first row is selected, and the second scan electrode Y ₂ is selected. ) Is selected, the address voltage is applied only to the even-numbered address electrodes A ₂ and A ₄ so that light emission is selected in the even-numbered column of the second row. That is, when the scan electrode Y ₁ is selected, all of the driving switching elements A _{H of the} odd-numbered address selection circuit are turned on and all of the ground switching elements A _L of the even-numbered address selection circuit are turned on. When (Y ₂ ) is selected, the driving switching element A _H of the even-numbered address selection circuit is turned on and the ground switching element A _L of the odd-numbered address selection circuit is turned on.

Next, in the line on / off pattern shown in FIG. 7, when the first scan electrode Y ₁ is selected, address voltages are applied to all the address electrodes A _{1 to} A ₄ , but the second scan electrode Y ₂ is selected. Is a display pattern obtained by repeating a display mode in which no address voltage is applied to all the address electrodes A _{1 to} A ₄ . That is, the scan electrodes (Y ₁₎ all of the driving switching element (A _H) of the address selecting circuit is turned on, the scan electrode (Y ₂₎ All ground switching of the address selecting circuit elements (A _L), when this is driven when the driven Is turned on.

8 is a display pattern generated by continuously applying address voltages to all address electrodes when the scan electrodes are sequentially selected. That is, the drive switching elements A _H of all the address selection circuits are always turned on.

As described above, the ground switching element A _L of the address selection circuit is periodically turned on in the dot on / off pattern and the line on / off pattern, but the ground switching element A _L is not turned on in the full white pattern. The voltage of the capacitor C ₂ in the power recovery circuit of FIG. 5 varies depending on whether the ground switching element A _L is turned on.

In the following, since the dot on / off pattern and the line on / off pattern operate similarly in that the ground switching element A _L is periodically turned on, the dot on / off pattern and the full white pattern are illustrated as examples of the address of FIG. 5. The operation of the driving circuit will be described in detail.

1. Dot on / off pattern-see FIGS. 9, 10A-10H

First, referring to the dot on / off pattern, FIGS. 9 and 10A to 10H will be described with respect to time-series operation changes of the address driving circuit in the case where a pattern with a large number of switching changes of the address selection circuits 220 _{1 to} 220 _m is displayed. It demonstrates with reference. Here, the operation change is performed in eight modes M1 to M8, and the mode change is caused by the operation of the switching element. Here, the phenomenon called resonance is not a continuous oscillation but a change in voltage and current due to the combination of the inductor L and the panel capacitors C _p1 and / or C _p2 generated when the switching element A _erc is turned on. .

9 is a driving timing diagram of the power recovery circuit of FIG. 5 for showing a dot on / off pattern. 10A to 10H are diagrams illustrating current paths in respective modes of the address driving circuit of FIG. 5 according to the driving timing of FIG. 9.

In the case of displaying the dot on / off pattern in the circuit of FIG. 5, the driving switching element of the address selection circuit 220 _2i-1 connected to the odd-numbered address electrode A _2i-1 when one scan electrode is selected. The ground switching element A _L2 of the address selection circuit 220 _2i connected to (A _H1 ) and the even-numbered address electrode A _2i is turned on, and the address and the driving switching element A _H2 of the address selection circuit 220 _2i are turned on. The ground switching element A _L1 of the selection circuit 220 _2i-1 is turned off. When the next scan electrode is selected, the driving switching element A _H1 and the ground switching element A _L2 are turned off, and the driving switching element A _H2 and the ground switching element A _L1 are turned on. This operation is repeated. When the dot on / off pattern is displayed in this manner, the driving switching elements A _{H1 of} the address selection circuits 220 _2i-1 and 220 _2i in synchronization with the scan voltages sequentially applied to the scan electrodes Y _{1 to} Y _n . , A _H2 ) and the turn-on / turn-off operation of the ground switching elements A _L1 and A _L2 are continuously repeated.

In FIG. 9, the switching elements A _H1 , A _L2 and A _a are turned on and the switching elements A _H2 and A _L1 are turned off before the mode 1 M1 starts, so that the panel capacitor C _p1 has _a voltage of V _a. It is assumed that the voltage is applied and the 0V voltage is applied to the panel capacitor C _p2 . That is, it is assumed that the voltage V _a is applied to the odd _- numbered address electrode A _2i-1 and the voltage 0 V is applied to the even-numbered address electrode A _2i .

First, in mode 1 M1, the switching elements A _erc are turned on (the channel is turned on) while the switching elements A _H1 , A _L2 and A _a are turned on and the switching elements A _H2 and A _L1 are turned off. )do. The power source (V _a), the switching device _{(A a),} the inductor (L), the switching device (A _erc) and a capacitor inductor (L) and the capacitor through the path (C ₂₎ (C ₂ as shown in Figure 10a Current is injected into the capacitor C ₂ to charge the voltage. Here, the current I _L flowing in the inductor L increases linearly with a slope of (V _a -V ₂ ) / L. _A voltage V _a is applied to the panel capacitor C _p1 and _a voltage of 0 V is applied to the panel capacitor C _p2 .

In mode 2 (M2), the switching element A _a is turned off so that the panel capacitor C _p1 , the body diode of the driving switching element A _H1 , the inductor L, the switching element A _erc , and the like as shown in FIG. 10B. The resonance path ① is formed by the capacitor C ₂ . As shown in FIG. 9, the resonance current I _L is formed as a sine wave in the resonance path, and the panel capacitor C _p1 is discharged by the resonance current I _{L in} the positive direction, thereby decreasing the panel capacitor C _p1. Decreases the voltage V _p1 . And a resonant current discharged from the panel capacitor (C _p1) is supplied to the capacitor (C ₂₎ and a voltage is charged in the capacitor (C _2). At this time, since the ground switching element A _L2 is turned on, the voltage V _p2 of the panel capacitor C _p2 is continuously maintained at a voltage of 0V. And the panel capacitor (C _p1) panel by a voltage (V _p1) is a ground switching element is smaller than the 0V voltage of the panel capacitor (C _p1) connected to the diode (D _g) associated with the body diode, or a ground voltage (A _L1) of The voltage V _p1 of the capacitor C _p1 does not decrease below the 0 V voltage.

Here, when the resonant current becomes 0A, the voltage of the voltage of the panel capacitor C _p1 V _p1 varies depending on the voltage V ₂ of the capacitor C ₂ . Voltage of the capacitor (C ₂₎ of the voltage (V ₂₎ does not decrease until the voltage (V _p1) is 0V voltage is high when the amount of resonance current only by the panel capacitor (C _p1) in the direction of, the capacitors (C ₂₎ When (V ₂ ) is low, the voltage V _p1 of the panel capacitor C _p1 may decrease to a voltage of 0 V while the positive current flows in the positive direction. If the resonant current I _L in the positive direction remains after the voltage V _p1 of the panel capacitor C _p1 becomes 0 V, the residual current I _L is a diode D _g , an inductor. (L), is recovered as a switching device (a _erc) and capacitor (C ₂₎ via a line (②) of the capacitor (C _2). And the panel capacitor (C _p1) voltage (V _p1) in this case has not decreased to the voltage 0V to panel capacitor (C _p1) the residual voltage is to be turned on and the ground switching element (A _L1) in the mode 3 (M3) under the When discharged.

Next, mode 3 (M3) in the switching element so as not to select the address electrode (A _2i), and select the address electrode _{(A 2i-1) (A} H1, A L2) is turned off and the switching element (A _H2, A _L1 ) is turned on. The 0V voltage is applied to the panel capacitor C _p1 by the turned-on switching element A _L1 . At this time, when the front of the voltage (V _p1) of a panel capacitor (C _p1) greater than the voltage 0V as described there are discharged the residual voltage of the panel capacitor (C _p1) via a grounding switching device (A _L1). When the resonant current I _L becomes 0A in the mode 2 (M2), the resonant current flows again in the negative direction through the body diode of the switching element A _erc by the principle of resonance. That is, as shown in FIG. 10C, a resonance path is formed by the capacitor C ₂ , the body diode of the switching element A _erc , the inductor L, the driving switching element A _H2 , and the panel capacitor C _p2 . The panel capacitor C _p2 is charged by the resonant current I _{L in} the negative direction to increase the voltage V _p2 of the panel capacitor C _p2 . Herein, the panel capacitor (C _p2) voltage (V the voltage (V _p2) is V automatically switching element (A _a) a body diode or a diode (D _a) a conduction because the panel capacitor (C _p2) in _a higher than the voltage at the _p2 ) does not exceed the voltage V _a .

In mode 4 M4, the switching element A _a is turned on (channel is turned on), the switching element A _erc is turned off, and _a voltage V _a is applied to the panel capacitor C _p2 as shown in FIG. 10D. After the panel capacitor C _p2 becomes the voltage V _a , the current I _L remaining in the inductor L is the capacitor C ₂ , the body diode of the switching element A _erc , the inductor L and the switching element. It is recovered to the power supply V _a through the body diode or diode D _a of (A _a ).

And the voltage of the modes 3 and 4 (M3, M4) the panel capacitor (C _p1) current, so the capacitor (C ₂₎ being discharged at a current which is recovered in the resonance current and the power supply (V _a) to be filled has a capacitor (C ₂₎ in in This decreases.

As described above, the power recovery circuit 210 applies the voltage V _a to the address electrode A _2i through the driving switching element A _H2 of the address selection circuit 220 _2i through the modes 1 to 4 (M1 to M4). . The 0V voltage is applied to the address electrode A _2i-1 through the ground switching element A _L1 of the address selection circuit 220 _2i-1 .

Next, in mode 5 (M5) to mode 8 (M8), only the switching element operation of the address selection circuit is changed and the switching element operation of the power recovery circuit is the same.

In the mode 5 M5, the switching elements A _H2 , A _L1 and A _a are turned on and the switching elements A _erc are turned on (the channel is turned on) while the switching elements A _H1 and A _L2 are turned off. . The power source as shown in Fig. 10e (V _a), the switching device _{(A a),} the inductor (L), the switching device (A _erc) and a capacitor inductor (L ₂₎ and the capacitor through the path (C ₂₎ (C _The current is injected into ₂ ) to charge the capacitor C ₂ . Here, the current I _L flowing in the inductor L increases linearly with a slope of (V _a -V ₂ ) / L. And the panel capacitor (C _p1) is applied with a voltage of about 0V, and the panel capacitor (C _p2), there is applied _a voltage V.

In mode 6 (M6), the switching element A _a is turned off so that the panel capacitor C _p2 , the body diode of the driving switching element A _H2 , the inductor L, the switching element A _erc , and the like as shown in FIG. 10F. The resonance path ① is formed by the capacitor C ₂ . The panel capacitor C _p2 is discharged by the resonant current I _L in the positive direction in this resonance path, and the voltage V _p2 decreases. And a resonant current discharged from the panel capacitor (C _p2) is supplied to the capacitor (C ₂₎ and a voltage is charged in the capacitor (C _2). At this time, since the ground switching element A _L1 is turned on, the voltage V _p1 of the panel capacitor C _p1 is continuously maintained at a voltage of 0V. The voltage V _p2 of the panel capacitor C _p2 does not decrease below 0 V by the body diode of the ground switching element A _L2 to which the panel capacitor C _p2 is connected or the diode D _g connected to the ground voltage. Do not.

In the mode 6 (M6), as described in the mode 2 (M2), the voltage of the panel capacitor C _p2 (V _p2 ) varies when the resonant current becomes 0A depending on the voltage V ₂ of the capacitor C ₂ . . If the resonant current I _L in the positive direction remains after the voltage V _p2 of the panel capacitor C _p2 becomes 0 V, the residual current I _L is _{equal to the} diode D _g and the inductor L. ) Is recovered to the capacitor C ₂ through the path ② of the switching element A _erc and the capacitor C ₂ . And the panel capacitor (C _p2) voltage (V _p2) in this case has not decreased to the voltage 0V to panel capacitor (C _p2) the residual voltage will have to be turned on, grounding switching device (A _L2) in the mode 7 (M7) of the bottom of the When discharged.

Next, in the mode 7 M7, the switching elements A _H2 and A _L1 are turned off and the switching elements A _H1 and A are selected so as to select the address electrode A _2i-1 and not select the address electrode A _2i . _L2 ) is turned on. A 0 V voltage is applied to the panel capacitor C _p2 by the turned-on switching element A _L2 . At this time, not less than the voltage of about 0V voltage (V _p2) of the panel capacitor (C _p2) there are discharged the residual voltage of the panel capacitor (C _p2) via a grounding switching device (A _L2). As described in the mode 3 (M3), a resonance path is formed by the capacitor C ₂ , the body diode of the switching element A _erc , the inductor L, the driving switching element A _H2 , and the panel capacitor C _p1 . . A current is supplied from the capacitor C ₂ to the panel capacitor C _p1 to the current in the negative direction in this resonance path, so that the voltage V _p1 of the panel capacitor C _p1 increases. Herein, the panel capacitor (C _p2) voltage (V the voltage (V _p2) is V automatically switching element (A _a) a body diode or a diode (D _a) a conduction because the panel capacitor (C _p2) in _a higher than the voltage at the _p2 ) does not exceed the voltage V _a .

In mode 8 M8, the switching element A _a is turned on (channel is turned on), the switching element A _erc is turned off, and _a voltage V _a is applied to the panel capacitor C _p1 as shown in FIG. 10H. After the panel capacitor C _p1 becomes V _a , the current remaining in the inductor L is the capacitor C ₂ , the body diode of the switching element A _er c, the inductor L and the switching element A _a . It is recovered to the power supply (V _a ) through the body diode or diode (D _a ) of.

Mode 7 and 8 (M7, M8) in the current collected by the resonance current and the power supply (V _a) to be charged in the panel capacitor (C _p1) is a current that is discharged from the capacitor (C ₂₎ so that the voltage of the capacitor (C ₂₎ Decreases.

Thus, through the Mode 5 to 8 (M5~M8) energy recovery circuit 210 to the address electrode (A _2i-1) through the driving switching element (A _H1) of the address selecting circuit (220 _2i-1) V _a Apply voltage. The 0V voltage is applied to the address electrode A _2i through the ground switching element A _L2 of the address selection circuit 220 _2i . As the operations of the modes 1 to 8 (M1 to M8) are repeated, a dot on / off pattern is realized.

Here, a description will be given of the movement of the stored energy of the capacitor C ₂ . First, in mode 1 (M1), current (energy) is supplied to capacitor (C ₂ ) through inductor (L ₂ ) in power supply (V _a ), and panel capacitor (C _p1 ) is discharged in mode (M2). As a result, current (energy) is supplied to the capacitor C ₂ . That is, mode 1 and 2 (M1, M2) is the energy in the capacitor (C ₂₎ charging voltage is increased by ΔV1 of the capacitor (C _2). Next, in mode 3 (M3), a current is supplied from the capacitor C ₂ through the inductor L to increase the voltage of the panel capacitor C _p2 , and the remaining current is recovered to the power source V _a to circulate energy. . That is, in the mode 3 (M3) is the energy discharged from the capacitor (C ₂₎ the voltage of the capacitor (C ₂₎ is lowered by ΔV2. However, assuming that the capacitor C ₂ is initially charged with a voltage of V _a / 2, the capacitor C ₂ supplies more energy through the power supply V _a in mode 1 (M1) when the capacitor C ₂ is charged. the charge energy of the (C ₂₎ is greater than the discharge energy of the capacitor (C _2). That is, ΔV1 is greater than ΔV2. The energy charged and discharged to the capacitor C ₂ in the modes 5 to 8 (M5 to M8) is also the same as in the modes 1 to 4 (M1 to M4). Since the panel capacitor C _p1 or C _p2 is charged again in modes 3 or 7 (M3 and M7) after it becomes 0 V, the panel capacitor C _p1 or C is repeated even if the modes 1 to 8 (M1 to M8) are repeated. The energy discharged in capacitor C ₂ to charge _{p 2} ) is substantially constant.

However, the capacitor from when the increasing voltage of the capacitor (C ₂₎ charging energy is large capacitor (C ₂₎ than the discharge energy of the mode 1 and 2 (M1, M2) or modes 5 and 6 (M5, M6) (C 2 Decreases the energy charged in That is, when the operations of the modes 1 to 8 (M1 to M8) are repeated repeatedly, the charging energy of the capacitor C ₂ is decreased, and finally, the charging energy and the discharge energy of the capacitor C ₂ are substantially the same. It is in equilibrium. In equilibrium, the voltage charged in the capacitor C ₂ is greater than the voltage V _a / 2 and smaller than the voltage V _a .

Thus the capacitor to the panel capacitor (C _p1, C _p2) by the principle of resonance in the capacitor is a voltage charged in the (C ₂₎ is greater than V _a / 2 voltage, mode 3, and 7 (M3, M7) (C 2) A voltage corresponding to twice the voltage of, i.e., _a voltage greater than the voltage V _a may be charged. Therefore, even when a parasitic component is present in the address driving circuit, the voltage of the panel capacitors C _p1 and C _p2 may increase to the voltage V _a by resonance, so that the zero voltage switching of the switching element A _a is achieved. Therefore, switching loss can be reduced.

2. Full White Pattern-see FIGS. 11, 12A-12D

Next, referring to FIGS. 11 and 12A to 12D, the time-series operation change of the address driving circuit in the case of displaying a pattern in which the switching change of the address selection circuits 220 _{1 to} 220 _m is small is taken as an example. Explain. Here, the operation change is sequential in four modes M1 to M4, and the mode change is caused by the operation of the switching element.

FIG. 11 is a driving timing diagram of the power recovery circuit of FIG. 5 for illustrating a full white pattern. 12A to 12D are diagrams illustrating current paths in respective modes of the address driving circuit of FIG. 5 according to the driving timing of FIG. 11.

In the case of displaying the full white pattern in the circuit of FIG. 5, the driving switching elements A _H1 and A _H2 of the address selection circuits 220 _2i-1 and 220 _2i are always turned on while the scan electrodes are sequentially selected. .

In FIG. 11, it is assumed that the switching elements A _H1 , A _H2 , and A _a are turned on before the mode 1 M1 starts, so that _a voltage V _a is applied to the panel capacitors C _p1 and C _p2 .

First, in the mode 1 M1, the switching element A _erc is turned on (channel is turned on) while the switching elements A _H1 , A _H2 and A _a are turned on. Then, as shown in FIG. 12A, as in the mode 1 M1 of FIG. 9, the current I _L flowing in the inductor L increases linearly with a slope of (V _a -V ₂ ) / L, and thus the capacitor a (C ₂₎ current is injected and a voltage is charged in the capacitor (C _2). In addition, _a voltage V _a is applied to the panel capacitors C _p1 and C _p2 .

In mode 2 (M2), switching element A _a is turned off, and as shown in FIG. 12B, panel capacitors C _p1 and C _p2 , body diodes of driving switching elements A _H1 and A _H2 , and inductor L The resonance path is formed by the switching element A _erc and the capacitor C ₂ . Due to the positive resonance current I _L in this resonance path, the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 decrease, and the capacitor C as shown in the mode 2 (M2) of FIG. 9. ₂ ) the voltage is charged. As described in Mode 2 (M2) of FIG. 9, when the voltage of the capacitor C ₂ is low, the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 are reduced to a voltage of 0 V so that the remaining current becomes a capacitor. May be recovered as (C ₂ ). However, in the case of the full white pattern, the voltage V ₂ of the capacitor C ₂ is increased so that the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 are increased to 0 V due to the positive resonant current. It does not decrease. This will be described in detail below.

In the full white pattern, since the address electrodes A _2i-1 and A _2i are continuously selected when the scan voltages are sequentially applied to the scan electrodes Y _{1 to} Y _n , the driving switching elements A _H1 and A _H2 continue to be selected. It is turned on. Therefore, in the mode 3 (M3), unlike the dot on / off pattern, there is no switching between the driving switching elements A _H1 and A _H2 and the ground switching elements A _L1 and A _L2 , and thus the panel capacitors C _p1 and C _p2. ) Residual voltage is not discharged. After the resonance current I _L becomes 0A in the mode 2 (M2), the mode changes to the negative direction in the direction of the resonance current I _L in the mode 3 (M3). Therefore, as shown in FIG. 12C, the resonance currents to the capacitor C ₂ , the body diode of the switching element A _erc , the inductor L, the switching elements A _H1 and A _H2 , and the panel capacitors C _p1 and C _p2 ( I _L ) increases the voltages V _p1 and V _p2 of the panel capacitors C _p1 and C _p2 and discharges the capacitor C ₂ . Herein, the panel capacitor (C _p2) voltage (V the voltage (V _p2) is V automatically switching element (A _a) a body diode or a diode (D _a) a conduction because the panel capacitor (C _p2) in _a higher than the voltage at the _p2 ) does not exceed the voltage V _a .

Next, in mode 4 (M4), switching element A _a is turned on (channel is turned on) and switching element A _erc is turned off so that the voltage V _{a is} applied to panel capacitors C _p1 and C _p2 as shown in FIG. 12D. Is approved. After the panel capacitors C _p1 and C _p2 become the voltage V _a , the current I _L remaining in the inductor _L is the capacitor C ₂ , the body diode of the switching element A _erc , and the inductor L. And the power source V _a through the body diode or diode D _a of the switching element A _a .

As described above, the power recovery circuit 210 through the modes 1 to 4 (M1 to M4) is configured to perform the address electrodes A _2i through the driving switching elements A _H1 and A _H2 of the address selection circuits 220 _2i-1 and 220 _2i . Supply the voltage V _a to _-1 , A _2i ). When the full white pattern of FIG. 8 is displayed, the modes 1 to 4 (M1 to M4) are repeated while the switching elements A _H1 and A _H2 are continuously turned on.

In the full white pattern of FIG. 8, as described in the dot on / off pattern, the voltage V ₂ of the capacitor C ₂ increases by repetition of the modes 1 to 4 (M1 to M4). Here, when the voltage V ₂ of the capacitor C ₂ is high so that the panel capacitors C _p1 and C _p2 do not decrease to a voltage of 0 V, the ground switching element A of the address selection circuits 220 _2i-1 and 220 _2i . _{Since L1} and A _L2 are not turned on, the residual voltages of the panel capacitors C _p1 and C _p2 are not discharged. Therefore, mode 2 the panel capacitor through the _{(M2) (C p1, C} p2) is filled again via the after the discharge, the mode 3 while the residual voltage is not discharging the panel capacitor _{(C p1, C p2) (} M3) do. At this time, assuming that 100% of the energy is recovered and used, the energy charging the capacitor C ₂ in the mode 2 (M2) and the energy discharged from the capacitor C ₂ in the mode 3 (M3) become substantially the same. However, the capacitor is supplied a current to the (C ₂₎ to the capacitor is further carried out the process of the mode 1 (M1) to charge (C _2), when displaying the full white pattern of Figure 9 is to be charged to the capacitor (C ₂₎ The voltage ΔV1 is always greater than the voltage ΔV2 discharged from the capacitor C ₂ .

When the voltage of the capacitor (C ₂₎ of the process, when the voltage (ΔV1) to be charged is larger than the voltage (ΔV2) is discharged from the capacitor (C _2), Mode 1 to 4 (M1~M4) repeated in the capacitor (C ₂₎ Will increase. Then, when the voltage of the capacitor (C ₂ ) increases, the current discharged from the panel capacitors (C _p1 , C _p2 ) to the capacitor (C ₂ ) in the mode 2 (M2) decreases, thereby discharging the panel capacitors (C _p1 , C _p2 ). The amount is reduced. That is, as shown in FIG. 11, when the processes of the modes 1 to 4 (M1 to M4) are repeated, the amount of the voltages V _p1 and V _{p2 of} the panel capacitors C _p1 and C _p2 decreases.

And since the voltage (V _p1, V _p2) of when the voltage of the capacitor (C ₂₎ increasing haejimyeon substantially equal to V _a voltage, a panel capacitor (C _p1, C _p2) equal to the voltage of the capacitor (C ₂₎ In the mode 2 (M2), the panel capacitors C _p1 and C _p2 do not discharge. And the mode 2 (M2) the panel capacitor (C _p1, C _p2) voltage (V _p1, V _p2) is not reduced mode 3 the panel capacitor (C _p1, C _p2) in (M3) in the not charged. As such, when the voltage of the capacitor C ₂ increases to the voltage V _a , substantially no current moves in the modes 2 and 3 (M2 and M3). That is, when the full white pattern is displayed, the power recovery circuit 210 does not substantially operate.

As described above, in the power recovery circuit according to the first embodiment of the present invention, the voltage level of the capacitor C ₂ is automatically changed by the switching operation of the address selection circuit so that the operation of the power recovery circuit is set. At this time, the voltage of the capacitor (C ₂₎ is determined by the energy discharged from the energy charged in the capacitor (C ₂₎ and a capacitor (C _2). And a capacitor (C ₂₎ charging energy is composed of a discharge energy of the energy to the panel capacitor is supplied through the inductor from the electrical discharge energy of the capacitor (C ₂₎ is made on a charge energy of the panel capacitor, the capacitor (C ₂₎ half of the address voltage (V _a / 2) If the terminal voltage of the level, the charge energy of the capacitor (C ₂₎ is greater than the discharge energy of the capacitor (C _2).

However, in the case of the dot on / off pattern, since the panel capacitor charged up to the address voltage is completely discharged to the ground voltage by turning on the switching element A _L of the address selection circuit, the panel capacitor is charged again to the address voltage, so that the operation is repeated. Even if the discharge energy of the capacitor C ₂ , which is the charge energy of the panel capacitor, is almost constant. On the other hand, a capacitor (C ₂₎ substantially V _a / 2 the voltage in the charge capacitor (C ₂₎ increasing the voltage of the capacitor (C ₂₎ charging energy is larger than the discharge energy, and of this capacitor (C ₂ in accordance with the Decreases the charging energy. Therefore, if the operation is repeated by reducing the charge energy of the capacitor (C ₂₎ be an equilibrium state becomes substantially the same as the discharge energy of the capacitor (C ₂₎ is made as the power recovery operation.

That is, address selection circuit (220 ₁ ~200 _m) select an address change many of the switching state of the circuit panel to be filled after being completely discharged from a plurality of panel capacitors connected to the (220 ₁ ~200 _m) to the ground voltage to the address voltage If there are many capacitors, the capacitor C ₂ is charged to _a voltage between the voltage V _a / 2 to the voltage V _a to perform a power recovery operation.

In the case of the full white pattern, the ground switching element A _L connected to the panel capacitor charged to the address voltage is not turned on. However, the capacitor does (C ₂₎ becomes larger than a V _a / 2 voltage the voltage of the charging energy is large capacitor (C ₂₎ than the discharge energy, the voltage of the panel capacitor by the resonance of the inductor and the panel capacitor is not discharged until a ground voltage . Since the ground switching element A _L connected to the panel capacitor charged to the address voltage is not turned on, the panel capacitor generates a residual voltage. Due to this residual voltage, the charging energy of the panel capacitor and the discharge energy of the panel capacitor are equally reduced, and accordingly, the voltage of the capacitor C ₂ continues to increase. As the voltage of the capacitor C ₂ increases, the residual voltage of the panel capacitor also increases, so that there is almost no energy charged and discharged in the panel capacitor, so that little energy is consumed in the power recovery circuit.

The power recovery operation is hardly performed like the full white pattern even in a pattern in which only one color is displayed on all screens or a pattern in which address voltage is continuously applied only to a certain amount of address electrodes.

As described above, in the first embodiment of the present invention, the power recovery operation is performed in the pattern requiring the power recovery operation due to the large number of switching variations of the address selection circuit, and the power recovery operation in the pattern in which the power recovery operation is not necessary because there is little switching change of the address selection circuit. Does not automatically. In addition, in the first embodiment of the present invention, since the level of the voltage applied to the address electrode is changed only by the resonance current generated by the turn-on of the switching element A _erc , the scan electrode is applied to the address electrode when the scan electrodes are sequentially selected. Voltage change is faster. In other words, high-speed addressing with a rapid cycle of the pulse applied to the address electrode can be achieved.

13 illustrates an address driving circuit including a gate driving circuit of the switching element A _a according to the second embodiment of the present invention.

As shown in Figure 13, the gate driving circuit of the switching device (A _a) according to the second embodiment of the present invention comprises a bootstrap capacitor (C _boot), a voltage charged in the bootstrap capacitor (C _boot) The on / off of the switching element A _a is controlled by using. However, in the first embodiment of the present invention, the switching element for supplying the ground voltage is removed in the conventional address power recovery circuit, and the ground voltage is applied to the address electrode through the switching element _Aerc . Therefore, in order to charge the bootstrap capacitor (C _boot) by connecting the switching elements (Q _d) connected to the ground voltage to one bootstrap capacitor (C _boot) and haejueoya form the charging path. In this case, since the switching element Q _d is for forming a path for charging only a voltage for driving the gate of the switching element A _a , a small switching element may be used.

However, as shown in FIG. 13, when the switching element Q _d is turned on to connect the small capacitance switching element Q _d and charge the bootstrap capacitor C _boot , the capacitor C ₂ -the switching element A _erc- A current path of the inductor L-switching element Q _d is formed and a voltage charged in the capacitor C ₂ is discharged through this current path, which causes a power recovery operation to be unstable. Therefore, to solve this disadvantage, a separate floating power source for driving the gate of the switching element A _a without the bootstrap capacitor C _boot and the switching element Q _d must be used. However, when a separate floating power supply is used, a manufacturing cost increases because a separate DC-DC converter and an address buffer must be mounted.

Therefore, the third embodiment of the present invention provides a circuit capable of performing a stable power recovery operation while driving the gate of the switching element (A _a ) by using a bootstrap capacitor (C _boot ).

FIG. 14 shows an address driving circuit including the gate driving circuit of the switching element A _a according to the third embodiment of the present invention.

As shown in FIG. 14, the gate driving circuit of the switching element A _a according to the third embodiment of the present invention includes a small switching element having one end connected to a ground terminal to charge a bootstrap capacitor C _boot . connecting a Q _d) to one end of the bootstrap capacitor (C _boot) and connects the contacts of the switching device (Q _d) and a bootstrap capacitor (C _boot) to the source of the switching element _{(a a).} In addition, when the bootstrap capacitor C _boot is charged, a current on a current path connected to the switching element A _erc and the switching element Q _d to prevent the charged voltage from flowing into the capacitor C ₂ . Connect the diode (D _b ) in the direction of suppressing the flow of.

According to the third exemplary embodiment of the present invention, when the switching element A _a and the switching element A _erc are turned off in sections other than the address period, the switching element Q _d is turned on so that the switching element A _a is turned on. The driving voltage is charged to the bootstrap capacitor (C _boot ).

In the address period, when the switching element A _a is turned on by the voltage charged in the bootstrap capacitor C _boot , the address voltage V _{a is} applied to the address electrode through the path of the switching element A _a -diode D _b . ) Is applied. At this time, the diode (D _b) to a voltage drop may occur by, but an address voltage (V _a) at this time is applied to the flowing current is in size compared to the current that flows when discharge is a voltage charged in the capacitor (C ₂₎ so Since the voltage drop by the diode D _b is small, it can be ignored.

In addition, in the third embodiment of the present invention, the current remaining in the inductor L when the voltage V _p of the panel capacitor C _p exceeds the voltage V _a and after the panel capacitor C _p1 becomes the voltage V _a. When recovering, the voltage V _p of the panel capacitor C _p is clamped to the voltage V _a through the diode D _a , and the residual current is recovered to the power supply V _a .

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, since the ground voltage is not applied in the power recovery circuit of the address driving circuit, the switching element connected to the ground voltage can be removed, and only a low capacity diode and the switching element are added without using a separate independent power supply. Therefore, the switching element for applying the address voltage can be driven by the bootstrap operation, thereby reducing the manufacturing cost.

Claims (15)

A panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode; A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode to which a second voltage is applied from among the plurality of second electrodes; And A first driving circuit electrically connected to a first end of the plurality of selection circuits and applying the second voltage to a second electrode selected by the selection circuit, The first driving circuit, A first capacitor; A first transistor electrically connected to a first end of the selection circuit and a second end electrically connected to the first end of the capacitor; An inductor electrically connected between a first end of the selection circuit and a first end of the first transistor or between a second end of the first transistor and a first end of the first capacitor; A second transistor having a first end electrically connected to a first end of the selection circuit and a second end electrically connected to a power supply for supplying the second voltage; Connected to a control terminal of the second transistor to control an on-off operation of the second transistor, charge a voltage for driving the second transistor, and a first end is electrically connected to the first end of the second transistor A gate driving circuit comprising a second capacitor; And A switch electrically connected between the first end of the second capacitor and a third power supply for supplying a third voltage Plasma display device comprising a. The method of claim 1, The first driving circuit, A first diode in which an anode is electrically connected to the first end of the second capacitor and a cathode is electrically connected to the first end of the plurality of selection circuits. Plasma display device further comprising. The method of claim 1, In the first transistor, a body diode corresponding to a cathode and an anode is formed at a first end and a second end, respectively. The first driving circuit reduces the voltage of the second electrode with a first current in a first direction formed of the second electrode, the first transistor, and the first capacitor through the inductor, and then through the inductor. The voltage of the second electrode is increased by a second current formed in the first capacitor, the body diode of the first transistor, and the second electrode in the second direction. Plasma display device. The method of claim 1, The first driving circuit may include a second diode having a cathode electrically connected to a first end of the first transistor and an anode electrically connected to a second end of the first transistor. Plasma display device further comprising. The method of claim 4, wherein The first driving circuit reduces the voltage of the second electrode with a first current in a first direction formed of the second electrode, the first transistor, and the first capacitor through the inductor, and then through the inductor. The voltage of the second electrode is increased by a second current formed in the first capacitor, the first diode, and the second electrode in a second direction. Plasma display device. The method according to any one of claims 3 to 5, And the first driving circuit increases the voltage of the second electrode and applies the second voltage to the second electrode through the second transistor. The method of claim 6, When the voltage of the second electrode is reduced to a predetermined voltage by the first current, when the current in the first direction remains in the inductor, the current in the first direction is recovered to the first capacitor, And a second current in the second direction is transferred from the first capacitor to the inductor after the current in the first direction decreases to 0A. The method of claim 7, wherein The selection circuit includes a third transistor electrically connected to a first end of the selection circuit and the second electrode, and a fourth transistor electrically connected between the second electrode and the predetermined voltage, And the current in the first direction is recovered to the first capacitor through the body diodes of the third and fourth transistors. The method of claim 6, The first driving circuit has the inductor and the first through the second transistor and the first transistor in a state where the voltage of the second electrode is substantially maintained at the second voltage before the voltage of the second electrode is decreased. A plasma display device which supplies a third current in the first direction to one capacitor. The method according to any one of claims 1 to 5, And the second transistor is an n-channel (nMOS) transistor. A plurality of first electrodes and a plurality of second electrodes are formed, and a capacitive load is formed by the first electrode and the second electrode, and an output terminal is connected to a first end of a selection circuit electrically connected to the first electrode. An electrically connected inductor, a first transistor electrically connected to a first end of the selection circuit to supply a first voltage to the first electrode selected by the selection circuit, and to drive the first transistor A method of driving a plasma display panel comprising a driving circuit including a capacitor charging a voltage and having a first end electrically connected to a first end of the first transistor. The driving method, Charging an electric charge to the capacitor; Discharging a current in a first direction through the inductor to reduce a voltage of a first electrode selected by the selection circuit among the plurality of first electrodes; Reselecting a first electrode to which the first voltage is applied from the plurality of first electrodes through the selection circuit; Increasing the voltage of the selected first electrode to a current in a second direction opposite to the first direction formed through the inductor after the current in the first direction becomes 0A; And Turning on the first transistor to apply the first voltage to the selected first electrode, The current in the first direction is formed by a second transistor electrically connected to the inductor, the current in the second direction is formed by a diode formed in parallel to the second transistor, and the path in which the capacitor is charged and the first Current in two directions A method of driving a plasma display panel. The method of claim 11, The driving circuit further includes a switch electrically connected to the first end of the capacitor, To turn on the switch to charge the capacitor A method of driving a plasma display panel. The method of claim 11, And supplying current in the first direction to the inductor before reducing the voltage of the selected first electrode. The method according to claim 11 or 13, A second voltage is applied to the first electrode unselected by the selection circuit. The first stage voltage of the selection circuit is substantially equal to the first electrode voltage selected by the selection circuit, When the first end voltage of the selection circuit decreases to a third voltage larger than the second voltage when the current in the first direction becomes 0A, the first end voltage of the selection circuit is decreased by the current in the second direction. And a plasma display panel increasing at the third voltage. The method according to claim 11 or 13, And the first transistor is an n-channel (nMOS) transistor.

Images