KR100536203B1 - Plasma display panel and driving method thereof - Google Patents

Abstract

The present invention provides a method of driving a plasma display panel which can reduce an address period by improving a driving waveform applied to an X electrode in an address period.

According to the present invention, the plasma display panel is arranged so that the first and second electrode lines are alternately arranged side by side and the address electrodes are crossed with the lines, and a driving waveform including a reset period, an address period, and a sustain period is applied and driven. do. Specifically, during the address period, a scan pulse for applying the first voltage Vscl for the first time Tsc is sequentially applied to each of the first electrodes, and to each scan pulse applied to the first electrodes. In response, the second voltage Vxscl is applied to the second electrodes for the second time T1 and then the third voltage Vb is applied for the third time T2. Here, the second voltage may be greater than the first voltage. In addition, the second voltage may be a ground voltage, and the third voltage Vb may be a voltage applied to the second electrode at the end of the reset period. The time point of the first time Tsc may be the same as the time point of the second time T1, or the time point of the first time Tsc may be later than the time point of the second time T1.

Description

Plasma display panel and driving method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a driving method thereof, and more particularly, to a plasma display panel capable of increasing display brightness and a driving method thereof.

Recently, flat display devices such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel have been actively developed. Among the flat panel display devices, the plasma display panel has advantages of higher luminance and luminous efficiency and wider viewing angle than other flat panel display devices. Accordingly, the plasma display panel is in the spotlight as a display device to replace the conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

First, a structure of a general plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partially exploded perspective view illustrating a structure of a general plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 are arranged in parallel on the first glass substrate 1. A plurality of address electrodes 8 covered with the insulator layer 7 are provided on the second glass substrate 6. A partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The first glass substrate 1 and the second glass substrate 6 have a discharge space 11 therebetween so that the scan electrode 4 and the address electrode 8 and the sustain electrode 5 and the address electrode 8 are orthogonal to each other. They are arranged to face each other. The discharge space at the intersection of the address electrode 8 and the pair of the scanning electrode 4 and the sustain electrode 5 forms a discharge cell 12.

FIG. 2 is a diagram schematically illustrating an arrangement of electrodes of the plasma display panel of FIG. 1.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix configuration of m × n. Specifically, the address electrodes A1 to Am are arranged in the column direction and the scan electrodes of n rows in the row direction. (Y1 to Yn) (hereinafter referred to as Y electrode) and sustain electrodes X1 to Xn (hereinafter referred to as X electrode) are alternately arranged. That is, the X electrodes X1 to Xn and the Y electrodes Y1 to Yn are formed in a predetermined pattern on the back of the first glass substrate 1 to be orthogonal to the address electrodes A1 to Am. Discharge cells 12 are formed at each crossing point. The plasma forming gas is sealed in the discharge space of the discharge cell 12 and discharged by a pulse applied to the three electrodes to display an image.

As a driving method of the plasma display panel 1 having the above structure, an address-display separation (ADS) driving method in which a subfield is driven by dividing into a reset period, an address period, and a sustain period is US. It is disclosed in patent no.

3 is a view showing a driving waveform of a subfield of the plasma display panel used in the address-display separation driving method.

As shown in FIG. 3, each subfield includes a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charge state of the previous sustain discharge and to set up wall charge in order to stably perform the next address discharge. The address period is a period in which wall charges are accumulated on cells (addressed cells) that are turned on by selecting cells that are turned on and cells that are not turned on in the panel. The sustain period is a period in which a discharge for actually displaying an image on the addressed cells is performed.

Here, the wall charge refers to a charge formed in the wall of the discharge cell (for example, the dielectric layer) close to each electrode and accumulated in the electrode. Such wall charges are not actually in contact with the electrodes themselves, but here wall charges are described as "formed", "accumulated" or "stacked" on the electrodes. In addition, the wall voltage refers to a potential difference formed on the wall of the discharge cell by the wall charge.

In such an address-display separation driving method, during the address period, as shown in FIG. 3, scan pulses of the scan voltage Vscl are sequentially applied to the Y electrodes Y1 to Yn, and a predetermined predetermined value is commonly applied to the X electrodes. The voltage Vb is continuously applied. That is, after the reset period ends, negative charges accumulate on the X electrode and the Y electrode, positive charges accumulate on the address electrode A, and an address discharge occurs when the scan pulse and the address pulse are simultaneously applied in the address period. Will occur.

Sufficient address discharge will not occur until a predetermined time has passed after the scanning pulse and the address pulse were applied. The delay time until sufficient address discharge occurs is called an address discharge delay time. This address discharge delay is a cause of failing to shorten an address period especially in driving a large panel or an HD display panel, and is a barrier to high speed driving.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display panel and a driving method thereof capable of reducing an address period by improving a driving waveform applied to an X electrode in an address period.

According to an aspect of the present invention, there is provided a method of driving a plasma display panel, wherein first and second electrode lines are alternately arranged side by side, and address electrodes are arranged to intersect the lines, and a reset period. As a driving method of a plasma display panel which is driven by a driving waveform including an address period and a sustain period,

During the address period,

Scan pulses for sequentially applying a first voltage Vscl for a first time Tsc to each of the first electrodes are sequentially applied.

In response to each scan pulse applied to the first electrodes, a second voltage Vxscl is applied to the second electrodes for a second time T1 and a third voltage Vb for a third time T2. ) Is commonly applied.

Here, the second voltage may be greater than the first voltage.

The second voltage may be a ground voltage, and the third voltage Vb may be a voltage applied to the second electrode at the end of the reset period.

The time point of the first time Tsc may be the same as the time point of the second time T1, or the time point of the first time Tsc may be later than the time point of the second time T1.

Plasma display panel according to another aspect of the present invention,

A display panel in which scan and sustain electrodes are alternately arranged side by side and address electrodes are arranged to cross the lines; And

A driving unit which applies a corresponding driving waveform to each of the scan and sustain electrodes for a reset period, an address period, and a sustain period, wherein a first voltage Vscl is applied to each of the scan electrodes during the address period. A driving unit which sequentially applies a scanning pulse applied for a period of time, applies a second voltage Vxscl to the sustain electrodes in common during the first time, and then applies a third voltage Vb higher than the second voltage. Include.

The second voltage Vxscl may be greater than the first voltage Vscl.

The second voltage may be a ground voltage, and the third voltage Vb may be a voltage applied to the second electrode at the end of the reset period.

Hereinafter, with reference to the accompanying drawings will be described in detail embodiments of the present invention.

4 illustrates a driving waveform applied to a plasma display panel according to a first embodiment of the present invention.

First, during the reset-period, a waveform including a rising ramp section rising from the potential Vs to the potential Vset and a falling ramp section falling from the potential Vs to the potential Vnf is applied to the Y electrode. Is approved. This waveform is applied to form the wall charges of all the discharge cells in the same state after the last sustain period ends. Therefore, regardless of whether discharge occurred during the last sustain period or not, discharge cells accumulate on the Y electrode in the rising lamp section and weakly discharge the wall charges accumulated in the falling lamp section in all discharge cells. The charges are in the same state.

Next, during the address period (Address-period), the scan high voltage Vsch is applied to each of the Y electrodes Y1, ..., Yk, ... Yn, and the scan pulses of the scan low voltage Vscl are sequentially applied. When the scan pulse is applied to the Y electrode, addressing is performed by applying the address voltage Va to the address electrode Ak of the cell in which addressing is required among the address electrodes A1, ..., Ak, ..., Am. In addition, a pulse waveform having a certain period in common is applied to the X electrode X.

The driving waveforms applied to the Y electrode and the common X electrode in the address period will be described in more detail with reference to FIG.

FIG. 5 is an enlarged view of a scanning pulse sequentially applied to the Y electrodes and a pulse waveform applied to the common X electrode in the first embodiment.

As shown in FIG. 5, during the time Tsc when the scan low voltage Vscl is applied to the Y electrode, the voltage Vxscl is applied to the X electrode for a predetermined time T1, and the voltage (V2) during the time T2. Vb) is applied.

For example, a scan pulse of a negative scan low voltage Vscl is applied to the Y electrode Yk for a time Tsc, and a positive address voltage Va is applied to the address electrode Ak for a time Tsc for addressing. When applied, an address discharge is generated between the Y electrode and the A electrode of the display cells Yk and Ak.

At the same time, the voltage Vxscl is applied to the common X electrode X during the time T1, and the positive voltage Vb is applied during the time T2. By applying the voltage Vxscl to the X electrode during the time T1, immediately after the end of the reset period, the electrons accumulated on the X electrode and the electrons accumulated on the Y electrode become space charges at the same time to participate in the address discharge. The address discharge delay time can be shortened. Therefore, the address period can be shortened and high-speed driving of the display panel can be realized.

When a positive voltage Vb is applied to the X electrode during the time T2, electrons of the space charge generated by the address discharge accumulate on the X electrode. As a result, the negative charge generated by the address discharge is accumulated on the X electrode and the positive electrode is accumulated on the Y electrode, so that effective and reliable addressing is realized in the display cells Yk and Ak.

Next, the scan pulse of the scan low voltage Vscl is applied to the Y electrode Yk + 1 for the next time Tsc, and the positive address voltage Va is applied to the address electrode Ak for the time Tsc for addressing. Is applied. In addition, to assist the addressing of the Y electrode Yk + 1, the voltage Vxscl is applied to the X electrode during the time T3 and the voltage Vb is applied during the time T4 as described above. In this way, the addressing of the display cells Yk + 1, Ak is performed effectively.

Here, the magnitude of the voltage Vxscl applied to the X electrode during the time T1 should be greater than the scan low voltage Vscl applied to the Y electrode. If the voltage Vxscl is smaller than the scan low voltage Vscl, the voltage Va is reduced at the Y electrode to which the scanning pulse is not applied, for example, at the display cells Yk + 2 and Ak formed at the Y electrode Yk + 2. Discharge may occur between the address electrode Ak applied and the X electrode applied with a voltage Vxscl lower than the scan low voltage, thereby causing an incorrect address discharge.

Alternatively, the time T1 when the voltage Vxscl is applied to the X electrode must be shorter than the discharge delay time between the X electrode and the address electrode Ak to which the address voltage Va is applied. When the time T1 becomes longer than the discharge delay time between the X electrode and the address electrode Ak to which the address voltage Va is applied, the time T1 is formed on the Y electrode other than the Y electrode Yk to which the scan low voltage Vscl is applied. In the display cell, discharge occurs between the address electrode Ak to which the voltage Va is applied and the X electrode to which the voltage Vxscl is applied, thereby causing an incorrect address discharge.

6 illustrates a driving waveform applied to a plasma display panel according to a second embodiment of the present invention.

The second embodiment of the present invention differs from the first embodiment in that the voltage Vxscl is applied to the X electrode before the scan low voltage Vscl is applied to the Y electrode.

In Fig. 6, during the reset period, a waveform including a rising ramp section rising from the potential Vs to the potential Vset and a falling ramp section falling from the potential Vs to the potential Vnf is applied to the Y electrode. This waveform is applied to form the wall charges of all the discharge cells in the same state after the last sustain period ends. Therefore, regardless of whether discharge occurred during the last sustain period or not, discharge cells accumulate on the Y electrode in the rising lamp section and weakly discharge the wall charges accumulated in the falling lamp section in all discharge cells. The charges are in the same state.

Next, during the address period, the scan high voltage Vsch is applied to each of the Y electrodes Y1, ..., Yk, ... Yn, and the scan pulses of the scan low voltage Vscl are sequentially applied. When the scanning pulse is applied to the Y electrode, addressing is performed by applying the address voltage Va to the address electrode Ak of the cell where addressing the electrodes A1, ..., Ak, ..., Am is required. In addition, a pulse of the voltage Vxscl is applied to the X electrode at a predetermined cycle faster by a predetermined time Td than the time when the scan low voltage Vscl is applied to the Y electrode.

The driving waveforms applied to the Y electrode and the common X electrode in the address period will be described in more detail with reference to FIG.

FIG. 7 is an enlarged view illustrating scan pulses sequentially applied to the Y electrodes and pulse waveforms applied to the common X electrode in the second embodiment.

As shown in FIG. 7, the scan low voltage Vscl is applied to the Y electrode for a time Tsc, the voltage Vxscl is applied to the X electrode for a predetermined time T1, and the voltage (for the time T2). Vb) is applied. At this time, the time T1 is earlier than the time Tsc by the time Td. That is, the waveform applied to the X electrode in this embodiment is the waveform in which the waveform applied to the X electrode in the first embodiment is shifted by a predetermined time Td.

Thus, by first applying a voltage (Vxscl) to the X electrode before applying the scan low voltage to the Y electrode, electrons accumulated on the X electrode immediately after the end of the reset period become a space charge before applying the scan low voltage to the Y electrode. Since the address discharge delay time can be more efficiently engaged, the address period can be further shortened.

When a positive voltage Vb is applied to the X electrode during the time T2, electrons generated by the address discharge accumulate on the X electrode. As a result, the negative charge generated by the address discharge is accumulated on the X electrode and the positive electrode is accumulated on the Y electrode, so that effective and reliable addressing is realized in the display cells Yk and Ak.

Here, the magnitude of the voltage Vxscl applied to the X electrode during the time T1 should be greater than the scan low voltage Vscl applied to the Y electrode. If the voltage Vxscl is smaller than the scan low voltage Vscl, the voltage Va is reduced at the Y electrode to which the scanning pulse is not applied, for example, at the display cells Yk + 2 and Ak formed at the Y electrode Yk + 2. Discharge may occur between the address electrode Ak applied and the X electrode applied with a voltage Vxscl lower than the scan low voltage, thereby causing an incorrect address discharge.

Alternatively, the time T1 when the voltage Vxscl is applied to the X electrode must be shorter than the discharge delay time between the X electrode and the address electrode Ak to which the address voltage Va is applied. When the time T1 becomes longer than the discharge delay time between the X electrode and the address electrode Ak to which the address voltage Va is applied, the time T1 is formed on the Y electrode other than the Y electrode Yk to which the scan low voltage Vscl is applied. In the display cell, discharge occurs between the address electrode Ak to which the voltage Va is applied and the X electrode to which the voltage Vxscl is applied, thereby causing an incorrect address discharge.

8 is a diagram schematically illustrating a configuration of a plasma display panel according to the present invention.

As shown in FIG. 8, the plasma display panel according to the present invention includes a plasma panel 100, a controller 200, an address driver 300, an X electrode driver 400, and a Y electrode driver 500.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, a plurality of X electrodes X1 to Xn and Y electrodes Y1 to Yn arranged alternately in a row direction. Include. The X electrodes X1 to Xn are all commonly connected common X electrodes.

The controller 200 receives the image signal from the outside and controls the X electrode driving driving circuit signal, the Y electrode driving driving signal, and the address electrode driving signal to be output.

The X electrode driver 400 receives an X electrode driving control signal from the controller 200 and applies a driving voltage to a common X electrode to which the X electrodes X1 to Xn are commonly connected.

 The Y electrode driver 500 receives a Y electrode driving control signal from the controller 200 and applies a driving voltage to the Y electrode.

Specifically, as shown in FIG. 4, the Y electrode driver 200 applies the scan high voltage Vsch to the Y electrodes Y1 to Yn during the address period, and sequentially applies the scan pulses to sequentially apply the scan low voltage Vscl. Is authorized.

When the scan pulse is applied to the Y electrode, the address driver 300 applies the address voltage Va to the address electrode of the cell to which the address is required to perform addressing.

At this time, the X electrode driver 400 applies a pulse waveform having a predetermined period in accordance with the scanning pulse sequentially applied to the Y electrodes to the X electrode (X) connected in common.

For example, while the scan pulse is applied to the Y electrode (Tsc), the X electrode driver 400 applies the voltage Vxscl to the common X electrode for a specific time T1 and then the common X electrode for a specific time T2. The voltage Vb can be applied to it.

Alternatively, the X electrode driver 400 applies the voltage Vxscl to the common X electrode for a time T1 faster than the time when the scan pulse is applied to the Y electrode, and then the time T2. The voltage Vb can be applied to the common X electrode.

In this way, by applying the voltage Vxscl to the X electrode during the time T1, the electrons accumulated on the X electrode and the electrons accumulated on the Y electrode immediately participate in the address discharge at the same time. The address discharge delay time can be shortened. Therefore, the address period can be shortened and high-speed driving of the display panel can be realized.

When a positive voltage Vb is applied to the X electrode during the time T2, electrons of the space charge generated by the address discharge accumulate on the X electrode. As a result, of the space charges generated by the address discharge, electrons are accumulated on the X electrode, and positively charged Y electrodes are stacked, so that effective and reliable addressing is realized in the display cell.

Although the present invention has been described above based on the preferred embodiments, the embodiments are intended to illustrate and not limit the invention. It will be apparent to those skilled in the art that various changes, modifications, and the like can be made to the embodiments without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all changes or modifications.

According to the present invention, an address discharge delay time can be shortened by applying a pulse waveform having a certain period to the X electrodes in accordance with the scanning pulse applied to the Y electrode. That is, the address period can be shortened by shortening the address discharge delay time, thereby realizing high-speed driving of the display panel.

In addition, by applying a voltage Vxscl greater than the voltage Vscl of the scan pulse applied to the Y electrode to the common X electrode, the Y electrode to be scanned without causing an erroneous discharge to a display cell formed on another non-scanned Y electrode. The addressing of can be performed more effectively.

Alternatively, by applying a voltage Vxscl to the common X electrode for a time shorter than the address discharge delay time, addressing of the Y electrode to be scanned can be performed more effectively without causing an erroneous discharge to a display cell formed on another non-scanning Y electrode. Can be.

In addition, since the voltage Vb is applied again after the voltage Vxscl is applied to the common X electrode for a specific time, positive charges can be efficiently accumulated in the Y electrode after the address discharge is generated.

1 is a partially exploded perspective view illustrating a structure of a general plasma display panel.

FIG. 2 is a diagram schematically illustrating an arrangement of electrodes of the plasma display panel of FIG. 1.

3 is a diagram illustrating driving waveforms of a subfield of a plasma display panel having three electrodes described above.

4 illustrates a driving waveform applied to a plasma display panel according to a first embodiment of the present invention.

FIG. 5 is an enlarged view of a scanning pulse sequentially applied to the Y electrodes and a pulse waveform applied to the common X electrode in the first embodiment.

6 illustrates a driving waveform applied to a plasma display panel according to a second embodiment of the present invention.

FIG. 7 is an enlarged view of a scanning pulse sequentially applied to the Y electrodes and a pulse waveform applied to the common X electrode in the second embodiment.

8 is a diagram schematically illustrating a configuration of a plasma display panel according to the present invention.

Claims (8)

In the driving method of the plasma display panel in which the first and second electrode lines are arranged side by side alternately, the address electrodes are arranged to cross the lines, and a driving waveform including a reset period, an address period and a sustain period is applied and driven. In During the address period, Scan pulses for sequentially applying a first voltage Vscl for a first time Tsc to each of the first electrodes are sequentially applied. In response to each scan pulse applied to the first electrodes, a second voltage Vxscl is applied to the second electrodes for a second time T1 and a third voltage Vb for a third time T2. ) Is a method of driving a plasma display panel. The method of claim 1, And the second voltage is greater than the first voltage. The method of claim 2, And wherein the second voltage is a ground voltage, and the third voltage (Vb) is a voltage applied to the second electrode at the end of the reset period. The method according to any one of claims 1 to 3, The time point of the first time Tsc is the same as the time point of the second time T1. The method according to any one of claims 1 to 3, A method of driving a plasma display panel in which a time point of a first time Tsc is later than a time point of the second time T1. In the plasma display panel, A display panel in which scan and sustain electrodes are alternately arranged side by side and address electrodes are arranged to cross the lines; And A driving unit which applies a corresponding driving waveform to each of the scan and sustain electrodes for a reset period, an address period, and a sustain period, wherein a first voltage Vscl is applied to each of the scan electrodes during the address period. A driving unit which sequentially applies a scanning pulse applied during the first period, applies a second voltage Vxscl to the sustain electrodes in common during the first time, and then applies a third voltage Vb higher than the second voltage. Plasma display panel comprising a. The method of claim 6, The second voltage Vxscl is greater than the first voltage Vscl. The method according to claim 6 or 7, The second voltage is a ground voltage, and the third voltage (Vb) is a voltage applied to the second electrode at the end of the reset period.