KR20040029690A - Method and apparatus for driving plasma display panel - Google Patents

Abstract

PURPOSE: An apparatus for driving a plasma display panel and its driving method are provided to enable to operate stably at a low temperature. CONSTITUTION: The apparatus for driving a plasma display panel comprising a scan electrode receiving a ramp-up waveform during a setup period comprises a ramp-up voltage source, and a switching device(Q) installed between the ramp-up voltage source and the scan electrode, and a control signal supply part(CS) to control the switching device. The first slope control part(30) is installed between the ramp-up voltage source and the switching device and the control signal supply part, and controls a ramp-up slope of the ramp-up waveform supplied to the scan electrode from the ramp-up voltage source without regard to temperature. The second slope control part(34) is installed between the first slope control part and the control signal supply part, and controls a slope of the ramp-up waveform supplied to the panel from the ramp-up voltage source in correspondence to temperature. And a device protection part(32) is installed between the control signal supply part and the switching device, and prevents the switching device from being broken.

Description

Driving device and driving method of plasma display panel {METHOD AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and a driving method of a plasma display panel, and more particularly, to a driving apparatus and a driving method of a plasma display panel to enable stable operation at low temperatures.

Plasma Display Panel (hereinafter referred to as "PDP") displays an image including characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe inert mixed gas. . Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Y are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

On the other hand, the ramp ramp up supplied during the setup period is supplied by the ramp ramp supply shown in FIG.

Referring to FIG. 4, the conventional rising ramp waveform supply unit controls the switching element Q and the switching element Q provided between the rising ramp waveform voltage source Vr and the panel (ie, the scanning electrode Y). The control signal supply unit CS, the resistor R and the diode D connected in parallel between the control signal supply unit CS and the gate terminal of the switching element Q, and the gate terminal of the switching element Q. The capacitor C connected between the drain terminals is provided.

The rising ramp waveform voltage source Vr is connected to the drain terminal of the switching element Q. The control signal supply unit CS supplies a control signal to the gate terminal of the switching element Q to control the switching operation of the switching element Q.

The operation of the rising ramp waveform supply unit will be described in detail. First, the control signal supply unit CS supplies the control signal of the square wave to the switching element Q. At this time, the voltage value flowing to the panel through the switching element Q has a predetermined slope by the RC time constant values of the capacitor C and the resistor R. In other words, the voltage supplied to the panel via the switching element Q rises with a predetermined slope. That is, the rising ramp waveform Ramp-up is supplied to the scan electrode Y.

On the other hand, when the initialization waveform falls from the potential of the rising ramp waveform voltage Vr of about 400V to a predetermined voltage (about 180V), a reverse voltage of about -70V is generated between the gate and the source terminal of the switching element Q. . At this time, the diode D prevents the switching element Q from being damaged by the reverse voltage. That is, the conventional rising ramp waveform supply unit supplies the rising ramp waveform Ramp-up having a constant slope to the panel according to the RC time constant by the resistor R and the capacitor C.

On the other hand, the conventional PDP operating as described above has a problem that the contrast is reduced by the light generated in the initialization period. In detail, the discharge occurs between the scan electrode Y and the sustain electrode Z and the scan electrode Y and the address electrode X by the rising ramp waveform Ramp-up supplied during the initialization period. As shown in FIG. 5, negative wall charges are formed on the scan electrode Y, and positive wall charges are formed on the sustain electrode Z.

Here, as a result of the experiment, the discharge between the scan electrode (Y) and the sustain electrode (Z) occurs at a lower voltage than the discharge between the scan electrode (Y) and the address electrode (X). As such, the discharge generated between the scan electrode Y and the sustain electrode Z causes the amount of light emitted toward the observer to be larger than the amount of light emitted by the discharge between the scan electrode Y and the address electrode X. For this reason, the light emission amount is increased in the initialization period, which is the non-display period, so that the contrast characteristic is reduced by that much.

Therefore, in the related art, in order to improve the contrast characteristics of the PDP, a driving method as shown in FIG. 6 is proposed.

6 is a view showing a method of driving a plasma display panel according to another embodiment of the prior art.

Referring to FIG. 6, the PDP driving method according to another exemplary embodiment is divided into an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells. In addition, after the rising ramp waveform Ramp-up is raised to the peak voltage Vr in the setup period, the voltage of the peak voltage Vr is supplied to the scan electrodes Y for a predetermined time. When the peak voltage Vr of the rising ramp waveform Ramp-up is maintained for a predetermined time, wall charges formed in the discharge cells are strengthened.

In the first half of the setup period (the first half of the rising ramp waveform), the base voltage is supplied to the sustain electrodes Z, and in the second half of the setup period (the second half of the rising ramp waveform + the sustain period of the peak voltage Vr), the sustain electrodes are provided. (Z) is plotted. In the first half of the setup period in which the base voltages are supplied to the sustain electrodes Z, a discharge occurs between the scan electrodes Y and the sustain electrodes Z to form wall charges in the discharge cells. In the second half of the setup period in which the sustain electrodes Z are floated, no discharge occurs between the scan electrodes Y and the sustain electrodes Z. FIG. That is, in the second half of the setup period, the discharge occurs only between the scan electrodes Y and the address electrodes X. FIG.

In other words, the surface discharge can be prevented between the scan electrodes Y and the sustain electrodes Y by floating the sustain electrodes Z in the second half of the setup period. Therefore, according to another conventional embodiment, the luminance of the initialization period is lowered, and thus the contrast is improved. Here, when the sustain electrodes Z are floated, the amount of wall charges formed in the discharge cells during the setup period is smaller than that of the PDP driving method shown in FIG.

On the other hand, a predetermined voltage is induced in the sustain electrodes Z in the second half of the setup period in which the sustain electrodes Z are in a floating state. In other words, a predetermined voltage is induced to the sustain electrodes Z by the period of maintaining the rising ramp waveform Ramp-up and the peak voltage Vr applied to the scan electrodes Y later in the setup period. do.

The falling ramp waveform Ramp-down is supplied to the scan electrodes Y in the set down period. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

However, the PDP according to another conventional embodiment driven as described above generates bright point misfiring when operated at low temperature (about 20 ° C. to −20 ° C.). In other words, when the low temperature operating characteristics of the PDP according to the operating temperature, the bright point discharge is generated in the plurality of discharge cells. Such bright spot discharging is slowed down at low temperatures and no discharge occurs between the scan electrodes Y and the sustain electrodes Z at the end of the setup period (i.e., the sustain electrodes Z in the floating state). Induces a predetermined voltage).

In detail, when the movement of particles is slowed at a low temperature, erasure discharge due to an erase ramp waveform (erase) does not occur normally. In the cells in which such erasure discharge is not normally generated, wall charges formed in the scan electrode Y and the sustain electrode Z are not erased as shown in FIG. 7.

Thereafter, a positive rising ramp waveform Ramp-up is supplied to the scan electrode Y during the setup period. At this time, since negative wall charges are formed in the scan electrode Y (that is, the voltage applied to the scan electrode Y and the wall charges formed in the scan electrode Y have opposite polarities), the setup is performed. Normal discharge does not occur in the period. In particular, since no discharge occurs between the scan electrode Y and the sustain electrode Z in the second half of the setup period, sufficient setup discharge does not occur, so that desired wall charges are not formed in the discharge cells. Therefore, no discharge occurs even in the setdown period following the setup period. As such, if normal discharge does not occur in the initialization period, wall charges excessively formed in the erasing period affect the address period and the sustain period. In other words, the wall discharges excessively formed in the discharge cells cause an undesired strong point discharge in the sustain period.

On the other hand, such a bright spot discharge is mainly generated in the discharge cells formed with blue and green phosphors (in particular, discharge cells formed with green phosphors). In other words, the blue and green phosphors have a discharge start voltage than the red phosphors. Since approximately 20 to 30 V is set high, normal discharge does not occur in the initializing period, and thus bright spot false discharge occurs.

Accordingly, it is an object of the present invention to provide a driving apparatus and a driving method of a plasma display panel which enable stable operation at low temperatures.

1 is a perspective view showing a discharge cell of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing one frame of a conventional AC surface discharge type plasma display panel.

3 is a waveform diagram showing a driving waveform supplied to electrodes during the subfield shown in FIG.

4 is a circuit diagram showing a conventional rising ramp waveform supply unit.

5 shows wall charges formed on electrodes in an initialization period.

Fig. 6 is a waveform diagram showing a method of driving a plasma display panel according to another conventional embodiment.

7 shows wall charges formed in cells in which erasing discharge is not normally generated at low temperature.

8 is a circuit diagram showing a ramp ramp waveform supply unit according to an embodiment of the present invention.

FIG. 9 is a waveform diagram illustrating a rising ramp waveform supplied at a temperature higher than a low temperature by the rising ramp waveform supply unit of FIG. 8.

FIG. 10 is a waveform diagram illustrating rising ramp waveforms supplied at a low temperature by the rising ramp waveform supply unit of FIG. 8; FIG.

11A and 11B are diagrams showing voltage differences of driving waveforms supplied at a low temperature and a temperature higher than a low temperature during a setup period.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrodes 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

30, 34: tilt control unit 32: device protection unit

In order to achieve the above object, a driving apparatus of a plasma display panel of the present invention includes a rising ramp waveform voltage source; A switching element provided between a rising ramp waveform voltage source and the scan electrode; A control signal supply unit for controlling the switching element; A first slope control unit disposed between the rising ramp waveform voltage source, the switching element, and the control signal supply unit to control the rising slope of the rising ramp waveform supplied from the rising ramp waveform voltage source to the scan electrode regardless of temperature; A second slope control unit installed between the first slope control unit and the control signal supply unit for controlling the rising slope of the rising ramp waveform supplied to the panel from the rising ramp waveform voltage source in correspondence with the temperature; It is provided between the control signal supply unit and the switching element is provided with an element protection unit for preventing damage to the switching element.

The second slope controller is characterized in that the rising ramp waveform having a high rising slope is supplied to the scan electrode as the temperature is lowered.

The first slope controller includes a resistor and a capacitor, and controls the rising slope of the rising ramp waveform by the time constant of the resistor and the capacitor.

The second slope control unit includes a thermistor disposed between the resistor and the control signal supply unit.

The rising slope of the rising ramp waveform is controlled by the third resistance value of the sum of the first resistance value of the thermistor and the second resistance value of the resistor and the time constant of the capacitor.

The thermistor has a constant resistance temperature coefficient at which the resistance value increases as the temperature increases and the resistance value decreases when the temperature decreases.

The device protection unit includes a diode connected in parallel with a resistor and a surge.

In the second half of the setup period, the sustain electrode formed in parallel with the scan electrode is floated.

When the sustain electrode is floated at a temperature higher than the low temperature and the rising period of the rising ramp waveform overlaps, a constant voltage is induced to the sustain electrode.

At a low temperature, the sustain electrode floats and the rising period of the rising ramp waveform do not overlap, so that no voltage is induced to the sustain electrode.

In the driving method of the plasma display panel of the present invention, the rising slope of the rising lamp waveform is set differently at a temperature lower than the low temperature.

The rising slope at the low temperature is greater than the rising slope at a temperature above the low temperature.

Floating the sustain electrode later in the setup period.

The period in which the sustain electrode floats at the low temperature and the period in which the rising lamp waveform rises do not overlap.

The period in which the sustain electrode is floated at the temperature higher than the low temperature and the period in which the rising lamp waveform is raised overlap.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 11B.

8 is a circuit diagram illustrating an up ramp waveform supply unit according to an exemplary embodiment of the present invention. The rising ramp waveform supply portion of the present invention is used when the sustain electrode Z is floated in the second half of the setup period.

Referring to FIG. 8, the ramp ramp supply unit according to the embodiment of the present invention includes a first slope control unit 30, an element protection unit 32, a second slope control unit 34, and a control signal supply unit CS. . The control signal supply unit CS controls the switching operation of the switching element Q.

The first slope control unit 30 is installed between the rising ramp waveform voltage source Vr, the switching element Q, and the control signal supply unit CS, and scan electrode via the switching element Q from the rising ramp waveform voltage source Vr. Controls the slope of the ramp ramp up supplied to Y. The inclination controller 30 is a first capacitor provided between the capacitor C connected between the gate terminal and the drain terminal of the switching element Q and the gate terminal and the control signal supply unit CS of the switching element Q. A resistor R1 is provided. The first slope control unit 30 controls the slope of the ramp ramp up regardless of the temperature.

The second slope control section 34 is provided between the first slope control section 30 and the control signal supply section CS (that is, installed in series with the first resistor R1) to switch from the rising ramp waveform voltage source Vr. The slope of the ramp ramp Ramp-up supplied to the scan electrode Y is controlled via the device Q. The second slope control unit 34 controls the slope of the ramp ramp up in response to the temperature. To this end, the second slope control unit 34 has a thermistor R2. Here, the thermistor R2 uses a static thermistor having a constant resistance temperature coefficient at which the resistance value increases when the temperature increases and the resistance value decreases when the temperature decreases.

The element protection unit 32 prevents the switching element Q from being destroyed by the reverse voltage applied to the switching element Q. The device protection unit 32 includes a diode D installed in parallel with the first resistor R1 and the thermistor R2.

When the rising ramp waveform supply unit operates in detail at a low temperature or more, the control signal supply unit CS first supplies a control signal of a square wave to the switching element Q. At this time, the resistance value R ″ of R1 + R2 of the first slope control unit 30 and the second slope control unit 34 and the R ″ C time constant value of the capacitor C are passed through the switching element Q. The voltage value supplied to the panel rises with a predetermined slope. At this time, the thermistor R2 of the second slope control unit 34 has a high resistance value at a temperature equal to or lower than the low temperature, and thus the ramp ramp Ramp-up1 rises during the time of T1 with the first slope as shown in FIG. 9. The ramp waveform voltage source Vr rises to the voltage.

On the other hand, the sustain electrode Z is kept floating during the second half of the setup period. At this time, the rising period of the rising ramp waveform Ramp-up1 and the floating period Td of the sustain electrode Z overlap each other, thereby inducing a predetermined voltage to the sustain electrode Z. In other words, at a temperature equal to or lower than the low temperature, the ramp ramp Ramp-up1 rises for a time T1, and at this time, the period T1 overlaps the period Td in which the sustain electrode Z is floated. The predetermined voltage is induced.

That is, when the rising ramp waveform supply unit of the present invention is driven at a temperature higher than the low temperature, the driving waveform as shown in FIG. 6 is supplied to the panel. In other words, when the PDP of the present invention is driven at a temperature higher than the low temperature, no surface discharge occurs between the scan electrode Y and the sustain electrode Z in the second half of the setup period. Therefore, in the present invention, when the PDP is operated at a temperature equal to or lower than the low temperature, the brightness of the initialization period can be lowered to improve the contrast.

On the other hand, when the initialization waveform falls from the potential of the rising ramp waveform voltage Vr of about 400V to a predetermined voltage (about 180V), a reverse voltage of about -70V is generated between the gate and the source terminal of the switching element Q1. . At this time, the element protection unit 32 prevents the switching element Q from being damaged by the reverse voltage.

When the rising ramp waveform supply unit operates at low temperature (about 20 ° C. to −20 ° C.) in detail, first, the control signal supply unit CS supplies a square wave control signal to the switching element Q. FIG. At this time, the resistance value R ″ of R1 + R2 of the first slope control unit 30 and the second slope control unit 34 and the R ″ C time constant value of the capacitor C are passed through the switching element Q. The voltage value supplied to the panel rises with a predetermined slope. At this time, the thermistor R2 of the second slope control unit 34 has a low resistance value at a low temperature, and thus the rising ramp waveform Ramp-up2 has a second slope having a larger slope than the first slope as shown in FIG. 10. The rising ramp waveform voltage source Vr rises to the voltage during the time of T2, which rises to the slope and is less than T1.

On the other hand, the sustain electrode Z is kept floating during the second half of the setup period. At this time, since the rising period T2 of the rising ramp waveform Ramp-up1 and the floating period Td of the sustain electrode Z do not overlap, the sustain electrode Z maintains the base potential. In other words, at a low temperature, the rising ramp waveform Ramp-up2 rises for the time T2. At this time, since the period of T2 does not overlap the period of Td in which the sustain electrode is floated, the sustain electrode Z has no voltage. Not induced.

That is, when the rising ramp waveform supply unit of the present invention is driven at a low temperature, the driving waveform as shown in FIG. 3 is supplied to the panel. As such, when no voltage is induced to the sustain electrode Z at a low temperature, fine discharge may be stably generated in the discharge cells.

In detail, first, a predetermined voltage is induced in the sustain electrode Z by the high resistance value of the second slope controller 34 in the second half of the setup period at a temperature higher than the low temperature. When a predetermined voltage is induced in the sustain electrode Z as described above, a voltage difference of V1 is generated between the sustain electrode Z and the scan electrode Y as shown in FIG. 11A. (In FIG. 11A, the solid line indicates the voltage applied to the scan electrode Y, and the dotted line indicates the voltage applied to the sustain electrode Z.)

On the other hand, the voltage is not induced to the sustain electrode Z by the low resistance value of the second slope controller 34 in the second half of the setup period at a low temperature. If the voltage is not induced to the sustain electrode Z as described above, a voltage difference of V2 higher than V1 is generated between the sustain electrode Z and the scan electrode Y as shown in FIG. 11B. Therefore, stable setup discharge can be caused even at a low temperature. That is, in the present invention, the predetermined voltage is induced to the sustain electrode Z at a temperature higher than the low temperature, and the contrast is improved, and the voltage is not induced to the sustain electrode Z at the low temperature, resulting in stable setup discharge.

As described above, according to the driving apparatus and driving method of the plasma display panel according to the present invention, a predetermined voltage is induced to the sustain electrode at a temperature lower than a low temperature so that surface discharge between the sustain electrode and the scan electrode does not occur, thereby improving contrast. You can. In addition, since the voltage is not induced to the sustain electrode at a low temperature, stable set-up discharge can be caused, thereby preventing low-temperature bright point discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A driving apparatus of a plasma display panel having a scan electrode supplied with a rising ramp waveform during a setup period, A rising ramp waveform voltage source; A switching element provided between the rising ramp waveform voltage source and the scan electrode; A control signal supply unit for controlling the switching element; A first slope control unit disposed between the rising ramp waveform voltage source, the switching element, and a control signal supply unit to control the rising slope of the rising ramp waveform supplied from the rising ramp waveform voltage source to the scan electrode regardless of temperature; A second slope control unit installed between the first slope control unit and the control signal supply unit and controlling a rising slope of the rising ramp waveform supplied from the rising ramp waveform voltage source to the panel in correspondence to a temperature; And an element protection unit disposed between the control signal supply unit and the switching element to prevent breakage of the switching element. The method of claim 1, And the second slope controller is configured to supply a rising ramp waveform having a high rising slope to the scan electrode as the temperature decreases. The method of claim 1, The first slope controller includes a resistor and a capacitor, and controls the rising slope of the rising ramp waveform by the time constant of the resistor and the capacitor. The method of claim 3, The second slope control unit includes a thermistor disposed between the resistor and the control signal supply unit. The method of claim 4, wherein And a rising slope of the rising ramp waveform is controlled by a third resistance value obtained by adding the first resistance value of the thermistor and the second resistance value of the resistor and the time constant of the capacitor. The method of claim 4, wherein And the thermistor has a constant resistance temperature coefficient of decreasing resistance when the temperature increases and decreasing resistance when the temperature decreases. The method of claim 4, wherein And the device protection unit comprises a diode connected in parallel with the resistor and the surge. The method of claim 2, And a sustain electrode formed in parallel with the scan electrode in the second half of the setup period. The method of claim 8, And a constant voltage is induced to the sustain electrode by overlapping a time when the sustain electrode is floated at a temperature higher than a low temperature and a rise period of the rise lamp waveform. The method of claim 8, And a voltage is not induced to the sustain electrode because the time when the sustain electrode floats at a low temperature does not overlap with the rise period of the rise lamp waveform. A driving method of a plasma display panel comprising supplying a rising ramp waveform to a scan electrode during a setup period of an initialization period. And a rising slope of the rising ramp waveform is set differently at a low temperature and a temperature higher than the low temperature. The method of claim 11, And the rising slope at the low temperature is greater than the rising slope at the temperature higher than or equal to the low temperature. The method of claim 11, And a sustain electrode is floated in the second half of the set-up period. The method of claim 13, And a period during which the sustain electrode floats at the low temperature and a period during which the rising lamp waveform rises do not overlap. The method of claim 13, And a period in which the sustain electrode floats at a temperature higher than the low temperature and a period in which the rising lamp waveform rises.