JPH11133914A - Drive circuit for gas discharge type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the change in the gradient of a gentle gradient waveform outputted from a drive circuit, to stabilize the discharge action of the gas discharge type display device, to shorten the application time of the gentle gradient waveform outputted from the drive circuit, and to enlarge the freedom degree of the timing design of a drive circuit, even if there are changes in loads such as change in the discharge current and dispersion of electrode floating capacity. SOLUTION: A scanning electrode drive circuit 15 is constituted of an initialization pulse generation circuit S2 having scanning/maintenance pulse generation circuits P1 -PN and a gentle gradient waveform generation circuit U2a . The gentle gradient waveform generation circuit U2a is constituted of a pull-up FETQ connecting the drain to a constant potential point +Vr(V), and a Miller integrator circuit composed of a resistance RG2a whose one end is connected to the gate of the pull-up FETQ and a capacitor CF2a connected between the gate and the drain of the pull-up FETQ.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a gas discharge type display device used for displaying images on a television receiver, an advertisement display board, and the like.

[0002]

2. Description of the Related Art As an AC plasma display panel (hereinafter referred to as a PDP), which is one of the gas discharge type display devices, a two-electrode opposed discharge type, a three-electrode surface discharge type, and the like have been devised. As shown in FIG. 12, the electrode arrangement of the conventional three-electrode surface discharge type PDP 11 constitutes a matrix,
In a column direction are arranged data electrodes DATA ₁ to Data _M of M rows, the row direction sustain electrodes SUS ₁ ~SUS _N scan electrodes SCN ₁ ~SCN _N and N rows of N rows are arranged. M × N cells are formed at each intersection of these matrices. Data electrodes DATA _{1 to} DA of PDP 11
The TA _M is connected to the data electrode driving circuit 12, the scan electrodes in the SCN ₁ ～SCN _N is connected scan electrode driving circuit 13, sustain electrodes SUS ₁ ～SUS maintain the _N-electrode driving circuit 1
4 are connected.

FIG. 13 shows an example of a driving timing chart of such a PDP. By first rise in all the scanning electrodes SCN ₁ ~SCN _N voltage is + Vr In the initialization period (V) is applied to initialization pulse is gradually varying waveform, in cells having generated the address discharge one in the preceding sub-field An initialization discharge in which a discharge current flows from the scan electrode to the data electrode is generated.

Next, during a write period, a write pulse having a voltage of + Vw (V) on predetermined data electrodes DATA _{1 to} DATA _M and a voltage of −Vs on the _first scan electrode SCN _1.
By applying a scanning pulse is (V), causing the writing discharge in the cell of the intersection regions between the specified data electrodes DATA ₁ to Data _M and the scanning electrode SCN _1. Continue similar operations in the scan electrode SCN ₂ ~SCN _N is performed, the writing of data is performed over the entire display screen.

In the following sustain period, all sustain electrodes SUS _{1 to} SUS _N and all scan electrodes SCN _{1 to} SC _{N N}
, A sustain pulse having a voltage of -Vs (V) is applied alternately to start the sustain discharge in the cell where the write discharge has occurred, and thereafter, the sustain discharge is continued while the sustain pulse is continuously applied.

[0006] In the subsequent erase period, a voltage to all the sustain electrodes SUS ₁ ~SUS _N is applied to the erase pulse falls at -Vs (V) is gradually varying waveform, erase the cell was happening the sustain discharge Discharge is caused to stop the sustain discharge.

A plurality of subfields consisting of the above writing period, sustaining period and erasing period are weighted by changing the number of sustaining pulses, and a plurality of subfields are combined to form a subfield train, which is defined as one field (16.7 ms). ,
Perform image display.

In the conventional PDP drive circuit described above, a gentle gradient waveform generation circuit is used to generate an initialization pulse and an erase pulse. Hereinafter, a conventional scan electrode driving circuit and a conventional sustain electrode driving circuit will be described, and among them, a conventional gentle gradient waveform generating circuit will be described.

[0009] Figure 14 is shows the output portion of the conventional scanning electrode driving circuit 13, and a scanning / sustain pulse generating circuit P ₁ to P _N and reset pulse generating circuit S _1. The scan / sustain pulse generation circuits P _{1 to} P _N are connected to pull-up FETs Q _{H1 to} Q _HN whose drains are connected to the output of the initialization pulse generation circuit S ₁ and the source is connected to a constant potential point of −Vs (V). and pull-down FETs Q _L1 to Q _LN were, pulled up FETs Q _H1 to Q _HN parallel connected diodes D _H1 to D _HN (typically, a diode D _H1 to D _HN utilizes the parasitic diode of the pull-up FETs Q _H1 to Q _HN in the push-pull circuit consisting of) and their outputs are connected to the PDP of the scanning electrodes SCN ₁ ~SCN _N. The initialization pulse generation circuit S ₁ has a pull-up FET whose drain is connected to a constant potential point of + Vr (V) via a resistor R _1a.
Q _1a and a pull-down FET Q whose source is grounded
And _LS1, pulldown FETs Q _LS1 parallel connected diodes D _{LS 1} (usually, diode D _LS1 pulldown FET
(Using a parasitic diode of Q _LS1 ). In this reset pulse generating circuit S _1, U ₁ a is a conventional gradually varying waveform generation circuit, and a pull-up FETs Q ₁ a and the resistance R ₁ a.

The operation of the conventional scan electrode drive circuit will be described. First, at the beginning of the initialization period in FIG. 12, the pull-up FETs Q _{H1 to} Q _HN are turned on, and the pull-down FETs Q _L1 to
Q _LN is off, pull-up FET Q _1a is off, and pull-down FET Q _LS1 is on. Accordingly, the scanning electrodes SCN ₁ ~SCN _N pull-down FETs Q _LS1 to, diode D _LS1, the pull-up FETs Q _H1 to Q _HN, 0 through the diode D _H1 ~D _HN (V) is applied. And pull up FE pull-down FETQ _LS1 is turned off
When TQ _1a changes to ON, the constant potential point of + Vr (V) →
Resistance R _1a → Pull-up FET Q _1a → Pull-up FET Q
_H1 to Q _HN → current flows through a path of the scanning electrodes SCN ₁ ~SCN _N, the initialization pulse is applied to the scanning electrodes SCN ₁ ~SCN _N. The rise of this time initialization pulse, the scanning electrodes SCN ₁ ~SCN _N electrodes stray capacitance C _SCi each having (i
= 1 to N) total C _SC = C _SC1 + ... + C _SCN and resistance R _1a
And a gentle gradient waveform determined by the CR time constant circuit. If the screen size is a gas discharge display device of about 20 inches, the value of the resistor R _1a is relatively high value of several kilo-ohms several hundred ohms. Gradually varying waveform of the reset pulse, so it determines the stability of the PDP discharge operation, the resistance R _1a
Adjust the value of to optimize the gradient. And then pulled up FETs Q _1a is turned off, the pull-down FETs Q _LS1 enters the ON state, the scan electrodes SCN ₁ ~SCN _N → diode D
_H1 to D _HN → current flows through a path of the pull-down FETs Q _LS1, the initialization pulse ends.

In the subsequent writing period, the scan / sustain pulse generation circuits P _{1 to} P _N sequentially perform the push-pull operation while the pull-up FET Q _1a is off and the pull-down FET Q _LS1 is on, so that the scan electrodes SCN _{1 to} SCN _N. Is applied with a scanning pulse. In subsequent sustain period, the pull-up FETs Q _1a is turned off, while the pull-down FETs Q _LS1 is on, the scan / sustain pulse generating circuit P ₁ to P _N all by push-pull operation at the same time, the scanning electrodes SCN ₁ to SC
A sustain pulse is applied to N _N. In subsequent erase period, the pull-up FETs Q _1a is turned off, pull-down FET
When Q _LS1 is on, the pull-up FETs Q _{H1 to} Q _HN are on, and the pull-down FETs Q _{L1 to} Q _LN are off, and the scan electrode S
CN ₁ ~SCN _N The pull-down FETs Q _LS1, diode D _LS1, the pull-up FETs Q _H1 to Q _HN, diodes D
Via _H1 ~D _HN 0 (V) is applied.

FIG. 15 shows a conventional sustain electrode driving circuit 1.
And shows the output portion 4, and a gradually varying waveform generation circuit U _1b that operate as sustain pulse generating circuit W ₁ and the erase pulse generation circuit. Pull up FETQ sustain pulse generating circuit W ₁ is the drain of which is grounded
And _HW1, connected in parallel to the pull-up FETs Q _HW1 diode D _HW1 (usually diode D _HW1 pullup FET
Q _HW1 uses a parasitic diode) and the source is -V
Pull-down FET Q connected to the constant potential point of s (V)
Push-pull circuit consisting of _LW1 and its output is PDP
It is connected to the sustain electrodes SUS ₁ ~SUS _N. The gentle gradient waveform generation circuit U _1b includes a pull-down FET Q _1b whose source is connected to a constant potential point of −Vs (V), and a pull-down FE.
Consists of a resistor R _1b connected to the drain of TQ _1b, pull-down FETs Q _1b is maintained via a resistor R _1b electrodes SUS
_{1 to} SUS _N are connected.

Next, the operation of the conventional sustain electrode driving circuit will be described. First, in the initialization period and the write period of FIG. 12, the pull-up FETs Q _HW1 is turned on, pull-down F
ETQ _LW1 is off, and pull-down FET Q _1b is off. Therefore, the sustain electrodes SUS _{1 to} SUS _N are connected to 0 through the pull-up FET Q _HW1 and the diode D _HW1.
(V) is applied. The sustain pulse generating circuit W ₁ is in push-pull operation in the sustain period, sustain pulses are applied to the sustain electrodes SUS ₁ ~SUS _N. At the beginning of the subsequent erase period, the pull-up FET _{Q HW1} is on, the pull-down FET Q _LW1 is off, and the pull-down FE
When the pull-up FET Q _HW1 is turned off and the pull-down FET Q _1b is turned on from the state where TQ _1b is off, the sustain electrodes SUS _{1 to} SUS _N → the resistance R _1b → the pull-down FET Q _1b
→ -Vs current flows through a path of constant potential point (V), the erase pulse is applied to the sustain electrodes SUS ₁ ~SUS _N. At this time, the falling of the erase pulse is caused by the sustain electrodes SUS _{1 to} SU
S _N is the electrode stray capacitance C _SUi (i = 1~N) Total _{C SU = C SU1 + ··· +} C SUN gradually varying waveform determined by the CR time constant circuit according to the resistance R _1b of each having. Screen size is 20
In the case of a gas discharge type display device of about inches, the value of the resistor R _1b is a relatively high value of several hundred ohms to several kilo ohms. Since the gentle gradient waveform of the erase pulse determines the stability of the discharge operation of the PDP, the gradient is optimized by adjusting the value of the resistor _R1b . Then, the pull-down FET Q _1b is turned off,
When the pull-up FET _{Q HW1} changes to ON, 0 (V)
Constant potential point → pull-up FET _{Q HW1} → sustain electrode SUS ₁
Current flows through a path of ~SUS _N, erase pulse ends.

[0014]

However, when a gentle gradient waveform such as an initialization pulse or an erase pulse is applied, the number of cells to be discharged changes in accordance with the change in the number of lighting cells that have undergone write discharge or sustain discharge. Although the current at the time of application of the gentle gradient waveform fluctuates, as described above, if the gentle gradient waveform generating circuit is constituted by the CR time constant circuit having a relatively high output impedance, the gradient of the gentle gradient waveform is caused by this current variation. Was changing. Therefore, even if the gradient of the gentle gradient waveform is set so that the discharge operation range is maximized at a certain number of lighting cells,
When the number of illuminated cells changes, the gradient of the gentle gradient waveform changes, which makes it easy to generate defective cells for writing or erasing.
The discharge operation range of P was narrowed.

Further, in such a conventional PDP drive circuit, since the gentle gradient waveform generating circuit is constituted by a CR time constant circuit using the electrode floating capacitance of the PDP, the electrode floating capacitance varies from one PDP to another. In such a case, the gradient of the gentle waveform also varies, thus narrowing the discharge operation range of the PDP.

A first object of the present invention is to reduce the change in the gradient of the gentle gradient waveform even if there is a variation in the load of the gentle gradient waveform generation circuit, such as a change in the discharge current or a variation in the stray capacitance of the electrode, thereby reducing the discharge operation. An object of the present invention is to provide a PDP driving circuit having a wide range.

In such a conventional PDP drive circuit, the gentle gradient waveform generating circuit is composed of a CR time constant circuit, and the gentle gradient waveform draws a curve that becomes gentler as it approaches the saturation voltage. For this reason, a long application time is required to provide the required gradient even at the steepest point immediately after the start of the application of the gentle gradient waveform and to try to reach the saturation voltage at the leading end of the waveform. . Such a long application time hinders, for example, increasing the number of subfields per field in order to obtain higher image quality.

A second object of the present invention is to provide a drive circuit having a large degree of freedom in timing design by causing the tip of a gentle gradient waveform to completely reach the saturation voltage in a short time and suppressing the application time. is there.

[0019]

In order to solve this problem, a driving circuit of a gas discharge type display device according to the present invention has a first substrate and a second substrate which are arranged opposite to each other with a discharge space interposed therebetween. A driving circuit for driving a gas discharge display device in which a first electrode is arranged on a first substrate, and a second electrode is orthogonally opposed to the first electrode and arranged on the second substrate. 1
The apparatus is provided with a gentle gradient waveform generation circuit including a mirror integration circuit connected to the electrode or the second electrode.

A first driving circuit having a specific configuration is as follows.
An inverting amplifier element having a common terminal connected to the first electrode or the second electrode and an output terminal connected to a constant potential point; a current limiting element connected to an input terminal of the inverting amplifier element; A mirror integration circuit having a capacitor connected between the output terminal and the output terminal.

A second driving circuit having another specific configuration includes an inverting amplifier element having an output terminal connected to the first electrode or the second electrode and a common terminal connected to a constant potential point. A mirror integration circuit having a current limiting element connected to an input terminal of the inverting amplification element and a capacitor connected between the input terminal and the output terminal.

A third driving circuit, which is still another specific configuration, comprises: an inverting amplifier element having a common terminal connected to the first electrode or the second electrode and having an output terminal connected to a constant potential point; A mirror integration circuit having a current limiting element connected to an input terminal of the amplifying element and a capacitor connected between the input terminal and a constant potential point different from the constant potential point.

According to this configuration, the output impedance of the gentle gradient waveform generating circuit is reduced, and the gradient of the gentle gradient waveform is determined by the component constants of the gentle gradient waveform generating circuit. It becomes less susceptible to load fluctuation, and the change in the gradient of the gentle gradient waveform is reduced. Further, since the leading end of the gentle gradient waveform completely reaches the saturation voltage in a short time, the application time can be reduced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a driving circuit for a gas discharge type display device according to the present invention will be described below with reference to the drawings.

FIG. 9 shows a three-electrode surface discharge type PD used in the present invention.
It is a partially broken perspective view of P. As shown in FIG. 9, a scan electrode 2 group and a sustain electrode 3 group are provided on a first glass substrate 1, and these electrode groups are covered with a first dielectric layer 4, The layer is covered with a protective film 5. Then, a second glass substrate 7 is provided facing the first glass substrate 1 with the partition wall 6 interposed therebetween, and a discharge gas is filled between the first glass substrate 1 and the second glass substrate 7. A discharge space is formed. A group of data electrodes 8 is provided on a second glass substrate 7 so as to be orthogonally opposed to a group of scan electrodes 2 and a group of sustain electrodes 3. The data electrode group 8 is covered with a second dielectric layer 9, and a phosphor 10 is provided on the surface of the second dielectric layer 9.

As shown in FIG. 10, a three-electrode surface discharge type PD
P11 electrode arrangement constitutes a matrix in a column direction are arranged data electrodes DATA ₁ to Data _M of M columns, sustain electrodes of the scan electrodes SCN ₁ ~SCN _N and N rows of N rows is the row direction SUS _{1 to} SUS _N are arranged. M × N cells are formed at each intersection of these matrices. A data electrode driving circuit 12 is connected to the data electrodes DATA _{1 to} DATA _M of the PDP 11. Further, the scanning electrodes SCN ₁ ~SCN _N is connected scan electrode driving circuit 15, sustain electrode driving circuit 16 is connected to the sustain electrodes SUS ₁ ~SUS _N.

FIG. 11 is an example of a drive timing chart in the drive circuit of the gas discharge type display device of the present invention. First is applied rise in all the scanning electrodes SCN ₁ ~SCN _N voltage is + Vr In the initialization period (V) is an initialization pulse is linear gradually varying waveform, cause an address discharge one in the preceding sub-field An initialization discharge in which a discharge current flows in the direction from the scan electrode to the data electrode in the closed cell is caused.

Next, in the writing period, a predetermined data
Data electrode DATA₁~ DATA_MIs + Vw (V)
Write pulse, first scan electrode SCN₁To voltage
Is applied with a scanning pulse of -Vs (V),
Predetermined data electrode DATA ₁~ DATA_MAnd the first
Scan electrode SCN₁Write at the cell at the intersection with
Raise electricity. Continue scanning electrode SCN_Two~ SCN_Nsmell
The same operation is performed even when writing over the entire display screen.
Is performed.

In the subsequent sustain period, all sustain electrodes SUS _{1 to} SUS _N and all scan electrodes SCN _{1 to} SC _{N N}
, A sustain pulse having a voltage of -Vs (V) is applied alternately to start the sustain discharge in the cell where the write discharge has occurred, and then maintain the sustain discharge while continuing to apply the sustain pulse. I do.

[0030] In the subsequent erase period, all the sustain electrodes SUS ₁ ~SUS _N, falls the voltage at -Vs (V) by applying the erase pulse is a linear gradually varying waveform, happening of sustain discharge Erase discharge is caused in the erased cell to stop the sustain discharge.

A plurality of subfields consisting of the above writing period, sustaining period and erasing period are weighted by changing the number of sustaining pulses, and a plurality of subfields are combined to form a subfield train, which is defined as one field (16.7 ms). ,
Perform image display.

The above drive timing is different from the conventional example shown in FIG. 12 in that the gentle gradient waveforms of the initializing pulse and the erasing pulse linearly change and are saturated in a short time. That is, the time widths of the activation pulse and the erase pulse are reduced. According to experiments,
The time width of the initializing pulse and the erasing pulse each required 200 μs in the related art, but can be set to 100 μs in the present embodiment. When one field is composed of 8 subfields, the time width is 1.6 ms. The extra time can be obtained, and the extra time can be spent for improving the image quality, for example, by increasing the number of subfields or widening the write pulse width.

Hereinafter, a specific circuit configuration will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing an output portion of scan electrode drive circuit 15 in a PDP drive circuit according to Embodiment 1 of the present invention. Scan / sustain pulse generation circuits P _{1 to PN} and and a reset pulse generating circuit S _2. Data electrode DAT of gas discharge type display device 11
A _{1 to} DATA _M and sustain electrodes SUS _{1 to} SUS _N are omitted. Scan / sustain pulse generating circuit P ₁ to P _N, respectively, a pull-up FETs Q _H1 to Q _HN with a drain connected to the output of the reset pulse generating circuit S _2, the pull-up FE
A pull-down F having a drain connected to the sources of TQ _{H1 to} Q _{HN and} a source connected to a constant potential point of −Vs (V).
ETQ _L1 to Q _LN and the pull-up FETs Q _H1 to Q connected diode D between the source and the drain of the _{HN H1} to D _HN
(Usually, the diode D _H1 to D _HN pullup FETs Q _H1
To Q _HN (using a parasitic diode), and scan / sustain pulse generation circuits P _{1 to} P _N
The output of which is connected to a scanning electrode SCN ₁ ~SCN _N of PDP 11.

Initialization pulse generation circuit S_TwoThe drain
(Output terminal) connected to a constant potential point of + Vr (V)
Up FET (inverting amplification element) Q and pull-up FET
A resistor (current) with one end connected to the gate (input terminal) of Q
Limiting element) R_G2aAnd the gate and gate of the pull-up FET Q.
Capacitor C connected to the rain_F2aAnd the source
And the source of the pull-up FET Q (common
Pull-down FET Q with drain connected to
_LS2And pull-down FET Q_LS2With source and drain
Diode D connected between_LS2(Usually diode D
_LS2Is the pull-down FET Q _LS2Use the parasitic diode of
). This initialization path
Loose generator S_TwoIn the method of the present invention,
Raw circuit U_2aConsists of a Miller integrating circuit.
This is different from the conventional scan electrode driving circuit 13 shown in FIG.
Where it is.

In the above configuration, the pull-up FET Q
Although an N-type FET is used, a P-type FET can also be used if the direction of voltage application is reversed. Furthermore, the pull-up FET Q is a FET such as a bipolar transistor.
Other elements may be used.

In the above configuration, the resistor _RG2a is used as the current limiting element, but a current limiting element other than the resistor, such as a constant current element, may be used.

Next, the operation of the scan electrode driving circuit shown in FIG.
Explain the work. First, at the beginning of the initialization period in FIG.
And pull-up FET Q_H1~ Q_HNIs on, pulldown F
ETQ_L1~ Q_LNIs off, pull-up FET Q is off,
DOWN FET Q_LS2Is on. Accordingly
And scan electrode SCN₁~ SCN_NEach has a pulldown
FET Q_LS2, Diode D_LS2, Pull-up FET Q
_H1~ Q_HN, Diode D _H1~ D_HN0 (V) is marked through
Has been added. And pull down FETQ_LS2Turned off
When the pull-up FET Q changes to ON, + Vr
(V) constant potential point → pull-up FET Q → pull-up F
ETQ_H1~ Q_HN→ Scan electrode SCN₁~ SCN_NIn the path of
The current flows and the scanning electrode SCN₁~ SCN_NInitialization pulse
Applied. At this time, the rise time t of the initialization pulse
Changes the input voltage to V_IN, Gate threshold of pull-up FET Q
Value voltage to V_TThen, t = (C_F2a× Vr) / ｛(V
_IN-V _T) / R_G2a緩
You. Also, the gentle gradient waveform generation circuit U _2aThe output impedance of
Is determined by the output impedance of the pull-up FET Q.
Low value (several ohms). Therefore, initialization pal
Discharge caused by the discharge that occurs during the rise of the power waveform
Changes in current and electrode stray capacitance C_SC1~ C_SCNIs uneven
The slope of the gentle slope waveform hardly changes even if
The electric operation can be stabilized. Note that this initialization
The gentle slope waveform of Luz indicates the stability of the discharge operation of PDP11.
Because it decides, resistance R_G2aAdjust the value of to optimize the gradient
You.

Then, when the pull-up FET Q turns off and the pull-down FET Q _LS2 turns on, the scan electrode S
CN ₁ ~SCN _N → diode D _H1 to D _HN → pulldown F
Current flows through the path of ETQ _LS2 , and the initialization pulse ends.

In the subsequent writing period, the scan / sustain pulse generation circuits P _{1 to} P _N sequentially perform a push-pull operation while the pull-up FET Q is off and the pull-down FET Q _LS2 is on, so that the scan electrodes SC _{N 1 to} SC _{N N} are applied. A scanning pulse is applied. In subsequent sustain period, the pull-up FETQ is turned off, while the pull-down FETQ _LS2 is turned on, the scan / sustain pulse generating circuit P ₁ to P _N are push-pull operation at the same time, the sustain pulse to the scan electrodes SCN ₁ ~SCN _N Applied. In the subsequent erasing period, the pull-up FET Q is off, the pull-down FET Q _LS2 is on, the pull-up FETs Q _{H1 to} Q _HN are on, and the pull-down FET Q _HN is on.
ETQ _L1 to Q _LN is off, the scanning electrodes SCN ₁ to S
Pulldown The CN _N FETs Q _LS2, diode D _LS2,
0 (V) is applied via the pull-up FETs Q _{H1 to} Q _HN and the diodes D _{H1 to} D _HN .

[0040] Next Fig. 2 is a block diagram showing an output portion of the sustain electrode driving circuit in the first embodiment of the PDP driving circuit according to the present invention operates as sustain pulse generating circuit W ₁ and the erase pulse generating circuit and a gradually varying waveform generation circuit U _2b. Data electrodes DATA _{1 to} DATA _M and scan electrodes SCN of the gas discharge display device 11
_{1 ~SCN N,} etc. are omitted. Sustain pulse generation circuit W ₁
Is a pull-up FET Q _HW1 whose drain is grounded,
Diode D connected in parallel to pull-up FET _{Q HW1
HW1} (Usually, diode D _HW1 is a pull-up FET _{Q HW1}
And the source is connected to a constant potential point of -Vs (V), and the pull-up FET Q
Pulldown FET _Q with drain connected to source of _HW1
It is a push-pull circuit consisting of _LW1 and its output is P
Is connected to the sustain electrodes SUS ₁ ~SUS _N of DP11.

The gradually varying waveform generation circuit U _2b which operates as an erase pulse generator circuit, together with the sustain electrodes SUS ₁ to S connects the source (common terminal) to a constant potential point of -Vs (V)
Pulldown F connected to the US _N drain (output terminal)
Consists ET (inverting amplifying element) and Q _d, and the resistance R _G2b having one end connected to the gate (input terminal) of the pull-down FETs Q _d, and a capacitor connected C _F2b between the gate and the drain of the pull-down FETs Q _d Have been. As described above, the gentle gradient waveform generating circuit U _2b is constituted by a Miller integrating circuit, and the conventional sustain electrode driving circuit 14 shown in FIG.
Is different.

In the above configuration, the pull-down FET Q
_Although an N-type FET is used for _d , a P-type FET can be used similarly if the direction of voltage application is reversed. further,
Pull-down FETQ _d such as bipolar transistor F
Elements other than ET may be used.

In the above configuration, the resistor _RG2b is used as the current limiting element. However, a current limiting element other than the resistor, such as a constant current element, may be used.

Next, the operation of the sustain electrode driving circuit of the present invention will be described. First, at the end of the maintenance period in FIG.
Pull-up FET _{Q HW1} is ON, pull-down FET _{Q LW1}
Is off, the pull-down FETQ _d is turned off. Thus sustain electrodes SUS ₁ ~SUS _N pull-up FET
0 (V) is applied through Q _HW1 and the diode D _HW1 . In the sustain period, sustain pulse generating circuit W ₁
There was a push-pull operation, sustain pulses are applied to the sustain electrodes SUS ₁ ~SUS _N. At the beginning of the subsequent erasing period of FIG. 11, when the pull-up FET _{Q HW1} is turned on, the pull-down FET Q _{L W1} is turned off, and the pull-down FET Q _d is turned off, the pull-up FET Q _HW1 is turned off and the pull-down FET Q _d is turned on. Electrodes SUS _{1 to} S
A current flows through the path of the constant potential point of US _N → pull-down FET Q _d → −Vs (V), and an erase pulse is applied to sustain electrodes SUS _{1 to} SUS _N. Fall time t erase pulse this time, the input voltage V _IN, the gate threshold voltage of the pull-down FETs Q _d and _{V T, t = (C F2b} × Vs)
/ {(V _IN −V _T ) / R _G2b } becomes a linear gentle gradient waveform. Further, the output impedance of the gradually varying waveform generation circuit U _2b becomes a low value determined by the output impedance of the pull-down FETs Q _d. Therefore, even if there is a change in the discharge current due to the discharge that occurs during the fall of the waveform of the erase pulse or a variation in the electrode stray capacitances C _{SU1 to} C _SUN , the gradient of the gentle gradient waveform hardly changes, thus stabilizing the discharge operation. can do. The discharge operation of the PDP 11 can be stabilized by adjusting the value of the resistor _RG2b and optimizing the slope of the falling edge of the erase pulse. And then the pull-down FETs Q _d is turned off, the pull-up FETs Q _HW1 is in ON state, 0 constant potential point of (V) → pullup FETs Q _{H W1} → sustain electrodes SUS ₁ ~SUS
_The current flows in the path of _N , and the erase pulse ends.

The drive circuit of the gas discharge type display device of the present embodiment has the above-described gentle gradient waveform generating circuit, so that the output impedance of the gentle gradient waveform generating circuit is reduced and the gentle gradient waveform generating circuit is provided. The gradient of the gentle gradient waveform is determined by the component constants. Thus, even if there is a load change such as a change in the discharge current or a variation in the electrode stray capacitance, the change in the gradient of the gentle waveform is reduced, and the discharge operation range of the PDP can be widened. In addition, since the gradient of the gentle gradient waveform becomes a substantially constant voltage change amount per unit time and becomes linear, and the leading end of the waveform reaches the saturation voltage completely in a short time, the application time can be suppressed,
That time can be spent on improving the image quality, such as by increasing the number of subfields or widening the write pulse width. Therefore, the degree of freedom in designing the timing of the drive circuit can be increased.

(Embodiment 2) Next, FIG. 3 is a circuit diagram showing only a gentle gradient waveform generation circuit portion of a scan electrode drive circuit in a PDP drive circuit according to Embodiment 2 of the present invention. The configuration is the same as in the first embodiment. ₃ has a common terminal (source) connected to the electrode of the PDP 11 and a constant potential point V _B1.
A pull-up FET (inverting amplifying element) Q ₃ to (V) to the output terminal (drain) is connected, the resistance of which one end to the input terminal of the pull-up FETs Q ₃ (gate) is connected (current limiting element) and R _G3 And a capacitor C _F3 having one end connected to the input terminal (gate) of the pull-up FET Q ₃ and the other end connected to a constant potential point V _B2 (V) different from the constant potential point V _B1 (V). This is a Miller integrating circuit. Here, the pull-up FETs Q ₃ is N-type, + Vr to V _B1 (V)
0 (V) is applied to (V) and V _B2 (V). With this configuration, the initialization pulse shown in FIG. 11 can be generated.

Further, the pull-up FET Q ₃ in the gentle gradient waveform generating circuit U ₃ is replaced with a P-type FET,
By applying -Vs (V) to _B1 (V) and 0 (V) to _VB2 (V), a gentle gradient waveform generation circuit used for the sustain electrode driving circuit can be formed. Can occur.

With the above configuration, the same effects as in the first embodiment can be obtained. In the first embodiment, N
A gentle slope waveform generating circuit that generates a rising waveform and a falling waveform can be configured by using either one of the P-type FET and the P-type FET. A gentle-gradient waveform generation circuit that generates a falling waveform with a waveform and a P-type FET can be configured.

The pull-up FET Q ₃ (which becomes a pull-down FET when used in a sustain electrode driving circuit) may be a device other than the FET, such as a bipolar transistor.

In the above configuration, the resistor _RG3 is used as the current limiting element. However, a current limiting element other than the resistor, such as a constant current element, may be used.

(Embodiment 3) Next, FIGS. 4 (a) to 4 (d)
FIG. 10 is a circuit diagram showing only a gentle gradient waveform generating circuit portion of a scan electrode driving circuit according to a third embodiment of the PDP driving circuit according to the present invention, and the other configuration is the same as that of the first or second embodiment.

The point that the gentle gradient waveform generating circuit U ₄ of FIG. 4A is different from the gentle gradient waveform generating circuit U _{2a of} FIG.
Between the gate and the drain of the pull-up FETs Q _4, is that of providing a material obtained by serially connecting the capacitor C _F4 and resistors R _F4. FIG 4 (b) of gradually varying waveform generation circuit U ₅ is gradually varying waveform generation circuit U ₃ and the circuit configuration on different points in FIG. 3,
Between the pull-up FETs Q ₅ of the gate and the constant potential point V _B2 (V), is that of providing those connected in series with the capacitor C _F5 and resistor R _F5. Figure 4 (c) of gradually varying waveform generation circuit U ₆ is gradually varying waveform generation circuit U _2a and circuitry on different points 1, between the gate and drain of the pull-up FETs Q _6, capacitor C _F6 and constant That is, a voltage diode ZD _F6 connected in series is provided. Figure 4 (d) of gradually varying waveform generation circuit U ₇ is gradually varying waveform generation circuit U ₃ and the circuit configuration on different points in Figure 3, between the pull-up FETs Q ₇ of the gate and the constant potential point V _B2 (V) _{Another point} is that the capacitor C _F7 and the constant voltage diode ZD _F7 are replaced with a capacitor connected in series. Gentle gradient waveform generation circuits U ₄ , U ₅ , U ₆ and U ₇
5 (a) is shown by a solid line in FIG.

Further, the gentle gradient waveform generating circuit U ₄ or U ₆ can be used as a gentle gradient waveform generating circuit of the sustain electrode driving circuit. The gentle falling waveform that occurs in this case is shown by the solid line in FIG. As described above, in the present embodiment, the offset voltage V _F (V) can be provided in the gentle gradient waveform. If the value of the offset voltage V _F is provided with a resistor R _F (R _F4 or R _F5), the input voltage V _IN, FETs Q
(Q ₄ or Q ₅₎ the gate threshold voltage V _T of the gate resistor and R _G, the value calculated by _{V F = R F × (V} IN -V T) / R G. In addition, the constant voltage diode ZD
When providing the _F (ZD _F6 or ZD _F7), the value of the offset voltage V _F becomes the Zener voltage value of the constant voltage diode ZD _F. PDP value of the V _F is is supplied, gradually varying waveform
Is set to a value slightly smaller than the discharge starting voltage of The waveforms indicated by the dotted lines in FIGS. 5A and 5B are shown in FIGS.
Gradually varying waveform generation circuit U _2a shown in, U _2b, a gradually varying waveform generated by U _3, requires the application period t _1. On the other hand, when an offset voltage of V _F is provided, the voltage change amount of the gentle gradient waveform is reduced by V _F, so that the application time is t ₂
Thus, the application time can be made shorter than in the case of the gentle gradient waveform generation circuits U _2a , U _2b , and U _3.
The degree of freedom in designing the timing of the driving circuit can be increased more than in the case of (1).

(Embodiment 4) Next, FIGS. 6 (a) and 6 (b)
FIG. 10 is a circuit diagram showing only a gentle gradient waveform generating circuit portion of a scan electrode driving circuit according to a fourth embodiment of the PDP driving circuit according to the present invention, and the other configuration is the same as that of the first or second embodiment. The gentle waveform generator U ₈ shown in FIG.
There gradually varying waveform generation circuit U _2a and the circuit configuration on a different point, the capacitor C _F8, together with those connected in parallel and a diode D _S8 is rectifying element and the resistor R _S8 is a current limiting element connected in series, the current The rectifying element D _G8 is connected in parallel to the limiting element R _G8 . FIG 6 (b) of gradually varying waveform generation circuit U ₉ is gradually varying waveform generation circuit U ₃ and the circuit configuration on a different point, the capacitor C _F9, resistor R _S9 is a current limiting element
And a diode D _S9 , which is a rectifying element, connected in parallel, and a rectifying element D _G9 is connected in parallel to the current limiting element R _G9 .

In the gentle slope waveform generating circuits U ₈ and U ₉ , the discharge current of the capacitors C _F8 and C _F9 when the slow slope waveform is generated flows through the diodes D _S8 and D _S9 , and the voltage is rapidly restored after the slow slope waveform is generated. In this case, the peak value of the charging current of the capacitors C _F8 and C _F9 is suppressed by the resistors R _S8 and R _S9 , and the rise of the gate voltage of the pull-up FETs Q ₈ and Q ₉ is suppressed by the diodes D _G8 and D _G9. Can be. Therefore,
Pull-up F at the time of sudden voltage return after generation of gentle gradient waveform
ETQ _8, there is no pull-up of the gate voltage of Q _9, it is possible to prevent the heating and destruction of the pull-up FETQ _8, Q _9.

[0056] By a similar circuit configuration as gradually varying waveform generation circuit U _8, it may be a gradually varying waveform generation circuit of the sustain electrode driving circuit. Further, the gentle slope waveform generating circuit U ₉ can be used as a gentle slope waveform generating circuit of the sustain electrode drive circuit by making the N-type FET Q ₉ a P-type. In this case, the same effect as described above can be obtained.

(Embodiment 5) Next, FIG.
Embodiment 5 of the driving circuit for the gas discharge type display device
Of the sustain electrode drive circuit
FIG. 3 is a circuit diagram showing the same components as in the first embodiment.
The same. 7 (a), a gentle gradient waveform generation circuit U _TenFigure 2
Gentle slope waveform generation circuit U_2bThe difference in circuit configuration from the
DOWN FET Q_TenDrain and capacitor C_F10With
Connection point and sustain pulse generation circuit W₁Between the output of
Mode (rectifying element) D_A10Is provided.

[0058] By the configuration shown in FIG. 7 (a), the capacitor C _F10 is discharged when the gradually varying waveform generating circuit U ₁₀ outputs a gradually varying waveform, subsequent gradually varying waveform at the end of the voltage recovery , The capacitor C _F10 is charged, but the sustain pulse generation circuit W _1, which is a push-pull circuit wired or connected, has a rectifying element D _A10 even after the push-pull operation, so that the discharge current of the capacitor C _F10 is reduced. Is prevented, charging and discharging of the capacitor C _F10 are not performed, and power consumption of the drive circuit can be reduced.

A gentle gradient wave whose rising is gentle
Push-pull circuit W_TwoIs wired or connected
7B and FIG. 7C when the operation is continued.
FIG. 7B shows a gentle gradient waveform generation circuit U.₁₁Is the slow gradient wave in Fig. 1.
Shape generation circuit U_2aThe difference with the circuit configuration is that the pull-up F
ETQ₁₁Diode D at the source of_A11That you have
It is. FIG. 7C shows a gentle gradient waveform generation circuit U.₁₂Of FIG.
Gentle waveform generator U _ThreeThe difference with the circuit configuration is that the pull
Up FET Q₁₂Diode D at the source of_A12With
It is that you are.

(Embodiment 6) Next, FIGS. 8A and 8B
Is an embodiment of the driving circuit of the gas discharge type display device of the present invention.
Slow gradient waveform generation circuit section of scan electrode drive circuit in state 6
FIG. 3 is a circuit diagram showing only the components,
Same as 1 or 2. Generation of the gentle gradient waveform in FIG.
Circuit U₁₃Is a gentle gradient waveform generation circuit U_2aAnd circuit configuration
8 and the gentle gradient waveform generation circuit U shown in FIG.₁₄Is gentle
Waveform generator U_ThreeThe difference between the circuit configuration and
Flow restricting element) R_G13, R_G14One end of the other resistor (current limit
Element) R _I13, R_I14Terminal and constant voltage element ZD_G13, ZD
_G14And one end of the constant voltage element ZD_G13,
ZD_G14The other end of FETQ₁₃, Q₁₄Connected to the common terminal of
That is.

With the configuration shown in FIG. 8, the fluctuation of the input voltage V _IN is stabilized by the constant voltage elements ZD _G13 and ZD _G14 . Therefore, even if the input voltage V _IN fluctuates, the gradient of the gentle gradient waveform almost changes. No longer. The resistors R _I13 and R _I14 protect the constant voltage elements ZD _G13 and ZD _G14 from overcurrent.

[0062] By a similar circuit configuration as gradually varying waveform generation circuit U _13, it may be a gradually varying waveform generation circuit of the sustain electrode driving circuit. Also, gradually varying waveform generation circuit U ₁₄ depending on the circuit configuration in which the FETs Q ₁₄ of N-type in P-type, may be a gradually varying waveform generation circuit of the sustain electrode driving circuit. In this case, the same effect as described above can be obtained.

In the above-described six embodiments, an example is described in which the gentle slope waveform generation circuit of the present invention is used for the initialization pulse generation circuit and the erase pulse generation circuit. Also in the drive pulse generation circuit of the drive circuit of the device, the gentle gradient waveform generation circuit described in the above six embodiments can be used.

Further, in the above-mentioned six embodiments, the drive circuit of the three-electrode surface discharge type gas discharge type display device is described as an example, but the two-electrode opposed discharge type and other gas discharge type display devices are described. In the drive circuit described above, the gentle gradient waveform generation circuit described in the above six embodiments can be used.

[0065]

As described above, according to the present invention, since the output voltage waveform of the gentle gradient waveform generation circuit comprising the Miller integration circuit is applied to the electrodes of the gas discharge type display device, the discharge current is reduced. Even if there is a load variation such as a variation in the stray capacitance of the electrode or a variation in the stray capacitance of the electrode, the variation in the gradient of the gentle gradient waveform output from the drive circuit is reduced, and as a result, the discharge operation range of the gas discharge type display device can be widened. . Further, since the leading end of the gentle gradient waveform output from the drive circuit can completely reach the saturation voltage in a short time and the application time can be suppressed, the degree of freedom in designing the timing of the drive circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a scan electrode drive circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a sustain electrode driving circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a gentle gradient waveform generation circuit according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a gentle slope waveform generating circuit according to a third embodiment of the present invention;

FIG. 5 is an output waveform diagram of the gentle gradient waveform generation circuit of FIG. 4;

FIG. 6 is a block diagram showing a gentle gradient waveform generation circuit according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a gentle gradient waveform generation circuit according to a fifth embodiment of the present invention;

FIG. 8 is a block diagram showing a gentle gradient waveform generation circuit according to a sixth embodiment of the present invention.

FIG. 9 is a partially broken perspective view of a gas discharge type display device.

FIG. 10 is a configuration diagram of an entire driving circuit of the gas discharge display device of the present invention.

FIG. 11 is a drive timing diagram of the gas discharge type display device according to the present invention.

FIG. 12 is a configuration diagram of an entire driving circuit of a conventional gas discharge type display device.

FIG. 13 is a drive timing chart of a gas discharge type display device in a conventional example.

FIG. 14 is a block diagram showing a scan electrode drive circuit of a conventional gas discharge type display device.

FIG. 15 is a block diagram showing a sustain electrode drive circuit of a conventional gas discharge type display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st glass substrate 2 scanning electrode 3 sustaining electrode 4 1st dielectric layer 5 protective film layer 6 partition 7 2nd glass substrate 8 data electrode 9 2nd dielectric layer 10 fluorescent substance 11 gas discharge display 13, 15 scan electrode drive circuit 14, 16 sustain electrode drive circuit

Claims (9)

[Claims] A first electrode disposed on the first substrate and disposed opposite to each other with a discharge space interposed therebetween, a first electrode arranged on the first substrate, and a second electrode orthogonally opposed to the first electrode. Is the second
A drive circuit for driving a gas discharge type display device arranged on a substrate, the gas discharge type display including a gentle gradient waveform generation circuit comprising a Miller integration circuit connected to the first electrode or the second electrode. The drive circuit of the device. 2. An inverting amplifying element having a common terminal connected to the first electrode or the second electrode and having an output terminal connected to a constant potential point, and a current limiting element connected to an input terminal of the inverting amplifying element. 2. A driving circuit for a gas discharge type display device according to claim 1, further comprising a Miller integrating circuit having a capacitor connected between said input terminal and said output terminal. 3. An inverting amplifying element having an output terminal connected to the first electrode or the second electrode and having a common terminal connected to a constant potential point, and a current limiting element connected to an input terminal of the inverting amplifying element. 2. A driving circuit for a gas discharge type display device according to claim 1, further comprising a Miller integrating circuit having a capacitor connected between said input terminal and said output terminal. 4. An inverting amplifier element having a common terminal connected to the first electrode or the second electrode and having an output terminal connected to a constant potential point, and a current limiting element connected to an input terminal of the inverting amplifier element. 2. The driving circuit for a gas discharge display device according to claim 1, further comprising a Miller integrating circuit having a capacitor connected between the constant potential point different from the constant potential point and the input terminal. 5. The drive circuit for a gas discharge type display device according to claim 2, wherein an element in which a capacitor and a current limiting element or a constant voltage element are connected in series is provided instead of the capacitor. 6. In place of a capacitor, an element in which a capacitor is connected in series to an element in which a current limiting element and a rectifying element are connected in parallel is provided, and a rectifying element connected in parallel to a current limiting element connected to an input terminal is provided. 5. A driving circuit for a gas discharge type display device according to claim 2, wherein the driving circuit is provided. 7. The driving circuit for a gas discharge type display device according to claim 2, wherein a rectifier is connected to a common terminal of the inverting amplifier. 8. The driving circuit for a gas discharge type display device according to claim 3, wherein a rectifying element is connected to a connection point between the output terminal and the capacitor. 9. One end of another current limiting element and one end of a constant voltage element are connected to the other end of the current limiting element having one end connected to the input terminal, and the other end of the constant voltage element is connected to a common terminal. 5. A driving circuit for a gas discharge type display device according to claim 2, wherein said driving circuit is connected to a driving circuit.