KR100533731B1 - Method and Apparatus of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can sufficiently secure a driving time for displaying an image.

A method of driving a plasma display panel of the present invention comprises the steps of: setting a blank period between frame periods each time-divided into a plurality of subfields;

Applying a positive ramp pulse to the scan electrodes during the blank period.

Description

Driving method and driving device of plasma display panel {Method and Apparatus of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a driving apparatus for a plasma display panel. More particularly, the present invention relates to a method and a driving apparatus for a plasma display panel to ensure a sufficient driving time for displaying an image.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a PDP arranged in a matrix form on a panel includes scan electrodes Y and sustain electrodes Z formed on the upper substrate 10, and addresses formed on the lower substrate 18. An electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 is a view showing a driving apparatus of a conventional plasma display panel.

Referring to FIG. 3, a conventional PDP driving apparatus includes an address driver 32 for driving address electrodes X1 to Xm provided in the panel 30, and scan electrodes Y1 to X1 provided in the panel 30. A driving voltage using the scan driver 34 for driving Yn, the sustain driver 36 for driving the sustain electrodes Z1 to Zn provided in the panel 30, and the drivers 32, 34, 36. And a timing controller 38 for supplying control signals SCS1 to SCS3 to the driving units 32, 34, and 36.

The driving voltage generator 40 generates various driving voltages so as to generate driving waveforms as shown in FIG. 4 and supplies them to the address driver 32, the scan driver 34, and the sustain driver 36. For example, the driving voltage generator 40 generates voltages such as Vsetup, -Vw, Vr, and Vs to supply the scan driver 34, and generates the Vs voltage to supply the sustain driver 36. The driving voltage generator 40 generates a voltage of Va and supplies the voltage to the address driver 32.

The timing controller 38 generates various switching control signals and supplies them to the address driver 32, the scan driver 34, and the sustain driver 36 so that a driving waveform as shown in FIG. 4 can be generated. For example, the timing controller 38 generates a first switching control signal SCS1 and supplies it to the scan driver 34, generates a second switching control signal SCS2, and supplies it to the sustain driver 36. The timing controller 38 supplies the third switching control signal SCS3 and the dock clock DCLK to the address driver 32.

The address driver 32 controls the image data data supplied from the outside while being controlled by the dot clock DCLK and the third switching control signal SCS3 supplied from the timing controller 38 and the address electrodes X1 to Xm. To supply.

The scan driver 34 controls the reset pulse, the scan pulse, and the sustain pulse sus to the scan electrodes Y1 to Ym while being controlled by the first switching control signal SCS1 supplied from the timing controller 38. Supply.

The sustain driver 36 controls the positive voltage Vs, the sustain pulse sus and the erase pulse Ers by controlling the second switching control signal SCS2 supplied from the timing controller 38. To Zm).

The driving waveform supplied to the electrodes will be described in detail with reference to FIG. 4. First, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y during the setup period during the initialization period. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In such a conventional PDP, a blank period is included between the frame and the frame. This blank period is determined in time according to the data applied to the frame. In other words, since the frame period varies depending on the data applied to the frame, the time of the blank period is also set in various ways. For example, the time of the blank period is set in various ways corresponding to the frame period as shown in Figs. 5A to 5C.

On the other hand, the driving waveform is not applied in the blank period in the conventional PDP driving method. In other words, the blank period was wasted with unnecessary time unnecessary for driving. In fact, in PDP, sufficient time necessary for driving is required to express sufficient brightness, but there is a problem in that sufficient driving time cannot be secured due to time wasted by the blank period.

Accordingly, it is an object of the present invention to provide a driving method and a driving apparatus for a plasma display panel which can ensure a sufficient driving time for displaying an image.

In order to achieve the above object, a method of driving a plasma display panel according to the present invention comprises the steps of: setting a blank period between frame periods each time-divided into a plurality of subfields; Applying a positive ramp pulse to the scan electrodes during the blank period.

The remaining subfields excluding the first subfield included in the frame include applying a rising ramp waveform to the scan electrodes in the setup period, applying a falling ramp waveform to the scan electrodes in the setdown period, and during the address period. In addition to applying scan pulses to the scan electrodes to select cells to be turned on, data pulses are applied to the address electrodes, and alternately applying sustain pulses to the scan electrodes and sustain electrodes during the sustain period. Include.

The first subfield includes applying a falling ramp waveform to the scan electrodes in a set down period, applying a scan pulse to the scan electrodes to select cells to be turned on during the address period, and applying a data pulse to the address electrodes. And applying a sustain pulse alternately to the scan electrodes and sustain electrodes in the sustain period.

The positive lamp pulse is applied to the scan electrodes.

The peak voltage value of the positive ramp pulse is set equal to the peak voltage value of the rising ramp waveform.

The rise time in which the positive ramp pulse rises to the peak voltage value is set equal to the rise time in which the rise lamp waveform rises to the peak voltage.

The rise time in which the positive ramp pulse rises to the peak voltage value is set longer than the rise time in which the rise lamp waveform rises to the peak voltage.

The driving apparatus of the plasma display panel of the present invention includes a scan driver for applying a driving waveform to the scan electrodes; A sustain driver for applying a driving waveform to the sustain electrodes; An address driver for applying a driving waveform to the address electrodes; The blank driving waveform may be applied from the scan driver to the scan electrodes during the blank period between the frame and the frame while supplying the first control signals so that the scan driver, the sustain driver and the address driver may apply the driving waveform during the subfield period. And a timing controller for supplying a second control signal.

The scan driver applies a positive lamp pulse to the scan electrodes by a second control signal.

The positive ramp pulse is a waveform that rises to a peak voltage at a predetermined slope and maintains the elevated peak voltage for a predetermined time.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 7.

6 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 6, an apparatus for driving a PDP according to an embodiment of the present invention includes an address driver 52 for driving address electrodes X1 to Xm provided in the panel 50, and a scan provided in the panel 50. A scan driver 54 for driving the electrodes Y1 to Yn, a sustain driver 56 for driving the sustain electrodes Z1 to Zn provided in the panel 50, and drivers 52, 54, And a timing controller 58 for supplying control signals SCS1 to SCS4 to the driving units 52, 54, and 56.

The driving voltage generator 60 generates various driving voltages so as to generate driving waveforms as shown in FIG. 7 and supplies them to the address driver 52, the scan driver 54, and the sustain driver 56. For example, the driving voltage generation unit 60 generates voltages such as Vsetup, -Vw, Vr, and Vs to supply the scan driver 54, and generates Vs voltage to supply the sustain driver 56. The driving voltage generator 60 generates a voltage of Va and supplies it to the address driver 52.

The timing controller 58 generates various switching control signals and supplies them to the address driver 52, the scan driver 54, and the sustain driver 56 so that a driving waveform as shown in FIG. 7 can be generated. That is, the timing controller 58 generates and supplies the first switching control signal SCS1 and the fourth switching control signal SCS4 to the scan driver 54, generates the second switching control signal SCS2, and maintains the driving driver. Supply to (56). The timing controller 58 supplies the third switching control signal SCS3 and the dot clock DCLK to the address driver 52.

The address driver 52 supplies the image data supplied from the outside to the address electrodes X1 to Xm while being controlled by the dot clock DCLK and the third switching control signal SCS3 supplied from the timing controller 58. . Here, the address driver 52 is controlled by the third switching control signal SCS3 to supply data (ie, a video signal) for each address period of the subfield.

The sustain driver 56 is controlled by the second switching control signal SCS2 supplied from the timing controller 58 while maintaining the positive voltage in the setdown period and the address period of the subfield, the sustain pulse and the sustain pulse during the sustain period. (erase) is supplied to the sustain electrodes Z1 to Zm.

The scan driver 54 is controlled by the first switching control signal SCS1 supplied from the timing controller 58 and reset pulses (setup waveforms) during the setup, set down, address and sustain periods of the remaining subfields except the first subfield. Setdown waveform), a scan pulse and a sustain pulse su are supplied to the scan electrodes Y1 to Ym. The scan driver 54 is controlled by the first switching control signal SCS1 supplied from the timing controller 58 and reset pulses (set down waveforms) and scan pulses (scan) during the set down, address and sustain periods of the first subfield. ) And a sustain pulse su are supplied to the scan electrodes Y1 to Ym. In addition, the scan driver 54 supplies the lamp pulses (Ramp-blank) to the scan electrodes (Y1 to Ym) during the blank period while being controlled by the fourth switching control signal (SCS4) supplied from the timing controller (58). .

The driving waveform supplied to the electrodes will be described in detail with reference to FIG. 7. The remaining subfields except the first subfield included in one frame are driven by being divided into a setup period, a setdown period, an address period, and a sustain period.

First, during the setup period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y. This rising ramp waveform (Ramp-up) generates wall charges in the cells of the full screen. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing wall charges requiring address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In fact, the remaining subfields except for the first subfield included in one frame repeat the above-described process to display an image corresponding to the gray scale.

In the blank period, a positive ramp pulse (blank-blank) is applied to the scan electrodes (Y). The ramp ramp of the positive polarity gradually rises to the V setup voltage (the same voltage as the peak voltage of the rising ramp waveform) and maintains the increased voltage for a predetermined time. When a ramp-blank is applied in the blank period, wall charges are generated in the cells of the full screen.

Here, the rising period T2 of the positive ramp pulse (blank-blank) applied in the blank period is set equal to or longer than the rising period T1 of the rising ramp waveform Ramp-up applied in the setup period. (I.e., T2 ≥ T1) If the rising period of the positive ramp-blank is set long, a weak discharge is generated in the cells, thereby minimizing the amount of light emitted to the outside. Therefore, contrast can be improved.

Meanwhile, the first subfield of one frame positioned after the blank period is driven by being divided into a set down period, an address period, and a sustain period. That is, since the wall charges are formed in the cells by the ramp-blank applied in the blank period, the setup period can be omitted in the first subfield, thereby securing more driving time than before. Since the driving waveform applied to the other first subfield period is set to be the same as the other subfields except for the first subfield, detailed description thereof will be omitted.

As described above, according to the driving method and driving apparatus of the plasma display panel according to the present invention, the ramp ramp waveform is applied in the first subfield because the wall charge is formed in the cells by applying the positive lamp pulse during the blank period. It is possible to omit, thereby securing more driving time for displaying an image. In addition, in the present invention, the rise time of the positive lamp pulse applied in the blank period can be set sufficiently long to improve the contrast.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating an example of a luminance weight of a plasma display panel.

3 is a view showing a driving apparatus of a conventional plasma display panel.

4 is a waveform diagram showing a driving waveform applied to a subfield period of a conventional plasma display panel.

5A to 5C are diagrams showing blank periods that change in response to data.

6 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention;

FIG. 7 is a waveform diagram showing driving waveforms applied to a subfield period and a blank period according to an embodiment of the present invention; FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

30,50 Panel 32,52 Address driver

34,54: scan driver 36,56: sustain drive

38,58: timing controller 40,60: drive voltage generator

Claims (10)

In the driving method of a plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, Setting a blank period between frame periods each time-divided into a plurality of subfields; And applying a positive lamp pulse to the scan electrodes during the blank period. The method of claim 1, The remaining subfields except for the first subfield included in the frame Applying a rising ramp waveform to the scan electrodes in the setup period; Applying a falling ramp waveform to the scan electrodes in a set down period; Applying a data pulse to address electrodes as well as applying a scan pulse to the scan electrodes to select cells to be turned on during an address period; And applying sustain pulses alternately to the scan electrodes and sustain electrodes in a sustain period. The method of claim 2, The first subfield is Applying a falling ramp waveform to the scan electrodes in a set down period; Applying a scan pulse to the scan electrodes and applying a data pulse to the address electrodes to select cells to be turned on during an address period; And applying sustain pulses alternately to the scan electrodes and sustain electrodes in a sustain period. The method of claim 2, And the positive lamp pulse is applied to the scan electrodes. The method of claim 2, And the peak voltage value of the positive ramp pulse is set equal to the peak voltage value of the rising ramp waveform. The method of claim 5, And a rise time at which the positive ramp pulse rises to a peak voltage value is set equal to a rise time at which the rise lamp waveform rises to a peak voltage. The method of claim 5, And a rise time at which the positive lamp pulse rises to a peak voltage value is set longer than a rise time at which the rise lamp waveform rises to a peak voltage. A scan driver for applying a driving waveform to the scan electrodes; A sustain driver for applying a driving waveform to the sustain electrodes; An address driver for applying a driving waveform to the address electrodes; The blank driving waveform is supplied from the scan driver to the scan electrodes during the blank period between the frame and the frame by supplying first control signals so that the scan driver, the sustain driver and the address driver can apply the driving waveform during the subfield period. And a timing controller for supplying a second control signal so that the second control signal can be applied to the plasma display panel. The method of claim 8, And the scan driver applies positive ramp pulses to the scan electrodes in response to the second control signal. The method of claim 9, Wherein the positive ramp pulse is a waveform which rises to a peak voltage at a predetermined slope and maintains the elevated peak voltage for a predetermined time.