KR101042993B1 - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to improve image quality by improving expression in low gray scale region expression.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a waveform diagram supplied to each electrode in the first to second subfields of FIG.

4A to 4D are model views of discharges occurring in the first subfield of FIG. 3.

FIG. 5 is a diagram of a decimal point gray scale representation method using the first subfield of FIG. 3; FIG.

6 is a driving waveform diagram of a plasma display panel showing decimal point gray scale expression;

FIG. 7 is a diagram of a decimal point gray scale representation method using the first subfield of FIG. 6; FIG.

8 is a waveform diagram illustrating a gray scale expression method of a plasma display panel of the present invention.

FIG. 9 is a model diagram of discharges occurring in the first subfield of FIG. 8. FIG.

FIG. 10 is a diagram illustrating a decimal point gray scale representation method using the first subfield of FIG. 8; FIG.                 

11 is a diagram of a decimal point gradation representation method using the gradation representation method of the plasma display panel of the present invention;

FIG. 12 is a diagram of a driving circuit for supplying a voltage to each subfield of FIG. 8; FIG.

<Explanation of symbols for the main parts of the drawings>

10: upper substrate 14: upper dielectric layer

16: protective film 18: lower substrate

20X: address electrode 22: lower dielectric layer

24: partition 26: phosphor layer

30Y: scan / sustain electrode 30Z: common sustain electrode

60: timing controller 61: data driver

62: scan driver 63: sustain driver

64: drive voltage generator

The present invention relates to a display device, and more particularly, to a driving method of a plasma display panel.

In general, a plasma display panel (hereinafter referred to as "PDP") emits phosphors by 147 nm ultraviolet rays generated during discharge of an inert gas such as He + Xe, Ne + Xe or He + Ne + Xe. By doing so, an image including characters or graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view illustrating a discharge cell structure of a general plasma display panel.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. Each of the scan / sustain electrode 30Y and the common sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one edge of the transparent electrode. And (13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe or He + Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields SF having different emission counts in order to realize gray levels of an image. The subfield SF is divided into an sustain period for implementing gradation according to an address period for selecting a discharge cell and the number of discharges. Here, an erase period for erasing the sustain discharge is added after the sustain period in each subfield SF. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges are 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased in proportion.

3 is a waveform diagram illustrating driving waveforms supplied during the first to second subfields SF1 and SF2 included in one frame.

Referring to FIG. 3, each of the subfields SF1 and SF2 includes a reset period, an address period, and a sustain period. The reset period is driven by being divided into a setup period and a setdown period.

In the setup period, the setup voltage RPU rising in the form of a ramp wave is supplied to the scan / sustain electrodes 30Y so that the discharge cells of the entire screen cause a uniform setup discharge. In the set-down period t0, the set-down voltage RPD, which descends in the form of a ramp wave, is supplied to the scan / sustain electrodes 30Y to erase the transient wall charges among the wall charges formed during the setup period. After the set-up period and the set-down period, wall charges necessary for the address discharge remain uniformly in all the discharge cells.

In the address period, the scan voltage scn is sequentially supplied to the scan / sustain electrodes 30Y in units of one horizontal period. During the address period, the data voltage data synchronized with the scan voltage scn is supplied to the address electrode 20X. At this time, in the discharge cells supplied with the scan voltage scn and the data voltage data, an address discharge t1 is generated to form wall charges necessary for sustain discharge.

On the other hand, the address discharge generated in the address period is divided into the surface discharge (Y-Z) and the counter discharge (X-Y) as shown in Figs. 4A (t0) to 4C (t2). In detail, first, negative wall charges are formed in the scan / sustain electrode 30Y during the reset period, and positive wall charges are formed in the common sustain electrode 30Z and the address electrode 20X, as shown in FIG. 4A (to). Is formed. Thereafter, as shown in FIG. 4B (t1), the positive data voltage data is supplied to the address electrode 20X, and the negative scan voltage scn is supplied to the scan / sustain electrode 30Y.

Here, the negative scan voltage scn supplied to the scan / sustain electrode 30Y is combined with the negative wall charge and voltage value formed on the scan / sustain electrode 30Y during the reset period. The positive data voltage data supplied to the address electrode 20X is combined with the positive wall charges formed on the address electrode 20X and the voltage value during the reset period. At this time, a high voltage difference is generated between the scan / sustain electrode 30Y and the address electrode 20X, so that an opposite discharge XY is generated between the scan / sustain electrode 30Y and the address electrode 20X as shown in FIG. 4B (t1). . Further, since the scan / sustain electrode 30Y has a high negative potential due to the scan voltage scn and the negative wall charge, the common sustain electrode 30Z to which the positive DC voltage is supplied as shown in FIG. 4C (t2). ) And surface discharge (YZ).

In this way, positive wall charges are formed on the scan / sustain electrode 30Y in the discharge cells in which the counter discharge XY and the surface discharge YZ are generated during the address period, that is, the discharge cells selected in the address period, as shown in FIG. 4C. The positive sustain voltage is applied to the common sustain electrode 30Z to form negative wall charges. Further, negative wall charges are formed on the address electrode 20X.

In the sustain period t3, the sustain pulse su is alternately supplied to the scan / sustain electrode 30Y and the common sustain electrode 30Z. Here, the number of sustain pulses sused to the scan / sustain electrode 30Y and the common sustain electrode 30Z is determined corresponding to the luminance weight. For example, if one sustain pulse sus has a luminance weight of "1", only one sustain pulse sus is supplied in the sustain period of the first subfield SF1 expressing the luminance weight of "1". do. Then, two sustain pulses sus are supplied in the sustain period of the second subfield SF1 expressing the luminance weighting value of " 2 ". In practice, the number of sustain pulses sused in the sustain period of each subfield SF is set in various ways in response to the luminance weighting value.

On the other hand, during the sustain period, the first sustain pulse sus is supplied to the scan / sustain electrode 30Y. When the sustain pulse su is supplied to the scan / sustain electrode 30Y, as shown in FIG. 4D (t3), the positive wall charges formed in the address period and the voltage values of the sustain pulse su are combined in the discharge cells selected in the address period. Sustain discharge occurs.

However, in the PDP driving method of FIG. 3 as described above, there is a problem in that decimal point gradations of "1" or less cannot be expressed. In fact, in order to improve the image quality in the PDP, the decimal point luminance must be expressed. Halftone processing is used to express the decimal point gray scale.

For example, as illustrated in FIG. 5, a brightness of 0.25 is expressed on average by turning on one pixel based on four pixels in the case of decimal gray scale expression, that is, 0.25 gray level. Here, the turn-on pixel has a luminance weight of "1". However, such halftone processing is perceived as a certain pattern of noise by the viewer because of the way the decimal point is expressed on average. Therefore, in order to solve this problem, the PDP driving waveform shown in FIG. 6 has been proposed.

6 is a diagram illustrating a PDP driving waveform for decimal point gray scale expression.

Referring to FIG. 6, in the PDP driving waveform of FIG. 6, the first subfield SF1 is used as a gray level for representing a decimal point. To this end, the first subfield SF1 includes only a reset period and an address period.

In detail, during the reset period of the first subfield SF1, the setup voltage RPU and the setdown voltage RPD are sequentially supplied to form uniform wall charges in the discharge cells. In the address period of the first subfield SF1, a discharge cell for which a decimal point gray scale is to be expressed is selected. That is, in the address period of the first subfield SF1, the data voltage data is supplied to the discharge cells expressing the decimal point gray scale to cause address discharge (surface discharge + counter discharge). After this address period, the sustain pulse sus is not supplied to the scan / sustain electrode 30Y and the common sustain electrode 30Z. That is, only address discharge occurs in the address period, and then the reset period of the second subfield SF2 is positioned.

In the PDP driving waveform of FIG. 6, the decimal point gray scale is expressed using the light generated by the address discharge (surface discharge + counter discharge). In other words, in the PDP driving waveform shown in FIG. 6, light generated by the address discharge is used to express a gray level of "0.5". Therefore, in order to express the 0.25 gray level in the PDP driving waveform of FIG. 6, as shown in FIG. As described above, the halftone processing method of selectively turning on two discharge cells among four discharge cells in order to express a gray level of 0.25 has an advantage of reducing noise as compared to the driving method of FIG. 5. However, in the driving method of FIG. 5, since the decimal point gradation is expressed using the average brightness, a problem that the viewer perceives as noise occurs. In other words, when two discharge cells of four discharge cells are repeatedly selected to express a gray scale of 0.25, predetermined noise is generated. In addition, since the decimal point gray scale is represented by using the subfield SF having one luminance weight value, various decimal point gray scales cannot be represented.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel that can improve image quality by improving expression in low gray scale region expression.

In order to achieve the above object, the plasma display panel driving method according to the embodiment of the present invention, the scan voltage is supplied to the scan / sustain electrode, the data voltage is supplied to the address electrode during the address period of the first subfield, The base voltage is supplied to the common sustain electrode, the scan voltage is supplied to the scan / sustain electrode, the data voltage is supplied to the address electrode, and the positive DC voltage is applied to the common sustain electrode during the address period of the second subfield. It may include the step of supplying.
The first subfield may be configured to apply a negative scan voltage lowered from the scan bias voltage to the scan / sustain electrode during the address period of the first subfield, and apply a positive data voltage synchronized with the scan voltage to the address electrode. And supplying a ground voltage to the common sustain electrode.
The method may further include lowering the voltage of the common sustain electrode immediately after applying the positive voltage to the common sustain electrode while the scan voltage and the data voltage are applied.
In addition, the first subfield may express a gray level corresponding to a predetermined brightness during an address period, and the second subfield may express a gray level corresponding to a higher brightness than the first sub field during an address period.
In addition, the first and second subfields may express brightness corresponding to a gray scale less than or equal to the decimal point.
Subsequently, the first subfield induces the address discharge only by the counter discharge during the address period, and the second subfield induces the address discharge by the counter discharge during the address period, and then maintains the voltage of the common sustain electrode for a predetermined time to scan / sustain. Surface discharge may be induced between the electrode and the common sustain electrode.
The second subfield may include applying a negative scan voltage lowered from a scan bias voltage to the scan / sustain electrode during an address period of the second subfield, and applying a positive data voltage synchronized with the scan voltage to the address electrode. And applying a positive voltage to the common sustain electrode while the scan voltage and the data voltage are applied, and maintaining the voltage of the common sustain electrode at the positive voltage for a predetermined time.

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Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 12.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention. In the present invention as described above, one frame includes at least two or more subfields SF to express the decimal point gray scale.

Referring to FIG. 8, in the embodiment of the present invention, the susfields SF1 and SF2 for representing the decimal point are driven by being divided into a reset period and an address period. The reset period is driven by being divided into a setup period and a setdown period.

During the setup period, the setup voltage RPU rising in the form of a ramp wave is supplied to the scan / sustain electrodes Y so that the discharge cells of the entire screen cause a uniform setup discharge. In the set-down period, the set-down voltage RPD, which descends in the form of a ramp wave, is supplied to the scan / sustain electrodes Y to erase some of the wall charges formed during the set-up period. After the set-up period and the set-down period, the wall charges necessary for the address discharge remain uniformly in all the discharge cells.

In the address period, the scan voltage scn is sequentially supplied to the scan / sustain electrodes Y in one horizontal period. During the address period, the data voltage data synchronized with the scan voltage scn is supplied to the address electrode X. At this time, in the discharge cells supplied with the scan voltage scn and the data voltage data, an address discharge is generated to form wall charges necessary for the sustain discharge. At this time, in the present invention, the positive DC voltage supplied to the common sustain electrode Z to generate the surface discharge YZ and / or the counter discharge XY during the address periods of the subfields SF1 and SF2 representing the decimal point. To control.

In detail, as illustrated in FIGS. 8 and 9, a positive DC voltage is not supplied to the common sustain electrode Z during the address period of the first subfield SF1. In other words, the scan voltage sustain is supplied to the scan / sustain electrode Y and the data voltage data is supplied to the address electrode X during the address period. The common sustain electrode Z is supplied with the voltage of the ground voltage source GND. First, each of the scan / sustain electrode Y and the address electrode X is supplied with a data voltage data synchronized with the scan voltage scn and the scan voltage scn. As a result, a counter discharge (X-Y) is generated between the scan / sustain electrode Y and the address electrode X (tadd). At this time, since the common sustain electrode Z maintains the ground potential GND, a voltage difference is formed between the scan / sustain electrode Y and the common sustain electrode Z below the discharge start voltage. Therefore, no discharge occurs between the scan / sustain electrode Y and the common sustain electrode Z. (t2)

Meanwhile, a positive DC voltage is supplied to the common sustain electrode Z during the address period of the second subfield SF2. That is, in the address period of the second subfield SF2, as shown in FIGS. 4A to 4C, the scan voltage scn is supplied to the scan / sustain electrode Y and the data voltage data is applied to the address electrode X. Supplied. The common sustain electrode Z is supplied with a positive DC voltage. First, when the data voltage data synchronized with the scan voltage scn and the scan voltage scn is supplied to each of the scan / sustain electrode Y and the address electrode X, the scan / sustain electrode Y and the address electrode ( The counter discharge XY is generated between X). At this time, a positive DC voltage is supplied to the common sustain electrode Z. In other words, a voltage difference sufficient for the discharge start voltage is formed between the scan / sustain electrode Y and the common sustain electrode Z. Therefore, surface discharge (Y-Z) is generated between the scan / sustain electrode (Y) and the common sustain electrode (Z).

In the first subfield SF1 of the present invention, the gray level corresponding to the predetermined luminance is expressed by generating the counter discharge X-Y during the address period. (E.g., brightness of approximately " 0.25 ") And in the second subfield SF2, the opposite discharge XY and the surface discharge YZ are generated during the address period to achieve higher luminance than the first subfield SF1. (E.g., brightness of approximately " 0.5 "). When such a first subfield SF1 of the present invention is represented with a grayscale of approximately " 0.25 ", it is shown in FIG. As shown in FIG. 1, the halftone processing is not required since each pixel (here, the luminance of each pixel is " 0.25 ") can be represented in the 0.25 gray level representation. Therefore, the noise problem that occurs during halftone processing does not occur. Similarly, as shown in FIG. 11, even in the gray gray level expression, which is another decimal gray scale expression, an image can be displayed without halftone processing using light generated in the second subfield. Also, various decimal point gray scales can be expressed through an optional arrangement of the decimal point gray representations of 0.25 and 0.5.

Meanwhile, in the present invention, subfields (not shown other than SF3) for expressing gray scales other than the decimal point gray scale are driven by being divided into a reset period, an address period, and a sustain period. Here, the reset period and the address period of the subfields for expressing grayscales other than the decimal point grayscale are the same as the reset period and the address period of the second subfield described above, and thus will be omitted.

In the sustain period, the sustain pulse su is alternately supplied to the scan / sustain electrode Y and the common sustain electrode Z. As described above, when the sustain pulse su is alternately supplied to the scan / sustain electrode Y and the common sustain electrode Z, the sustain discharge is generated in the discharge cells selected in the address period to express a predetermined luminance. Here, the number of sustain pulses sus supplied to the scan / sustain electrode Y and the common sustain electrode Z is determined so as to correspond to the luminance weight of each of the subfields SF.

Voltages necessary for the reset period, the address period and the sustain period are generated by the driving device as shown in FIG.

Referring to FIG. 12, a driving apparatus of a plasma display panel according to an exemplary embodiment includes a scan driver 62, a sustain driver 63, and a data driver 61. In addition, a driving voltage generator 64 for supplying a voltage to each driving unit and a timing controller 60 for controlling each voltage are provided.

The data driver 61 samples the data in response to the timing control signal CTRX supplied from the timing controller 60, and then stores the data synchronized with the scan pulse scn by one horizontal line every one horizontal line. It is supplied to (X1 to Xm). Here, the timing control signal CTRX supplied to the data driver 61 includes a sampling clock for sampling data, a switch control signal for controlling the on / off time of the energy recovery circuit, and the driving switch element. The data voltage supplied from the data driver 61 to the address electrodes X1 to Xm selects an unselected off-cell.

The scan driver 62 supplies a setup ramp RPU in the form of a rising ramp wave to the scan / sustain electrodes Y1 to Yn during the reset period under the control of the timing controller 60 to cause a reset discharge, and then a falling ramp. The wave form setdown voltage RPD is supplied to the scan / sustain electrodes Y1 to Yn to initialize wall charges of all cells. The scan driver 62 sequentially applies the negative scan voltage scn to the scan / sustain electrodes Y1 to Yn to the scan / sustain electrodes Y1 to Yn during the address period under the control of the timing controller 60. To supply. In the sustain period, a sustain pulse sus for causing a sustain discharge for the cell selected by the address discharge is supplied to the scan / sustain electrodes Y1 to Yn according to the luminance weighting value. The timing control signal CTRY applied to the scan driver 62 includes a switch control signal for controlling the on / off time of the switch element in the scan driver 62.

The sustain driver 63 supplies the base voltage GND to the common sustain electrode Z during the set-up period under the control of the timing controller 60 and the positive voltage in the set-down period. The sustain driver 63 supplies the base voltage GND in the address period of the first subfield SF1 to suppress the surface discharge immediately after the address discharge. On the other hand, a voltage is supplied to maintain the positive voltage in the address period of the second subfield and the third subfield SF2 and SF3. In the sustain period, a sustain pulse su is supplied to the sustain electrodes Z alternately with the scan driver 62. The timing control signal CTRZ applied to the sustain driver 63 includes a switch control signal for controlling the on / off time of the switch element in the sustain driver 63.

The driving voltage generator 64 has a positive reset voltage Vsetup corresponding to the upper limit voltage of the setup voltage rising in the ramp wave form and a negative voltage Vy corresponding to the lower limit voltage of the setdown voltage falling in the ramp wave form. ), The positive scan voltage Vscn, the sustain voltage Vsus, and the positive data voltage Vd for selecting the off-cell are generated.                     

The timing controller 60 receives the vertical / horizontal synchronization signal and the main clock signal, and generates timing control signals CTRX, CTRY, and CTRZ required for each driving unit by using the synchronization signal and the main clock.

The method for driving the plasma display panel according to the present invention expresses the gray scale of the decimal point in a plurality of subfields, thereby improving the expressive power of the gray scale, thereby improving the image quality. In other words, in the present invention, since the gray scale of the decimal point is represented without the halftone processing, there is an advantage that the gray scale of the decimal point can be represented without noise. In fact, by using the brightness of 0.25 of the first subfield and the brightness of 0.5 of the second subfield of the present invention, the image quality can be improved by expressing a more diverse and sophisticated decimal point gray scale.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

A driving method of a plasma display panel having a scan / sustain electrode, a common sustain electrode, and an address electrode, and time-dividing one frame period into a plurality of subfields, Supplying a scan voltage to the scan / sustain electrode, a data voltage to the address electrode, and a ground voltage to the common sustain electrode during an address period of a first subfield; And Supplying a scan voltage to the scan / sustain electrode, a data voltage to the address electrode, and supplying a positive DC voltage to the common sustain electrode during an address period of a second subfield; How to drive the display panel. The method of claim 1, wherein the first subfield is Applying a negative scan voltage lowered from a scan bias voltage to the scan / sustain electrode during the address period of the first subfield; Applying a positive data voltage to the address electrode in synchronization with the scan voltage; And And supplying a ground voltage to the common sustain electrode. delete The method of claim 1, Wherein the first subfield represents a gray level corresponding to a predetermined luminance during an address period, and the second subfield represents a gray level corresponding to a higher luminance than the first sub field during an address period. Method of driving. The method of claim 4, wherein And the first and second subfields represent brightness corresponding to gray scales below the decimal point. The method of claim 1, The first subfield induces an address discharge only by opposing discharge during an address period, and the second subfield induces an address discharge by opposing discharge during an address period, and then maintains the voltage of the common sustain electrode for a predetermined time. / Induction of surface discharge between the sustain electrode and the common sustain electrode. The method of claim 1, wherein the second subfield is Applying a negative scan voltage lowered from a scan bias voltage to the scan / sustain electrode during the address period of the second subfield; Applying a positive data voltage to the address electrode in synchronization with the scan voltage; And And maintaining the voltage of the common sustain electrode at the positive voltage for the predetermined time after supplying a positive voltage to the common sustain electrode while the scan voltage and the data voltage are applied to the plasma display panel. Driving method. delete delete delete delete

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