KR100489879B1 - Apparatus and Method of Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that enables stable operation.

The driving method of the plasma display panel of the present invention includes an initialization period for initializing discharge cells, a supply address period for selecting discharge cells, a dummy address period for initializing an address driver for driving address electrodes, The driving is divided into a sustain period for discharging the selected discharge cells in the supply address period.

Description

Driving apparatus and driving method of plasma display panel {Apparatus and Method of Driving Plasma Display Panel}

The present invention relates to a driving apparatus and a driving method of a plasma display panel, and more particularly, to a driving apparatus and a driving method of a plasma display panel to enable a stable operation.

Plasma Display Panel (hereinafter referred to as "PDP") displays characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe, Ne + Xe or He + Xe + Ne inert gas mixtures. The included image is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 is a view showing a driving apparatus of a conventional plasma display panel.

Referring to FIG. 3, a conventional PDP driving apparatus includes an address driver 32 for driving address electrodes X1 to Xm provided in the panel 30, and scan electrodes Y1 to X1 provided in the panel 30. A driving voltage using the scan driver 34 for driving Yn, the sustain driver 36 for driving the sustain electrodes Z1 to Zn provided in the panel 30, and the drivers 32, 34, 36. And a timing controller 38 for supplying control signals SCS1 to SCS3 to the driving units 32, 34, and 36.

The driving voltage generator 40 generates various driving voltages so as to generate driving waveforms as shown in FIG. 4 and supplies them to the address driver 32, the scan driver 34, and the sustain driver 36. For example, the driving voltage generator 40 generates voltages such as Vsetup, -Vw, Vr, and Vs to supply the scan driver 34, and generates the Vs voltage to supply the sustain driver 36. The driving voltage generator 40 generates a voltage of Va and supplies the voltage to the address driver 32.

The timing controller 38 generates various switching control signals and supplies them to the address driver 32, the scan driver 34, and the sustain driver 36 so that a driving waveform as shown in FIG. 4 can be generated. For example, the timing controller 38 generates a first switching control signal SCS1 and supplies it to the scan driver 34, generates a second switching control signal SCS2, and supplies it to the sustain driver 36. The timing controller 38 generates the third switching control signal SCS3 and the data clock DCLK and supplies it to the address driver 32.

The address driver 32 controls the image clock data supplied from the outside while being controlled by the data clock DCLK and the third switching control signal SCS3 supplied from the timing controller 38 to the address electrodes X1 through Xm. To supply.

The scan driver 34 controls the reset pulse, the scan pulse, and the sustain pulse sus to the scan electrodes Y1 to Ym while being controlled by the first switching control signal SCS1 supplied from the timing controller 38. Supply.

The sustain driver 36 controls the positive voltage Vs, the sustain pulse sus and the erase pulse Ers by controlling the second switching control signal SCS2 supplied from the timing controller 38. To Zm).

The driving waveform supplied to the electrodes will be described in detail with reference to FIG. 4. First, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y during the setup period during the initialization period. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

On the other hand, the supply time of the data clock DLCK supplied to the address driver 32 during the address period is set equal to the supply time of the data as shown in FIG. Therefore, the address driver 32 maintains the data supplied at the end of the current address period until the next address period. That is, the data held in the address driver 32 is set differently for each address period in accordance with the data supplied last.

However, if it is determined by the data last supplied to the address driver 32 as described above, the state of the address driver 32 cannot be accurately determined, which may cause a malfunction.

Accordingly, it is an object of the present invention to provide a driving apparatus and a driving method of a plasma display panel which enable stable operation.

In order to achieve the above object, a method of driving a plasma display panel according to the present invention includes an initialization period for initializing discharge cells, a supply address period for selecting discharge cells, and an address driver for driving address electrodes. The dummy address period and the sustain period for discharging the selected discharge cells in the supply address period are driven.

During the supply address period, the address driver receives data pulses and external data to generate data pulses, and supplies the generated data pulses to the address electrodes.

During the supply address period, a scan pulse synchronized with the data pulse is supplied to the scan electrodes to select a discharge cell.

The address driver is initialized by receiving dummy data pulses and dummy data during the dummy address period.

The dummy data is data of "0".

At least one dummy data pulse is supplied to the address driver during the dummy address period.

The dummy data pulse has the same period as the data pulse.

In the driving method of the plasma display panel of the present invention, the address period is driven by dividing the supply address period and the dummy address period, and supplying data pulses to the address electrodes in the address driver during the supply address period, the current address period and the next address. And supplying specific data to the address driver in the dummy address period in order to initialize the state of the address driver to the specific state between the periods.

The data "0" is supplied to the specific data to initialize the address driver to the state "0".

A driving apparatus of a plasma display panel of the present invention includes a timing controller for supplying a data clock and a switching control signal to an address driver; An address driver for receiving data supplied from the outside and supplying the data to the address electrodes using the data clock and the switching control signal; The timing controller supplies the dummy data clock and the dummy data to the address driver after the data clock is supplied to initialize the address driver.

The dummy data is data of "0".

The dummy data clock is set at the same period as the data clock.

The dummy data clock is supplied to the address driver at least one cycle.

A driving apparatus of a plasma display panel of the present invention includes a timing controller for supplying a data clock and a switching control signal to an address driver; An address driver for receiving data supplied from the outside and supplying the data to the address electrodes using the data clock and the switching control signal; A dummy clock generation unit for generating a dummy data clock and supplying the dummy data clock to the address driver while monitoring the data clock supplied from the timing controller.

The dummy clock generator generates at least one cycle of the dummy data clock at the end of supply of the data clock and supplies the dummy clock to the address driver.

The dummy data clock is set at the same period as the data clock.

When the dummy data clock is supplied, the dummy data is supplied to the address driver from one of the timing controller and the dummy clock generator.

The dummy data is data of "0".

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 9.

6 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 6, the driving apparatus of the PDP of the present invention includes an address driver 42 for driving address electrodes X1 to Xm provided in the panel 52, and scan electrodes Y1 provided in the panel 52. Scan driver 44 for driving Yn to Yn, sustain driver 46 for driving sustain electrodes Z1 to Zn provided in panel 52, and driving units 42, 44, and 46 A driving voltage generation unit 50 for supplying a voltage and a timing controller 48 for supplying control signals SCS1 to SCS3 to the driving units 42, 44, and 46 are provided.

The driving voltage generator 50 generates various driving voltages to generate the driving waveforms as shown in FIG. 7 and supplies them to the address driver 42, the scan driver 44, and the sustain driver 46.

For example, the driving voltage generation unit 50 generates voltages such as Vsetup, -Vw, Vr, and Vs to supply the scan driver 44, and generates the Vs voltage to supply the sustain driver 46. The driving voltage generator 50 generates a voltage of Va and supplies the voltage to the address driver 42.

The timing controller 48 generates various switching control signals and supplies them to the address driver 42, the scan driver 44, and the sustain driver 46 to generate a driving waveform as shown in FIG. 7. For example, the timing controller 48 generates the first switching control signal SCS1 and supplies it to the scan driver 44, generates the second switching control signal SCS2, and supplies it to the sustain driver 46.

The timing controller 48 generates the third switching control signal SCS3, the data clock DCLK, and the dummy data clock DDCLK and supplies it to the address driver 42. The data clock DCLK is supplied to the supply address period of the address period. Here, the supply address period is a period in which data supplied from the outside is supplied to the address electrodes X1 to Xm. The dummy data clock DDCLK is supplied in the dummy address period of the address period. Here, in the dummy address period, dummy data (for example, "0" data) is supplied to the address driver 42 to initialize the address driver 42. The dummy data is supplied from the timing controller 48 to be synchronized with the dummy data clock DDCLK. On the other hand, the data clock DCLK and the dummy data clock DDCLK have the same period.

The address driver 42 controls the image clock data supplied from the outside while being controlled by the data clock DCLK, the dummy data clock DDCLK, and the third switching control signal SCS3 supplied from the timing controller 48. Supply to electrodes X1 to Xm. The address driver 42 is initialized by the dummy data clock DDCLK after all data is supplied to the address electrodes X1 to Xm.

The scan driver 44 controls the reset pulse, the scan pulse and the sustain pulse sus to the scan electrodes Y1 to Ym while being controlled by the first switching control signal SCS1 supplied from the timing controller 48. Supply.

The sustain driver 46 is controlled by the second switching control signal SCS2 supplied from the timing controller 48 to maintain the positive electrodes V1, the sustain pulse sus and the erase pulses Z1. To Zm).

The driving waveform supplied to the electrodes will be described in detail with reference to FIG. 7. First, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y during the setup period during the initialization period. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

The address period is driven by being divided into a supply address period and a dummy address period. During the supply address period, the address driver 42 supplies data supplied from the outside to the address electrodes X in synchronization with the data clock DCLK as shown in FIG. 8 (actually, a data pulse using a Va voltage). ), And the generated data pulses are supplied to the address electrodes X so as to correspond to the data.) During the supply address period, the scan electrodes Y are synchronized with the data pulses (data). Is approved. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

During the dummy address period, the address driver 42 receives the dummy data clock DCLK and the dummy data Ddata having at least one period as shown in FIG. 8. Here, the dummy data Ddata is substantially set to data of "0", so that the address driver 42 is initialized to the state of "0" during the dummy address period. For example, the address driver 42 may be initialized by supplying the dummy data clock DCLK having one period during the dummy address period. On the other hand, scan pulses are not supplied during the dummy address period.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In the present invention as described above, the state of the address driver 42 is always constant by adding a dummy address period for initializing the state of the address driver 42 to a specific state (for example, a state in which "0" data is input). I can keep it. In other words, since the address driver 42 always maintains a specific state between the current address period and the next address period, the malfunction of the address driver 42 can be prevented.

Meanwhile, in the present invention, the driving device of the PDP may be configured as shown in FIG. 9. Here, the components having the same function as the driving apparatus shown in FIG. 6 are assigned the same reference numerals and detailed description thereof will be omitted.

Referring to FIG. 9, a driving apparatus of a PDP according to another embodiment of the present invention includes an address driver 42 for driving address electrodes X1 to Xm provided in the panel 52, and a panel 52. A scan driver 44 for driving the scan electrodes Y1 to Yn, a sustain driver 46 for driving the sustain electrodes Z1 to Zn provided in the panel 52, and drivers 42 and 44 A driving voltage generator 50 for supplying a driving voltage to the motor 46, a timing controller 62 for supplying the control signals SCS1 to SCS3 to the drivers 42, 44, and 46, and an address driver ( 42, a dummy clock generation unit 60 for supplying a dummy data clock DDCLK.

The driving voltage generator 50 generates various driving voltages to generate the driving waveforms as shown in FIG. 7 and supplies them to the address driver 42, the scan driver 44, and the sustain driver 46.

The timing controller 62 generates various switching control signals and supplies them to the address driver 42, the scan driver 44, and the sustain driver 46 so that the driving waveform shown in FIG. 7 can be generated.

The timing controller 62 generates the third switching control signal SCS3 and the data clock DCLK and supplies it to the address driver 42. The dummy clock generator 60 generates the dummy data clock DDCLK while monitoring the data clock DCLK from the timing controller 62. (The dummy data clock DDCLK has the same period as the data clock DCLK. .)

  This will be described in detail. The dummy clock generator 60 does not supply the dummy data clock DDCLK to the address driver 42 while the data clock DCLK is input from the timing controller 48. When the data clock DCLK is not supplied to the dummy clock generator 60 after the last data clock DCLK is supplied, the dummy clock generator 60 generates at least one dummy data clock DDCLK to the address driver 42. Supply.

The data clock DCLK is supplied to the supply address period of the address period. Here, the supply address period is a period in which data supplied from the outside is supplied to the address electrodes X1 to Xm. The dummy data clock DDCLK is supplied in the dummy address period of the address period. Here, in the dummy address period, dummy data (e.g., "0" data) is supplied to the address driver 42 to initialize the address driver 42. (The dummy data is the timing controller 62 and the dummy clock generator. On the other hand, even if the dummy data Ddata is supplied to the address electrodes X1 to Xm during the dummy address period, the scan pulse is not supplied and thus does not affect the discharge. .

The address driver 42 is provided by the data clock DCLK, the dummy data clock DDCLK, the dummy data, and the third switching control signal SCS3 supplied from the timing controller 48 and / or the dummy clock generator 60. Controlled and supplied image data (data) supplied from the outside to the address electrodes (X1 to Xm). The address driver 42 is initialized by the dummy data clock DDCLK after all data is supplied to the address electrodes X1 to Xm.

The scan driver 44 controls the reset pulse, the scan pulse and the sustain pulse sus to the scan electrodes Y1 to Ym while being controlled by the first switching control signal SCS1 supplied from the timing controller 48. Supply.

The sustain driver 46 is controlled by the second switching control signal SCS2 supplied from the timing controller 48 to maintain the positive electrodes V1, the sustain pulse sus and the erase pulses Z1. To Zm). In addition, the detailed driving process is the same as that of the embodiment of the present invention shown in FIG.

As described above, according to the driving apparatus and driving method of the plasma display panel according to the present invention, it is possible to prevent the malfunction of the address driver by setting the address driver to a specific state between the current address period and the next address period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing one frame of a conventional plasma display panel.

3 is a view showing a driving apparatus of a conventional plasma display panel.

4 is a waveform diagram showing a driving waveform supplied to electrodes by the driving apparatus shown in FIG.

5 is a diagram illustrating a data clock and data supplied to an address driver.

6 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating a driving waveform supplied to electrodes by the driving apparatus shown in FIG. 6.

8 is a diagram illustrating data clocks, data, dummy data clocks, and dummy data supplied to an address driver.

9 is a view showing a driving apparatus for a plasma display panel according to another embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

30, 52: panel 32, 42: address driver

34,44: scan driver 36,46: sustain drive

38,48,62: timing controller 40,50: drive voltage generator

60: dummy clock generator

Claims (18)

An initialization period for initializing the discharge cells, A supply address period for selecting the discharge cells; A dummy address period for initializing an address driver for driving address electrodes; And a driving period divided into a sustain period for discharging the selected discharge cells in the supply address period. The method of claim 1, And the address driver receives data pulses and external data during the supply address period, generates data pulses, and supplies the generated data pulses to the address electrodes. The method of claim 2, And the discharge cells are supplied to the scan electrodes in synchronization with the data pulses during the supply address period to select the discharge cells. The method of claim 1, And the address driver is initialized by receiving dummy data pulses and dummy data during the dummy address period. The method of claim 4, wherein And said dummy data is data of " 0 ". The method of claim 4, wherein And at least one dummy data pulse is supplied to the address driver during the dummy address period. The method according to claim 2 or 4, And said dummy data pulse has the same period as said data pulse. The address period is driven divided into the supply address period and the dummy address period. Supplying a data pulse to address electrodes in an address driver during the supply address period; And supplying specific data to the address driver in the dummy address period to initialize the state of the address driver to a specific state between a current address period and a next address period. The method of claim 8, And supplying data of " 0 " to the specific data to initialize the address driver to a state of " 0 ". A timing controller for supplying a data clock and a switching control signal to the address driver; An address driver for receiving data supplied from the outside and supplying the data to address electrodes using the data clock and the switching control signal; And the timing controller supplies a dummy data clock and dummy data to the address driver after the data clock is supplied to initialize the address driver. The method of claim 10, And said dummy data is data of "0". The method of claim 10, And the dummy data clock is set at the same period as the data clock. The method of claim 12, And the dummy data clock is supplied to the address driver for at least one cycle. A timing controller for supplying a data clock and a switching control signal to the address driver; An address driver for receiving data supplied from the outside and supplying the data to address electrodes using the data clock and the switching control signal; And a dummy clock generator for generating a dummy data clock and supplying the dummy data clock to the address driver while monitoring the data clock supplied from the timing controller. The method of claim 14, And the dummy clock generator generates at least one cycle of the dummy data clock at a time point at which the data clock is supplied and supplies the dummy clock to the address driver. The method of claim 14, And the dummy data clock is set at the same period as the data clock. The method of claim 14, And when the dummy data clock is supplied, dummy data is supplied to the address driver from any one of the timing controller and the dummy clock generator. The method of claim 17, And said dummy data is data of "0".