KR100719570B1 - Apparatus for driving discharge display panel wherein reset operation is stabilized - Google Patents

Abstract

In the driving apparatus of the discharge display panel of the present invention, in a state in which a second voltage is applied to the electrode-lines of the discharge display panel, the voltage of the electrode-lines is raised to a first voltage higher by a third voltage than the second voltage. And a reset rising circuit. The reset rising circuit includes a first capacitor, a field effect transistor, a second capacitor, and a diode. A third voltage is applied to one end of the first capacitor and a second voltage is applied to the other end thereof. A third voltage is applied to the drain of the field effect transistor, a control signal is applied to the gate, and a voltage of the source is applied to the electrode-lines. One end of the second capacitor is connected to the gate of the field effect transistor. An anode of the diode is connected to the other end of the second capacitor and a cathode is connected to the drain of the field effect transistor.

Description

Apparatus for driving discharge display panel where reset operation is stabilized}

1 is an internal perspective view showing the structure of a plasma display panel of a three-electrode surface discharge method that is a driving target of the driving apparatus of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a unit display cell of the panel of FIG. 1.

3 is a timing diagram illustrating an address-display separation driving method for Y electrode-lines of the plasma display panel of FIG. 1.

4 is a block diagram illustrating an apparatus for driving a plasma display panel according to the present invention.

5 is a timing diagram illustrating driving signals applied to the panel of FIG. 1 in a unit sub-field by the driving apparatus of FIG. 4.

6 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t2 of FIG. 5.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t3 of FIG. 5.

8 is a view illustrating a scan driving circuit and a switching output circuit of a Y driving unit in the driving device of FIG. 4.

FIG. 9 is a diagram illustrating the reset / hold circuit of FIG. 8.

FIG. 10 is a diagram illustrating an internal circuit of an X driver in the driving device of FIG. 4.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., X _n ... X electrode-line, Y ₁ , ..., Y _n ... Y electrode-line,

A _R1 , ..., A _Bm ... address electrode-line, X _na , Y _na ... transparent electrode-line,

X _nb , Y _nb ... metal electrode-line,

SF1, ... SF8, SF ₁ , ... SF ₈ ... sub-field,

52 logic controller, 53 address drive,

54 ... X drive, 55 ... Y drive,

56 image processing unit, RSC ...

AC ... scan drive circuit,

SIC ... switching output circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive device for a discharge display panel including a reset rise circuit, and more particularly, to a drive device for a discharge display panel including a reset rise circuit for raising a voltage of electrode-lines in a reset period.

In a typical discharge display device, for example, the plasma display device of US Pat. No. 5,541,618, a unit frame is divided into a plurality of subfields for time division gray scale display, and each of the subfields is a reset period, an addressing period, and a sustain period. It includes. Each of the subfields has a unique gray scale weight value, and a maintenance period is set in proportion to the gray scale weight value.

In the discharge display device as described above, a reset rising operation for continuously raising the voltage of the electrode-lines to the maximum voltage in the reset period is required. Accordingly, a more stable reset rising operation is required.

An object of the present invention is to provide a drive device for a discharge display panel having a more stable reset rising circuit.

In the driving apparatus of the discharge display panel of the present invention for achieving the above object, the voltage of the electrode-lines by a third voltage than the second voltage in a state in which a second voltage is applied to the electrode-lines of the discharge display panel A reset rising circuit for raising to a higher first voltage. The reset rising circuit includes a first capacitor, a field effect transistor, a second capacitor, and a diode. The third voltage is applied to one end of the first capacitor, and the second voltage is applied to the other end of the first capacitor. The third voltage is applied to a drain of the field effect transistor, a control signal is applied to a gate, and a voltage of a source is applied to the electrode lines. One end of the second capacitor is connected to the gate of the field effect transistor. An anode of the diode is connected to the other end of the second capacitor and a cathode is connected to the drain of the field effect transistor.

According to the driving device of the discharge display panel of the present invention, in the reset rising circuit, since the second capacitor acts between the gate and the drain of the field effect transistor, the operation of the field effect transistor can be more stabilized. In addition, when the initial overvoltage of the third voltage is generated when power is applied to the driving device of the plasma display panel, the initial overvoltage of the third voltage is applied to the gate of the field effect transistor to provide the field effect transistor. The problem of turning on can be prevented by the diode. Accordingly, a more stable reset rising operation can be performed.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

1 shows the structure of a plasma display panel 1 of a three-electrode surface discharge method that is a driving target of the driving apparatus of the present invention. FIG. 2 shows the configuration of a unit display-cell of panel 1 of FIG. 1. 1 and 2, between the front and rear glass substrates 10, 13 of a conventional surface discharge plasma display panel 1, address electrode-lines A _R1 ,..., A _Bm , Dielectric layers 11 and 15, Y electrode-lines Y ₁ , ..., Y _n , X electrode-lines X ₁ , ..., X _n , phosphor 16, partition 17 And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied over the entire surface in front of the address electrode lines A _R1 , ..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., A _Bm . These partitions 17 function to partition the discharge area of each cell and to prevent optical cross talk between each cell. The phosphor 16 is applied between the partition walls 17.

The X electrode-lines X ₁ , ..., X _n and the Y electrode-lines Y ₁ , ..., Y _n are address electrode-lines A _R1 , ..., A _Bm It is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to the. Each intersection sets a corresponding cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode-lines made of a transparent conductive material such as indium tin oxide (ITO). (X _na , Y _{na in} FIG. 2) and a metal electrode line (X _nb , Y _{nb in} FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the back of the X electrode lines X ₁ ,..., And X _n and the Y electrode lines Y ₁ ,..., And Y _n . . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

3 illustrates an address-display separation driving method for Y electrode-lines of the plasma display panel of FIG. 1. Referring to FIG. 3, each of the unit frames is divided into eight subfields SF1,..., SF8 to realize time division gray scale display. In addition, each subfield SF1, ..., SF8 has reset periods I1, ..., I8, address periods A1, ..., A8, and sustain periods S1, ..., S8. Is divided into

The discharge conditions of all the display cells become uniform in each reset period I1, ..., I8.

In each address period A1, ..., A8, a display data signal is applied to the address electrode lines (A _R1 , ..., A _{Bm in} FIG. 1) and at the same time, each Y electrode line Y ₁ , ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each sustain period S1, ..., S8, all Y electrode-lines Y ₁ , ..., Y _n and all X electrode-lines X ₁ , ..., X _n The holding pulses are alternately applied to generate display discharges in the discharge cells in which wall charges are formed in the corresponding address periods A1, ..., A8. Therefore, the luminance of the plasma display panel is proportional to the length of the sustain periods S1, ..., S8 occupied in the unit frame. The lengths of the sustain periods S1, ..., S8 occupy a unit frame are 255T (T is unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the sustain period S1 of the first subfield SF1 and the time 2T corresponding to 2 ¹ in the sustain period S2 of the second subfield SF2. Is a time 4T corresponding to 2 ² in the sustain period S3 of the third subfield SF3, and a time 8T corresponding to 2 ³ in the sustain period S4 of the fourth subfield SF4. Is a time 16T corresponding to 2 ⁴ in the sustain period S5 of the fifth subfield SF5, and a time 32T corresponding to 2 ⁵ in the sustain period S6 of the sixth subfield SF6. ) Is a time 64T corresponding to 2 ⁶ in the sustain period S7 of the seventh subfield SF7, and a time (2) corresponds to 2 ⁷ in the sustain period S8 of the eighth subfield SF8. 128T) are set respectively.

Accordingly, if a subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any subfields.

Referring to FIG. 4, the driving apparatus of the plasma display panel 1 according to the present invention includes an image processor 56, a logic controller 52, an address driver 53, an X driver 54, and a Y driver 55. It includes. The image processing unit 56 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 52 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 56. The address driver 53 generates the display data signal by processing the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 52, and generates the display data signal. Is applied to the address electrode-lines (A _R1 , ..., A _Bm in FIG. 1). The X driver 54 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the logic controller 52 to form X electrode-lines (X _{1 in} FIG. 1). , ..., X _n ). The Y driver 55 processes the Y driving control signal S _Y from the driving control signals S _A , S _Y , and S _X from the logic controller 52 to Y electrode-lines (Y _{1 in} FIG. 1). , ..., Y _n ).

FIG. 5 shows driving signals applied to the panel 1 of FIG. 1 in the unit sub-field SF by the driving device of FIG. 4. In FIG. 5, S _{AR1 .. ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 , ..., A _Gm , A _Bm of FIG. 1), and S _{X1 .. Xn} is X The driving signal applied to the electrode-lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are each Y electrode-lines (Y ₁ ,. .Y _n ) indicates a drive signal applied to the. FIG. 6 illustrates a wall charge distribution of one display cell at a time point t2 immediately after a gradual rising voltage is applied to the Y electrode lines Y ₁ , ... Y _n in the reset period I of FIG. 5. Shows. FIG. 7 illustrates a wall charge distribution of one display cell at a time point t3, which is the end point of the reset period I of FIG. 5. 6 and 7 the same reference numerals as used in FIG. 2 indicate the object of the same function.

Referring to FIG. 5, in the rising periods t1 to t2 in the reset period I of the unit sub-field SF, voltages applied to the Y electrode lines Y ₁ ,..., Y _n . For example, the second voltage V _S , for example, the first voltage V _SET + V _{S that} is higher than the second voltage V _S from 155 volts V by a third voltage V _SET . Continuously rising to 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 , ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ , ..., X _n ), while the Y electrode lines ( A weaker discharge occurs between Y ₁ ,..., Y _n ) and the address electrode-lines A _R1 ,..., A _Bm . Here, Y electrode lines (Y _1, ..., Y _n) and the address electrode Y _1, the line (- lines _{(A R1, ..., A Bm} ) a discharge than Y electrode between. .., Y _n ) and the discharge between X electrode-lines (X ₁ , ..., X _n ) become stronger because around X electrode-lines (X ₁ , ..., X _n ) This is because negative wall charges were formed in the. Accordingly, Y electrode lines _{(Y 1, ..., Y n} ) is formed around a lot of the negative wall charges, X electrode lines _{(X 1, ..., X n} ) is surrounded by positive Wall charges are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 6).

Next, in the falling period t2 to t3 in the reset period I, the voltage applied to the X electrode-lines X ₁ ,..., X _n is maintained at the second voltage V _S. In the state, the voltage applied to the Y electrode-lines Y ₁ ,..., Y _n is continuously lowered from the second voltage V _S to the ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 , ..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y). Some of the negative wall charges around ₁ , ..., Y _{n move} around the X electrode-lines X ₁ , ..., X _n (see FIG. 7). Further, the address electrode lines (A _R1, ..., A _Bm) is so applied with a ground voltage (V _G), the address electrode lines (A _R1, ..., A _Bm) positive wall surrounding The charges increase slightly.

Accordingly, in a subsequent addressing period A, the display data signal is applied to the address electrode lines A _R1 ,..., A _Bm , and the fourth voltage V _SCAN lower than the second voltage V _S. As a scan signal of the ground voltage V _G is sequentially applied to the Y electrode lines Y ₁ ,..., And Y _n biased by), smooth addressing may be performed. The display data signal applied to each address electrode line A _R1 , ..., A _Bm has a positive address voltage V _A when the display cell is selected and a ground voltage V _G otherwise. Is approved. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient address discharge, the second voltage V _S is applied to the X electrode lines X ₁ , X _n .

In the following sustain period S, the maintenance of the second voltage V _{S at} all the Y electrode-lines Y ₁ , ... Y _n and the X electrode-lines X ₁ , ... X _n . The pulses are alternately applied, causing discharge for retention in the display cells in which wall charges are formed in the corresponding address period A. FIG.

FIG. 8 shows a scan driving circuit AC and a switching output circuit SIC of the Y driver 55 in the driving device of FIG. 4. Referring to FIG. 8, the Y driver according to the present invention includes a reset / hold circuit RSC, a scan driver circuit AC, and a switching output circuit SIC. The reset / sustain circuit RCS generates drive signals to be applied to the Y electrode-lines Y ₁ ,... Y _n in the reset period I and the sustain period S. FIG. The scan driving circuit AC generates drive signals to be applied to the Y electrode-lines Y ₁ ,... Y _n in the addressing period A. FIG. In the switching output circuit SIC, the upper transistors YU1, ..., YUn and the lower transistors YL1, ..., YLn are arranged so that the common output lines of each upper transistor and each lower transistor are respectively. Are connected to correspond to the Y electrode lines Y ₁ , ..., Y _{n of} . 8 and 5, the operation process of the Y driver of FIG. 8 will be described.

In the reset period I and the sustain period S, the drive signals O _RS from the reset / hold circuit RSC are at the A point of the scan drive circuit AC and the lower transistor of the switching output circuit SIC. Are applied to the Y electrode-lines Y ₁ ,..., Y _{n of the} three-electrode plasma display panel 1 through the fields YL1,... In this case, all the large power transistors S _SC1 , S _SC2 , S _SSP , and S _{SCL of the} scan driving circuit AC are turned off. In addition, the driving signals O _RS from the reset / sustain circuit RCS may include the A point of the scan driving circuit AC, the third large power transistor S _SP , and the upper transistors of the switching output circuit SIC. YU1, ..., YUn) to the Y electrode-lines of the three-electrode plasma display panel 1. In this case, the other high power transistors S _SC1 , S _SC2 and S _SCL are turned off in the scan driving circuit AC except for the associated high power transistor S _SP .

In the addressing period A, the remaining large power transistors S _SC1 , S _SC2 , and S _SCL except for the third large power transistor S _SP of the scan driving circuit AC are turned on. Accordingly, the scanning bias voltage V _SCAN is applied to the upper transistors YU1,..., And YUn of the switching output circuit SIC through the first and second large power transistors S _SC1 and S _SC2 . Is approved. In addition, the ground voltage V _G of FIG. 5 is applied to the lower transistors YL1,..., YLn of the switching output circuit SIC through the fourth large power transistor S _SCL . Here, the lower transistor connected to the Y electrode-line to be scanned is turned on and the upper transistor is turned off. In addition, the bottom transistors connected to all remaining Y electrode-lines that are not to be scanned are turned off and the top transistors are turned on. Accordingly, the scan ground voltage V _G is applied to one Y electrode line to be scanned, and the scan bias voltage V _SCAN is applied to all the other Y electrode lines that are not to be scanned.

In the addressing period A, when the scan ground voltage V _G is applied to one Y electrode line to be scanned, the display data signal is applied to the address electrode lines A _R1 , ..., A _Bm . When the application of the display data signal is terminated at the time of application, the address electrode lines A _R1 , ..., A _Bm , and the scanning ground voltage V _G is applied to the Y electrode line to be scanned. Looking at the current paths at the end of the process is as follows.

First, at a time when the scanning ground voltage V _G is applied to one Y electrode line to be scanned, one lower side of the switching output circuit SIC from the display cells (electrical capacitors) connected to the one Y electrode line to be scanned. Current flows to the ground terminal through the fourth large power transistor S _SCL of the transistor and the scan driving circuit AC.

Second, at the time when the display data signal is applied to the address electrode lines A _R1 , ..., A _Bm , one Y electrode line being scanned from the address electrode lines to which the selection voltage V _A is applied. In addition to the discharge current, all remaining non-scanned Y electrode-lines, upper transistors of the switching output circuit SIC, first and second large power transistors S _SC1 , of the scan driving circuit AC, Current flows through the terminal of the scanning bias voltage V _SCAN through S _SC2 ).

Third, when the application of the display data signal to the address electrode lines A _R1 , ..., A _Bm is terminated, the first of the scan driving circuit AC is connected from the terminal of the scanning bias voltage V _SCAN . And currents through the second large power transistors S _SC1 , S _SC2 , the upper transistors of the switching output circuit SIC, and the Y electrode lines, to the address electrode lines A _{R1 ,.} Flows.

Fourth, at the time when the scanning ground voltage V _G is applied to the Y electrode line to be scanned, the first and the first portions of the scan driving circuit AC are connected from the terminals of the scanning bias voltage V _SCAN . Current flows into the display cells (electrical capacitors) through the two large power transistors S _SC1 , S _SC2 , the upper transistors of the switching output circuit SIC, and the Y electrode-lines.

Therefore, a large power transistor for switching is connected between the common line of the upper transistors of the switching output circuit SIC and the terminal of the scanning bias voltage V _SCAN .

Meanwhile, an operation in which the output O _X from the X driver 64 is applied to the X electrode lines X ₁ ,..., X _n will be described with reference to FIG. 10.

FIG. 9 shows the reset / hold circuit RSC of FIG. 8. In FIG. 9, the third through sixth transistors ST3,..., And ST6 are applied to the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) in a reset period (I in FIG. 5). It generates a driving signal (O _RS ) to be.

Referring to Figure 9, and 5, units of the sub-order to increase the reset period (t1 ~ t2) of the field (SF), Y electrode lines _{(Y 1, ..., Y n} ) a second voltage (V _S to ) in the applied state, Y electrode lines (by the higher first voltage Y _1, ..., Y _n) voltage to the second voltage (V _s) than the third voltage (V _SET) of (V _s There are reset rising circuits C1, ST6, C2, and D4 that raise to + V _SET ).

The reset rising circuits C1, ST6, C2, and D4 include a first capacitor C1, a sixth field effect transistor ST6, a second capacitor C2, and a fourth diode D4.

One end of the first capacitor C1 is applied with the third voltage V _SET through the third diode D3, and the other end thereof has the second voltage V _{S being} applied through the third field effect transistor ST3. Become.

The third voltage V _SET is applied to the anode of the sixth field effect transistor ST6 through the third diode D3, and the gate is controlled from the logic controller 52 in FIG. 4. A signal is applied and a voltage of the source is applied to the Y electrode lines Y ₁ ,..., Y _n .

One end of the second capacitor C2 is connected to the gate of the sixth field effect transistor ST6. An anode of the fourth diode D4 is connected to the other end of the second capacitor C2, and a cathode is connected to the anode of the sixth field effect transistor ST6.

According to the reset rising circuits C1, ST6, C2, and D4 as described above, the second capacitor C2 acts between the gate and the drain of the sixth field effect transistor ST6, and thus the sixth field effect transistor ST6. The operation of can be more stabilized. Further, when the initial voltage of the third voltage (V _SET) occurs at the point when the power is supplied to the drive device of a plasma display panel, the initial voltage of the third voltage (V _SET) of the sixth field-effect transistor (ST6) The problem that the sixth field effect transistor ST6 is turned on by being applied to the gate may be prevented by the fourth diode D4. Accordingly, a more stable reset rising operation can be performed. The voltage raising operation of the reset rising circuits C1, ST6, C2, and D4 will be described below.

For reference, according to an experiment, when the resistor is connected in parallel with the fourth diode D4, the charging / discharging effect of the second capacitor C2 can be obtained more, but the initial overvoltage of the third voltage V _SET is The sixth field effect transistor ST6 is turned on by being applied to the gate of the sixth field effect transistor ST6 through a resistor. Therefore, it is not preferable to connect the resistor in parallel with the fourth diode D4.

Meanwhile, the power regeneration capacitor C _SY , the first to fifth transistors ST1,..., ST5, and the tuning coil L _Y are Y electrode-lines in the display sustain period (S of FIG. 5). Generates a driving signal O _{RS to} be applied to (Y ₁ , ..., Y _n ).

Referring to FIGS. 9 and 5, the operation of the reset / hold circuit RSC of FIG. 9 will be described as follows.

In the reset rising periods t1 to t2 included in the reset period I of the unit sub-field SF, only the third and sixth transistors ST3 and ST6 are turned on and the sixth is turned on. The third voltage V _SET is applied to the drain Drain of the transistor ST6 through the third diode D3. Here, since a control voltage that is continuously raised is applied to the gate of the sixth transistor ST6, the channel resistance of the sixth transistor ST6 is continuously reduced. In addition, since the second voltage V _S is applied to the source of the third transistor ST3, between the source of the third transistor ST3 and the drain of the sixth transistor ST6. Due to the action of the first capacitor C1 connected to the drain, the drain of the sixth transistor ST6 has a voltage continuously rising from the second voltage V _S to the first voltage V _SET + V _S. Is approved. Accordingly, all Y electrode-lines Y ₁ ,..., Y _n are continuous from the second voltage V _S to the first voltage V _SET + V _S , for example 355 volts V. FIG. The voltage rising to is applied.

Here, as described above, since the second capacitor C2 operates between the gate and the drain of the sixth field effect transistor ST6, the operation of the sixth field effect transistor ST6 may be more stabilized. Further, when the initial voltage of the third voltage (V _SET) occurs at the point when the power is supplied to the drive device of a plasma display panel, the initial voltage of the third voltage (V _SET) of the sixth field-effect transistor (ST6) The problem that the sixth field effect transistor ST6 is turned on by being applied to the gate may be prevented by the fourth diode D4. Accordingly, a more stable reset rising operation can be performed.

In the reset falling period t2 to t3, first, only the third and fifth field effect transistors ST3 and ST5 are turned on so that the second voltage V _S is changed to all Y electrode-lines ( Y ₁ , ..., Y _n ). Next, since only the fifth and seventh field effect transistors ST5 and ST7 are turned on, and a control voltage that is continuously raised is applied to the gate of the seventh field effect transistor ST7, the seventh field is applied. The channel resistance of the effect transistor ST7 decreases continuously. Accordingly, the voltage applied to all the Y electrode lines Y ₁ ,..., Y _n is continuously lowered from the second voltage V _S to the ground voltage V _G.

In the following addressing period A, all the field effect transistors ST3, ..., ST6 of the reset / hold circuit RSC are turned off, so that the output of the reset / hold circuit RSC is turned off. It is in an electrically floating state.

In the subsequent display sustain period S, the unit pulses applied to all the Y electrode lines Y ₁ ,..., And Y _n fall from the second voltage V _S to the ground voltage V _G. Only the second and fifth field effect transistors ST2 and ST5 are turned on in time. Accordingly, charges that remain unnecessarily in the display cells (electrical capacitors) are collected in the power regenerative capacitor C _SY . The charges collected in this way are applied to all the Y electrode lines Y ₁ ,..., Y _n at the time of rising from the ground voltage V _G to the second voltage V _S to be recycled. This will be described step by step as follows.

The time to rise from the ground voltage V _G to the second voltage V _S in the unit pulse applied to all the Y electrode-lines Y ₁ ,..., Y _n in the display holding period S. Only the first and fifth field effect transistors ST2 and ST5 are turned on. Accordingly, charges collected in the power regeneration capacitor C _SY are transferred through the first field effect transistor ST1, the first diode D1, the tuning coil L _Y , and the fifth field effect transistor ST5. Is applied to all Y electrode-lines Y ₁ ,..., Y _n .

Next, only the third and fifth transistors ST3 and ST5 are turned on so that the second voltage V _S is applied to all Y electrode-lines Y ₁ ,..., Y _n . Is approved. Here, the turn-on time point of only the third and fifth field effect transistors ST3 and ST5 is the end point of rising of the sustain pulses.

Next, only the second and fifth field effect transistors ST2 and ST5 are turned on at the time of falling from the second voltage V _S to the ground voltage V _G. Accordingly, unnecessarily remaining charges in the display cells (electric capacitors) may cause the fifth field effect transistor ST5, the tuning coil L _Y , the second diode D2, and the second field effect transistor ST2. Collected in the power reproduction capacitor C _SY .

Finally, only the fourth and fifth field effect transistors ST4 and ST5 are turned on so that the ground voltage V _G is applied to all the Y electrode-lines Y ₁ ,..., Y _n . Is applied to.

FIG. 10 shows an internal circuit of the X driver 64 in the driving device of FIG. 4. Referring to FIGS. 10 and 5, the operation of the X driver 64 of FIG. 10 performing the driving method according to the present invention will be described below.

In the reset period I of the unit sub-field SF, only the fourth field effect transistor ST4a is turned on in the reset rising period t1 to t2 so that the output signal O _X is grounded. It becomes the voltage (V _G ).

Next, in the reset falling periods t2 to t3, only the third field effect transistor ST3a is turned on so that the voltage of the output signal O _X becomes the second voltage V _S. This state continues until the addressing period A.

In a unit pulse applied to all X electrode-lines X ₁ ,..., X _{n in the} subsequent display sustain period S, the voltage falls from the second voltage V _S to the ground voltage V _G. Only the second field effect transistor ST2a is turned on in time. Accordingly, charges that remain unnecessarily in the display cells (electrical capacitors) are collected in the power regenerative capacitor C _SX . The charges thus collected are applied to all the X electrode lines X ₁ ,..., X _n and recycled at a time rising from the ground voltage V _G to the second voltage V _S. This will be described step by step as follows.

The time to rise from the ground voltage V _G to the second voltage V _S in the unit pulse applied to all the X electrode lines X ₁ ,..., X _n in the display holding period S. Only the first field effect transistor ST1a is turned on. Accordingly, the charges collected in the power regeneration capacitor C _SX pass through all of the X electrode-lines X ₁ through the first field effect transistor ST1a, the fifth diode D5, and the tuning coil L _X. , ..., X _n ).

Next, only the third field effect transistor ST3a is turned on, so that the second voltage V _S is applied to all of the Y electrode lines Y ₁ ,..., Y _n . Here, the turn on time of only the third field effect transistor ST3a is the end time of the rising of the sustain pulses.

Next, only the second field effect transistor ST2a is turned on at the time of falling from the second voltage V _S to the ground voltage V _G. Accordingly, the display cells are the remaining unnecessary charges to the (electrically kaepesiteo s) tuning coils (L _X), the sixth diode (D6), and a kaepesiteo for electric power reproduction through the second field effect transistor (ST2a) (C _SX) Is collected on.

Finally, only the fourth field effect transistor ST4a is turned on so that the ground voltage V _G is applied to all X electrode-lines X ₁ ,..., X _n .

As described above, according to the driving device of the discharge display panel according to the present invention, in the reset rising circuit, since the second capacitor acts between the gate and the drain of the field effect transistor, the operation of the field effect transistor can be more stabilized. have. In addition, when the initial overvoltage of the third voltage is generated when power is applied to the driving device of the plasma display panel, the initial overvoltage of the third voltage is applied to the gate of the field effect transistor so that the field effect transistor is turned on. The problem can be avoided by the diode. Accordingly, a more stable rising reset operation can be performed.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (4)

A discharge display panel including a reset rising circuit configured to increase a voltage of the electrode lines to a first voltage higher by a third voltage than the second voltage in a state where a second voltage is applied to electrode lines of the discharge display panel; In the drive device of, The reset rising circuit, A first capacitor to which the third voltage is applied at one end thereof and the second voltage is applied at the other end thereof; A field effect transistor having the third voltage applied to its drain, a control signal applied to its gate, and a voltage of the source applied to the electrode-lines; A second capacitor whose one end is connected to the gate of the field effect transistor, and And an anode of which the anode is connected to the other end of the second capacitor and whose cathode is connected to the drain of the field effect transistor. The method of claim 1, In the discharge display panel, X electrode-lines and Y electrode-lines form XY electrode-line pairs, and address electrode-lines are arranged in a direction crossing the XY electrode-line pairs, And a reset driving circuit is included in a Y driver for driving the Y electrode lines. The method of claim 2, A controller configured to generate driving control signals according to an input image signal; An address driver which processes an address signal from the controller to generate a display data signal, and applies the generated display data signal to address electrode lines; An X driver configured to drive the X electrode lines by operating in response to an X drive control signal from the controller; And And a driving unit for operating the discharge display panel according to the driving control signal from the control unit. The method of claim 3, The apparatus may further include an image processor configured to convert an external analog image signal into a digital signal to generate an internal image signal. And a control unit to generate driving control signals according to an internal image signal from the image processing unit.

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