KR100480170B1 - Driving method and apparatus of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that enables stable operation at low temperatures.

In a method of driving a plasma display panel according to the present invention, the method of driving a plasma display panel in which an initialization period is divided into a setup period and a set-down period is provided, wherein the plasma display panel is configured to detect a temperature of the plasma display panel, Supplying a first rising ramp waveform to the scan electrode during the setup period when the temperature is higher than the low temperature; and supplying a second voltage to the scan electrode during the setup period when the plasma display panel is driven at the low temperature. And supplying a second rising ramp waveform that rises to.

Description

DRIVING METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and a driving method of a plasma display panel, and more particularly, to a driving apparatus and a driving method of a plasma display panel to enable stable operation at low temperatures.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a common sustain electrode 30Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. 20X is provided. Each of the scan electrode 30Y and the common sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one edge of the transparent electrode 13Y. , 13Z).

The transparent electrodes 12Y and 12Y are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in a direction crossing the scan electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a plurality of setup periods in which the rising ramp waveform is supplied and a set-down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

In Fig. 3, Y represents a scan electrode and Z represents a common sustain electrode. And X represents an address electrode.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp_up that rises to the peak voltage Vr higher than the sustain voltage level Vs is supplied to all the scan electrodes Y in the setup period. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain DC voltage of the sustain voltage level Vs is supplied to the common sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the common sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Sustain discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the common sustain electrode (Z) to erase wall charges in the cell.

However, in the conventional PDP driven as described above, bright point false discharge occurs when operating at a low temperature (approximately 20 ° C to -20 ° C). In other words, when the low temperature operating characteristics of the PDP according to the operating temperature, the bright point discharge is generated in the plurality of discharge cells. This bright spot discharge occurs because particle motion is slowed at low temperatures.

In detail, when the movement of particles is slowed at a low temperature, erasure discharge due to an erase ramp waveform (erase) may not be normally generated. In the cells in which the erase discharge is not normally generated, the wall charges formed on the scan electrode Y and the common sustain electrode Z are not erased.

Thereafter, a positive rising ramp waveform Ramp-up is supplied to the scan electrode Y during the setup period. At this time, since negative wall charges are formed on the scan electrode Y (that is, as shown in FIG. 4, the voltage applied to the scan electrode Y and the wall charges formed on the scan electrode Y have opposite polarities. Discharging normally does not occur during the set-up period. Therefore, no normal discharge occurs even in the setdown period following the setup period. As such, if normal discharge does not occur in the initialization period, wall charges excessively formed in the erasing period affect the address period and the sustain period. In other words, the wall discharges excessively formed in the discharge cells cause an undesired strong point discharge in the sustain period.

On the other hand, such bright spot mis-discharge is mainly generated in the discharge cells in which blue and green phosphors are formed. That is, since blue and green phosphors are set to have a discharge start voltage of approximately 20 to 30 V higher than that of the red phosphor, normal discharge does not occur in the initialization period, and thus, bright point discharge is generated.

Accordingly, it is an object of the present invention to provide a driving apparatus and a driving method of a PDP that enable stable operation at low temperatures.

In order to achieve the above object, the driving method of the PDP of the present invention is a driving method of a PDP in which the initialization period is divided into a setup period and a set-down period, the step of sensing the temperature of the PDP, and the temperature of the PDP is low temperature Supplying a first rising ramp waveform that rises to a first voltage during the set-up period when higher, and up to a second voltage for the scan electrode during the set-up period when the temperature of the PDP is driven at the low temperature; Supplying a rising second rising ramp waveform. The first rising ramp waveform is supplied to the scan electrode for a first time. The second rising ramp waveform is supplied to the scan electrode for a second time longer than the first time. The first rising ramp waveform and the second rising ramp waveform have the same slope. The second voltage is higher than the first voltage. The driving apparatus of the PDP of the present invention is a driving apparatus of a PDP in which an initialization period is divided into a setup period and a set-down period. And a control signal generator for generating a first rising ramp waveform rising to a first voltage to a scan electrode during the set-up period when the temperature of the PDP is higher than a low temperature in response to the control signal. And a scan driver for supplying a second rising ramp waveform rising to a second voltage to the scan electrode when the temperature is low. The temperature sensing unit generates different bit signals at low temperatures and temperatures higher than the low temperatures, and separates the low temperatures into a plurality of temperature levels to generate the bit signals.

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The bit signal is supplied to the control signal generator as an output signal of the temperature sensor. The control signal generation unit applies the control signal having a wider width as the ambient temperature decreases in response to the bit signal, and the scan driver supplies the rising ramp waveform to the scan electrode during the time that the control signal is supplied. do. The control signal generator applies the control signal having a wider width as the ambient temperature decreases corresponding to the bit signal. The scan driver supplies the rising ramp waveform to the scan electrode while increasing the voltage value in proportion to the width of the control signal. Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 7.

5 is a view showing a method of driving a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 5, in the PDP according to the embodiment of the present invention, a driving pulse supplied at a low temperature (about 20 ° C. to −20 ° C.) and a driving pulse supplied at a temperature higher than a low temperature are set differently.

First, when the PDP is driven at a temperature higher than the low temperature, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining the discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells. The rising ramp waveform Ramp-up is raised to the first peak voltage Vr1. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells.

The falling ramp waveform Ramp-down is supplied to the scan electrodes Y in the set down period. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

The common sustain electrodes Z are supplied with the positive DC voltage of the sustain voltage level Vs during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the common sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Sustain discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the common sustain electrode (Z) to erase wall charges in the cell.

On the other hand, when the PDP is driven at a low temperature (approximately 20 DEG C to -20 DEG C), the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. .

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. Here, the rising ramp waveform Ramp-up applied to the scan electrodes Y during the low temperature driving is increased to the second peak voltage Vr2 having a voltage value higher than the first peak voltage Vr1.

In detail, the rising ramp waveform Ramp-up supplied at a temperature higher than the low temperature and the rising ramp waveform Ramp-up supplied at a low temperature have the same slope. However, the rising ramp waveform Ramp-up is supplied for the first time T1 at a temperature higher than the low temperature. The rising ramp waveform Ramp-up at low temperature is supplied for a second time T2 longer than the first time T1 (that is, T2> T1). Therefore, the rising ramp waveform Ramp-up is supplied at a temperature higher than the low temperature. The voltage level of the peak voltage Vr2 of the rising ramp waveform Ramp-up supplied at a lower temperature than the peak voltage Vr1 of the ramp-up is set higher (that is, Vr2> Vr1).

As such, when the rising ramp waveform Ramp-up having the high peak voltage Vr2 is supplied to the scan electrode Y when the PDP is driven at a low temperature, a high voltage difference is generated between the scan electrode Y and the common sustain electrode Z. Can be generated and stable microdischarge in the cell.

During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain DC voltage of the sustain voltage level Vs is supplied to the common sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the common sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Sustain discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the common sustain electrode (Z) to erase wall charges in the cell.

FIG. 6 is a diagram illustrating a driving apparatus of a plasma display panel for supplying the waveform of FIG. 5.

Referring to FIG. 6, the driving apparatus of the PDP of the present invention includes a scan driver 40 for supplying a driving waveform to the scan electrode Y, a temperature sensing unit 42 for monitoring the ambient temperature of the panel, The control signal generator 44 is configured to generate a control signal corresponding to the driving temperature detected by the temperature sensor 42.

The scan driver 40 supplies the rising ramp waveform Ramp-up, the falling ramp waveform Ramp-down, the scan pulse and the sustain pulse sus to the scan electrode Y.

The temperature detector 42 supplies a bit signal to the control signal generator 44 while monitoring the ambient temperature at which the panel is driven. The control signal generator 44 supplies a control signal corresponding to the bit signal supplied from the temperature sensor 42 to the scan driver 40.

In detail, the temperature sensor 42 first supplies a predetermined bit, for example, a 4-bit signal, to the control signal generator 44. The temperature detector 42 supplies different bit signals to the control signal generator at a temperature lower than the low temperature and the low temperature.

For example, the temperature detector 42 supplies a bit signal of "0000" to the control signal generator 44 when the ambient temperature at which the panel is driven is a temperature higher than the low temperature (about 20 ° C or more). The control signal generator 44, which receives the bit signal of " 0000 " from the temperature sensor 42, supplies the control signal having the period T1 to the scan driver 40 as shown in FIG.

The scan driver 40 receiving the control signal having the period T1 from the control signal generator 44 supplies the rising ramp waveform Ramp-up to the scan electrode Y during the time T1 as shown in FIG. 5. At this time, the rising ramp waveform Ramp-up rises to the first peak voltage Vr1 and causes a plurality of fine discharges in the cell to form wall charges in the cell.

On the other hand, the temperature detector 42 supplies a bit signal of "0111" to the control signal generator 44 when the ambient temperature at which the panel is driven is driven at a low temperature, for example, 0 ° C. The control signal generator 44, which receives the bit signal of “0111” from the temperature sensor 42, supplies the control signal having the period T2 to the scan driver 40 as shown in FIG. 7.

The scan driver 40 receiving the control signal having the period T2 from the control signal generator 44 supplies the rising ramp waveform Ramp-up to the scan electrode Y during the time T2 as shown in FIG. 5. In this case, the rising ramp waveform Ramp-up rises to the second peak voltage Vr2 and causes a plurality of fine discharges in the cell to form wall charges in the cell. That is, in the present invention, when the PDP is driven at a low temperature, the voltage value of the rising ramp waveform Ramp-up is set high to stably set-up discharge in the cell.

Meanwhile, the temperature detector 42 supplies the bit signal higher than "0111" to the control signal generator 44 as the ambient temperature at which the panel is driven is lower than 0 ° C. The control signal generator 44, which receives a bit signal higher than "0111" from the control signal generator 44, supplies the scan driver 40 with a control signal having a wider period than that of T2. Similarly, the temperature detector 42 supplies the bit signal lower than " 0111 " to the control signal generator 44 as the ambient temperature at which the panel is driven is higher than 0 ° C. The control signal generator 44 which receives a bit signal lower than "0111" from the control signal generator 44 supplies the control signal having a period between T1 and T2 to the scan driver 40.

According to the present invention, a rising ramp waveform Ramp-up having a higher voltage value is supplied to the scan electrode Y as it is divided into a plurality of low-temperature levels, and as the level rises (the temperature decreases).

As described above, according to the driving apparatus and driving method of the plasma display panel according to the present invention, when the plasma display panel is driven at a low temperature, the application time of the rising ramp waveform is set longer than at a temperature higher than the low temperature (that is, high voltage). By applying a ramp ramp waveform with As such, when a stable setup discharge is generated in the plasma display panel driven at a low temperature, a false discharge in the form of a bright spot may be prevented.

 Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing one frame of a conventional AC surface discharge type plasma display panel.

3 is a waveform diagram showing a driving waveform supplied to electrodes during the subfield shown in FIG.

4 shows wall charges formed in the electrodes when no normal erase discharge has occurred.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention.

6 is a block diagram showing a driving apparatus of a plasma display panel according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a control signal generated by the control signal generator illustrated in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 30Y: scan electrode

30Z: common sustain electrode 40: scan driver

42: temperature detection unit 44: control signal generation unit

Claims (7)

A driving method of a plasma display panel in which an initialization period is driven divided into a setup period and a setdown period, Sensing a temperature of the plasma display panel; Supplying a first rising ramp waveform rising to a first voltage to a scan electrode during the set-up period when the temperature of the plasma display panel is higher than a low temperature; And supplying a second rising ramp waveform rising to a second voltage to the scan electrode during the setup period when the temperature of the plasma display panel is at the low temperature. The method of claim 1, The first rising ramp waveform is supplied to the scan electrode for a first time; The second rising ramp waveform is supplied to the scan electrode for a second time longer than the first time, And the first rising ramp waveform and the second rising ramp waveform have the same slope. The method of claim 1, And wherein the second voltage is higher than the first voltage. A driving apparatus of a plasma display panel in which an initialization period is driven divided into a setup period and a setdown period, A temperature sensing unit sensing a temperature of the plasma display panel; A control signal generator for generating a control signal in response to the output signal of the temperature sensor; In response to the control signal, when the temperature of the plasma display panel is higher than the low temperature, the first ramp ramp waveform rising to the first voltage is supplied to the scan electrode during the setup period, while the temperature of the plasma display panel is lower than the low temperature. And a scan driver for supplying a second rising ramp waveform rising to a second voltage to the scan electrode during the set-up period. The method of claim 4, wherein The temperature sensing unit generates different bit signals at a temperature lower than a low temperature and a low temperature, and separates the low temperature into a plurality of temperature levels to generate the bit signal. And the bit signal is supplied to the control signal generator as an output signal of the temperature sensor. The method of claim 5, The control signal generator applies the control signal having a wider width as the ambient temperature decreases in response to the bit signal. And the scan driver supplies the rising ramp waveform to the scan electrode during the time that the control signal is supplied. The method of claim 5, The control signal generator applies the control signal having a wider width as the ambient temperature decreases in response to the bit signal. And the scan driver supplies the rising ramp waveform to the scan electrode while increasing the voltage value in proportion to the width of the control signal.