KR100476338B1 - Method for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can stably drive the plasma display panel in a high temperature environment.

The driving method of the plasma display panel according to the present invention comprises the steps of applying a ramp waveform of the voltage rising during the setup period to the first electrode and applying a first positive DC voltage to the second electrode to cause the setup discharge in the discharge cell; A ramp waveform lowering at a voltage lower than the peak voltage of the ramp waveform is applied to the first electrode during the set down period, and a sustain voltage higher than the first positive DC voltage is supplied to the second electrode to set down in the discharge cell. Generating a discharge, applying a scan pulse to the first electrode during the address period, and supplying data to a third electrode crossing the first and second electrodes to cause an address discharge in the discharge cell; Applying a second positive DC voltage lower than the sustain voltage to the second electrode, during the sustain period; It is 1 and the sustain pulse of the sustain voltage to the second electrode alternately with a step that causes a sustain discharge in the discharge cell.

Description

Driving Method of Plasma Display Panel {METHOD FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel that can stably drive a plasma display panel in a high temperature environment.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP includes a sustain electrode pair including a scan electrode 30Y and a common sustain electrode 30Z formed on the upper substrate 10, and orthogonal to the sustain electrode pair. The address electrode 20X is formed on the lower substrate 18. Each of the scan electrode 30Y and the common sustain electrode 30Z has a structure in which transparent electrodes 12Y and 12Z and metal bus electrodes 13Y and 13Z are stacked. The upper dielectric layer 14 and the MgO passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 30Y and the common sustain electrode 30Z side by side. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. The initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling ramp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

In Fig. 3, Y represents a scan electrode and Z represents a common sustain electrode. And X represents an address electrode.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. This setup discharge accumulates positive wall charges on the address electrode X and the common sustain electrode Z, and negative wall charges on the scan / sustain electrode Y. After the rising ramp waveform Ramp-up is supplied in the set-down period SD, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The common sustain electrode Z is supplied with a positive DC voltage Zdc during the setdown period and the address period. The DC voltage Zdc causes the setdown discharge to occur between the common sustain electrode Z and the scan / sustain electrode Y in the setdown period and the space / charge generated by the address discharge during the address period. Y) and the common sustain electrode (Z). The accumulated space charges form wall charges, which help to generate the first sustain discharge during the sustain period.

In the sustain period, the sustain pulse SUS is applied to the scan electrodes Y and the common sustain electrodes Z alternately. The cell selected by the address discharge has a sustain discharge, i.e., between the scan / sustain electrode Y and the common sustain electrode Z each time the sustain pulse SUS is applied while the wall voltage and the sustain pulse SUS are added to the cell. , Display discharge occurs.

Finally, after the sustain discharge is completed, a ramp waveform (erase) having a small pulse width and a low voltage level is supplied to the common sustain electrode Z to erase wall charge remaining in the cells of the full screen.

However, when the conventional PDP is operated in a high temperature environment, misfiring occurs. The causes of the miss discharge are first, as the internal / external temperature of the cell rises, the insulation characteristics of the dielectric material and the protective layer material in the cell deteriorate, and leakage current occurs to leak wall charges. In particular, when the wall charges of the scan / sustain electrode Y and the common sustain electrode Z leak, the address discharge is likely to be miss discharged. Second, as the movement of the space charges in the cell caused by the discharge in the high temperature environment becomes active, recombination between the space charge and the electron-lost atom occurs easily, and the wall charges and space charges that contribute to the discharge have a long time. It is lost over time.

Accordingly, an object of the present invention is to provide a method for driving a plasma display panel that can stably drive a PDP in a high temperature environment.

In order to achieve the above object, the driving method of the PDP according to the embodiment of the present invention is to apply a ramp waveform of the voltage rising during the set-up period to the first electrode and to apply the first positive DC voltage to the second electrode discharge cell Causing a set-up discharge therein, and applying a ramp waveform lowering at a voltage lower than a peak voltage of the ramp waveform to the first electrode during a set-down period, and applying a sustain voltage higher than the first positive DC voltage to the second electrode. Supplying a set-down discharge in the discharge cell, applying a scan pulse to the first electrode during an address period, and supplying data to a third electrode crossing the first and second electrodes, thereby Applying a second positive DC voltage lower than the sustain voltage to the second electrode while causing an address discharge at Alternately applying sustain pulses of the sustain voltage to the first and second electrodes during the period to cause sustain discharge in the discharge cells. The driving method of the PDP further includes applying a erase pulse to the second electrode after the sustain period to erase the wall charges formed by the sustain discharge. The first positive DC voltage is within a range of 40V to 100V. The second positive DC voltage is approximately 90V.

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In the method of driving the plasma display panel, the falling ramp waveform and the second DC voltage are simultaneously applied to the first and second electrodes, respectively.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIG. 4.

4 illustrates a driving waveform of a PDP according to an embodiment of the present invention. Referring to FIG. 4, the PDP according to the embodiment of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the setup period SU, a rising ramp waveform Ramp-up that rises to a peak voltage higher than the sustain voltage Vs is applied to all the scan / sustain electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. This setup discharge accumulates positive wall charges on the address electrode X and the common sustain electrode Z, and negative wall charges on the scan / sustain electrode Y.

During the setup period SU, a first positive electrode having the same polarity as the rising ramp waveform Ramp-up is applied to the common sustain electrode Z simultaneously with the rising ramp waveform Ramp-up applied to the scan / sustain electrode Y. The polarity DC bias voltage Zdc1 is applied.

The voltage level of the first positive DC bias voltage Zdc1 is approximately 40V to 100V. Due to the first positive DC bias voltage Zdc1, the positive wall charges formed during the setup period SU are increased on the address electrode X, and on the common sustain electrode Z, compared to the conventional method shown in FIG. Less. Therefore, the wall voltage difference between the address electrode X and the common sustain electrode Z is increased by the setup discharge.

In the setdown period SD, a falling ramp waveform Ramp-down falling at a positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan / sustain electrode Y. The sustain voltage Vs is applied to the common sustain electrode Z during this set down period SD. This sustain voltage Vs has a level higher than the voltage level of the first positive DC bias voltage Zdc1.

In the set down period SD, the scan ramp sustain waveform is common to the scan / sustain electrode Y by the ramp ramp supplied to the scan / sustain electrode Y and the sustain voltage Vs supplied to the common sustain electrode Z. A set-down discharge, which is a dark discharge, is generated between the sustain electrodes Z, so that the scan / sustain electrode Y attracts positive ions and the common sustain electrode Z attracts electrons. As the set-down discharge proceeds, the negative wall charges on the scan / sustain electrode Y formed by the setup discharge and the positive wall charges on the common sustain electrode Z decrease. As a result, the wall charge polarity on the common sustain electrode Z is inverted and becomes negative at the end of the falling ramp waveform. Also, between the scan / sustain electrode Y and the address electrode X, a setdown discharge occurs in the form of a dark discharge at the end of the falling ramp waveform.

As a result of the discharge occurring during the setup period SU and the setdown period SD, an address discharge occurs when a scan pulse and a data pulse are applied to the scan / sustain electrode Y and the address electrode X. As much wall charges can be accumulated as possible. In addition, the amount of wall voltage of negative polarity increases in the common sustain electrode Z.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As a result, an address discharge is generated in the cell to which the data pulse is applied while the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added. During the address period, the level of the second positive DC bias voltage Zdc2 applied to the common sustain electrode Z is adjusted so that the gap voltage difference between the scan / sustain electrode Y and the common sustain electrode Z becomes approximately 0V. do. The second DC bias voltage Zdc2 is about 90V lower than the sustain voltage Vs, and prevents wall discharge loss due to a decrease in resistance of the protective layer material in a high temperature environment, thereby preventing failure of the address discharge.

The reason why the level of the second positive DC bias voltage Zdc2 is lower than the level of the sustain voltage Vs is that the falling ramp waveform Ramp- falls at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up. This is to prevent the discharge between the scan / sustain electrode (Y) and the common sustain electrode (Z) by lowering the voltage on the common sustain electrode (Z) as the wall voltage on the scan / sustain electrode (Y) becomes lower due to the lowering). . For this reason, in the initialization period, the negative voltage accumulated in the common sustain electrode Z is kept stable.

Accordingly, in the address period, the common sustain electrode Z and the scan / sustain electrode Y become voltage levels at which discharge can occur at a low discharge voltage, and the scan / sustain electrode Y and the address electrode X are discharged. The voltage level is lower than the voltage.

In the sustain period, a sustain pulse SUS of the sustain voltage Vs is applied to the scan / sustain electrode Y and the common sustain electrode Z alternately. The cell selected by the address discharge has a sustain discharge, i.e., between the scan / sustain electrode Y and the common sustain electrode Z whenever the sustain pulse SUS is applied while the wall voltage and the sustain pulse SUS are added to the cell. , Display discharge occurs.

In this sustain period, when the first sustain pulse is applied, the interval between the scan / sustain electrode Y and the common sustain electrode Z by the negative wall voltage accumulated on the common sustain electrode Z in the reset period and the address period. Since the voltage can be reduced, discharge can occur more easily. Therefore, when the PDP is driven in a high temperature environment, the discharge of the cell can be prevented.

After the sustain discharge is completed, the wall charges generated during the sustain discharge are erased by the small ramp waveform (erase) supplied to the common sustain electrode (Z).

The driving method of the plasma display panel according to the exemplary embodiment of the present invention applies the first DC bias voltage Zdc1 having a constant voltage level to the common sustain electrode Z during the setup period SU. The amount of positive wall voltage accumulated in Z is increased to increase the amount of positive wall voltage accumulated in the address electrode X, and the first DC bias low voltage Zdc1 is applied to the common sustain electrode Z in the set-down period SD. A higher sustain voltage (Vs) is applied to increase the accumulation amount of the negative wall voltage on the common sustain electrode (Z), and the gap voltage between the scan / sustain electrode (Y) and the common sustain electrode (Z) in the address period. By applying the second positive DC bias voltage Zdc2 to the common sustain electrode Z so as to be 0 V, address discharge and sustain discharge can be easily generated. Accordingly, it is possible to prevent miss discharge generated when the PDP is driven in a high temperature environment.

As described above, the driving method of the PDP according to the present invention prevents the loss of wall charges during the address period and increases the negative wall charges formed on the common sustain electrode immediately before the sustain period. It is possible to drive PDP stably in high temperature environment.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing driving waveforms for driving a conventional plasma display panel.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan electrode

30Z: common sustain electrode

Claims (7)

In a driving method of a plasma display panel divided into an initialization period divided into a setup period and a set down period, and an address period and a sustain period, Applying a ramp waveform of increasing voltage during the setup period to the first electrode and applying a first positive DC voltage to the second electrode to cause a setup discharge in the discharge cell; During the set down period, a ramp waveform lowering at a voltage lower than the peak voltage of the ramp waveform is applied to the first electrode, and a sustain voltage higher than the first positive DC voltage is supplied to the second electrode in the discharge cell. Causing a set-down discharge, During the address period, a scan pulse is applied to the first electrode and data is supplied to a third electrode crossing the first and second electrodes, thereby causing an address discharge in the discharge cell and lowering the sustain voltage. Applying a positive DC voltage to the second electrode; And alternately applying sustain pulses of the sustain voltage to the first and second electrodes during the sustain period to cause a sustain discharge in the discharge cell. The method of claim 1, And erasing wall charges formed by the sustain discharge by applying an erase pulse to the second electrode subsequent to the sustain period. The method of claim 1, And the first positive DC voltage is within a range of 40V to 100V. delete delete The method of claim 1, And said second positive DC voltage is approximately 90V. delete