KR100482338B1 - Driving method and apparatus of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus of a plasma display panel that can be stably operated even at a high temperature.

The driving apparatus of the plasma display panel of the present invention is connected to the sustain driving unit and includes a DC power supply unit having a plurality of DC voltage sources for determining the voltage level of the DC voltage, and sensing the ambient temperature at which the panel is driven and according to the ambient temperature. And a control unit for controlling the DC power supply unit so that the voltage of any one of the DC voltage sources can be supplied to the sustain driver.

Description

DRIVING METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

The present invention relates to a driving apparatus and a driving method of a plasma display panel, and more particularly, to a driving apparatus and a driving method of a plasma display panel that can be stably operated even at high temperature.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP includes a sustain electrode pair including a scan electrode 30Y and a common sustain electrode 30Z formed on the upper substrate 10, and orthogonal to the sustain electrode pair. The address electrode 20X is formed on the lower substrate 18. Each of the scan electrode 30Y and the common sustain electrode 30Z has a structure in which transparent electrodes 12Y and 12Z and metal bus electrodes 13Y and 13Z are stacked. The upper dielectric layer 14 and the MgO passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 30Y and the common sustain electrode 30Z side by side. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. The initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling ramp waveform is supplied.

For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

In Fig. 3, Y represents a scan electrode and Z represents a common sustain electrode. And X represents an address electrode.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the common sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. After the rising ramp waveform Ramp-up is supplied in the set-down period SD, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The common sustain electrode Z is supplied with a positive DC voltage Zdc during the setdown period and the address period. The direct current voltage Zdc causes set-down discharge between the common sustain electrode Z and the scan electrode Y in the set-down period, and opposes generated between the scan electrode Y and the address electrode X in the address period. The discharge is transferred to the surface discharge between the scan electrode Y and the common sustain electrode Z.

This will be described in detail with reference to FIG. 4 as follows. In the address period, a negative scan pulse scan is applied to the scan electrode Y, and a positive data pulse data synchronized with the scan pulse scan is applied to the address electrode X. In addition, the positive pole DC voltage Zdc is applied to the common sustain electrode Z. At this time, the opposite discharge is generated between the scan electrode Y and the address electrode X by the scan pulse and the data pulse data. By such counter discharge, positive wall charges (+) are formed on the scan electrode (Y), and negative wall charges (-) are formed on the address electrode (X).

In addition, surface discharge is generated between the scan electrode Y and the common sustain electrode Z by the DC voltage Zdc applied to the common sustain electrode Z. At this time, a negative wall charge (-) is formed on the common sustain electrode Z. On the other hand, the DC voltage Zdc applied to the common sustain electrode Z is supplied during the address period to prevent the disappearance of the negative wall charges (−) formed on the common sustain electrode Z.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, i.e., a display between the scan electrode Y and the common sustain electrode Z every time the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. Discharge occurs.

Finally, after the sustain discharge is completed, a ramp waveform (erase) having a small pulse width and a low voltage level is supplied to the common sustain electrode Z to erase wall charge remaining in the cells of the full screen.

However, the conventional PDP has a problem in that driving is unstable, such as discharge does not occur when operating in a high temperature environment. For example, when the PDP is divided into the upper half and the lower half as shown in FIG. 5 and the upper half is scanned from the top and the bottom half is scanned at the same time as the upper half and the upper half as shown in FIG. Discharge does not occur. If no address discharge occurs in the selected cell in this way, the image cannot be displayed because the sustain discharge does not occur in the selected cell even when the sustain voltage is applied. Similarly, when the PDP is sequentially scanned from the first line to the last line as shown in FIG. 6 at a high temperature of about 40 ° C. or higher, no address discharge occurs in the lower portion 51 of the screen having a late scanning order.

As a result of many experiments and analysis of the experiments, the main cause of miss discharge in high temperature environment is that the later the scanning sequence increases the amount of wall charges generated during the initialization period increases. The reason for this is explained based on the change of discharge characteristics in the cell. First, as the internal / external temperature of the cell rises, the insulation characteristics of the dielectric material and the protective layer material in the cell deteriorate, and leakage current occurs and the wall charges leak. . In particular, when the wall charges of the scan electrode Y and the common sustain electrode Z leak, the address discharge is likely to be miss discharged.

Second, as the movement of space charges in a cell caused by discharge in high temperature environment becomes active, recombination of the space charge and the electron-lost atom easily occurs, so that wall charge and space charge that contribute to discharge have a long time. It is lost over time.

Accordingly, an object of the present invention is to provide a driving apparatus and a driving method of a plasma display panel which can be stably operated even at high temperature.

In order to achieve the above object, the driving apparatus of the plasma display panel according to the present invention is connected to a sustain driving unit and detects a DC power supply unit having a plurality of DC voltage sources for determining a voltage level of DC voltage, and an ambient temperature at which the panel is driven. And a control unit for controlling the DC power supply unit so that the voltage of any one of the DC voltage sources can be supplied to the sustain driving unit according to the ambient temperature.

The DC power supply unit includes a plurality of switching elements which are respectively installed between the DC voltage sources and the sustain driver and turned on and off under the control of the controller.

The control unit; A temperature sensing unit for sensing an ambient temperature at which the panel is driven and generating a bit control signal corresponding thereto; And a switch controller for turning on any one of the plurality of switching elements in response to the bit control signal.

The temperature sensing unit generates different bit control signals at room temperature and high temperature, and separates the temperature of the high temperature environment into a plurality of temperature levels to generate the bit control signal.

The switch controller controls the switching elements such that a DC voltage having a high voltage can be supplied as the ambient temperature increases in response to the bit control signal.

The initialization period is a set down period.

In the method of driving the plasma display panel of the present invention, the voltage level of the DC voltage supplied at a high temperature is different from that of the DC voltage supplied at a temperature below the high temperature.

The voltage level of the DC voltage supplied at the high temperature is set higher than the voltage level of the DC voltage supplied at the temperature below the high temperature.

The high temperature is divided into a plurality of temperature levels, and the higher the temperature level, the higher the voltage level of the DC voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 9B.

7 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 7, a driving device of a PDP according to an embodiment of the present invention includes a data driver 62 for supplying data to address electrodes X1 to Xm and an initialization voltage to scan electrodes Y1 to Ym. And a scan driver 64 for supplying the scan voltage and the sustain voltage, a sustain driver 66 for supplying the positive DC voltage and the sustain voltage to the common sustain electrode Z, and each of the drivers 62, 64, and 66. ), A DC power supply 70 for supplying a different DC voltage to the sustain driver 66 according to the ambient temperature at which the panel 61 is driven, and the panel 61 are driven. A control unit 68 is provided for measuring the ambient temperature and controlling the DC power supply unit 70 accordingly.

The data driver 62 performs inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then outputs data mapped to each subfield by a subfield mapping circuit (not shown). After latching by one line under the control of, the latched data is simultaneously supplied to the address electrodes X1 to Xm.

The scan driver 64 supplies the rising ramp waveform and the falling ramp waveform to the scan electrodes Y1 to Ym in the initialization period, and then scans the scan pulses for selecting the scan line in the address period. Feed sequentially. The scan driver 64 simultaneously supplies sustain pulses to the scan electrodes Y1 to Ym to cause sustain discharge for the selected cell in the address period.

The sustain driver 66 supplies a DC voltage in the set down period and the address period, and also supplies a sustain pulse in the sustain period. Here, the sustain driver 66 increases the voltage level of the DC voltage to supply the common sustain electrode Z when the panel 61 is driven in a high temperature environment (approximately 90 ° C. or less) of about 40 ° C. or higher. As such, when the voltage level of the DC voltage is increased in a high temperature environment, the intensity of the address discharge is increased, thereby reducing the high temperature false discharge.

The timing controller 60 receives a vertical / horizontal synchronization signal to generate a timing control signal for each driver 62, 64, 66, and supplies the timing control signal to each driver 62, 64, 66. .

The controller 68 controls the DC power supply 70 while monitoring the ambient temperature at which the panel is driven. The DC power supply unit 70 supplies a predetermined DC voltage to the sustain driver 66 under the control of the controller 68.

To this end, the control unit 68 includes a temperature sensing unit 72 and a switch control unit 74 as shown in FIG. 8, and the DC power supply unit 70 includes a plurality of DC voltage sources Vs1, Vs2,... , Vsi) and switching elements Sw1, Sw2, ..., Swi.

Here, the voltage values of the DC voltage sources Vs1, Vs2, ..., Vsi included in the DC power supply unit 70 correspond to the conventional DC voltages (voltages supplied to the common sustain electrode Z in the setdown period and the address period). It is set to gradually increase from the voltage level. For example, Vs1 is set equal to the voltage level of the conventional DC voltage. In addition, the voltage level of Vs2 is set higher than the voltage level of Vs1. Similarly, the voltage level of Vsi is set higher than the voltage level of Vs2.

The switching elements Sw1, Sw2, ..., Swi are respectively installed between the DC voltage sources Vs1, Vs2, ..., Vsi and the sustain driver 66 to be turned on and turned under the control of the switch controller 74. -Off.

The temperature sensing unit 72 supplies a predetermined bit control signal to the switch control unit 74 while monitoring the ambient temperature at which the panel 61 is driven. For example, the temperature detector 72 may supply a 4-bit control signal to the switch controller 74.

Referring to the operation process in detail, first, the temperature sensing unit 72 generates a predetermined bit control signal, for example, a control signal of " 0000 " Supply to the switch control part 74 is carried out. The switch control unit 74 receiving the control signal of "0000" from the temperature sensing unit 72 turns on the first switch Sw1. At this time, the sustain driver 66 is supplied with a DC voltage of Vs1.

Therefore, the sustain driver 66 supplies the positive DC voltage Zdc having the voltage level of Vs1 in the setdown period SD and the address period as shown in FIG. 9A. As described above, the DC voltage Zdc is supplied to form a predetermined wall of the common sustain electrode Z as shown in FIG. 4. Meanwhile, in the address period, a negative scan pulse su is supplied to the scan electrode Y, and a data pulse data is supplied to the address electrode X to form a predetermined wall charge as shown in FIG. Thereafter, a sustain pulse su is supplied to the scan electrode Y and the common sustain electrode Z in the sustain period, so that a predetermined image of the panel 61 is displayed.

On the other hand, the temperature sensing unit 72 supplies a predetermined bit control signal, for example, a control signal of "0001" to the switch control unit 74 when the panel 61 is operated at the first high temperature (approximately 42 ° C). . The switch control unit 74 which receives the bit control signal of “0001” from the temperature sensing unit 72 turns on the second switch Sw2. At this time, the sustain driver 66 is supplied with a DC voltage of Vs2.

Accordingly, the sustain driver 66 supplies a positive DC voltage Zdc2 having a voltage level higher than the voltage level of Vs1, that is, the voltage level of Vs2, as shown in FIG. 9B in the setdown period SD and the address period. In this way, when a positive DC voltage having a high voltage level is supplied, the intensity of the address discharge generated during the address period becomes large. In other words, by supplying a positive DC voltage Zdc2 having a high voltage level in a high temperature environment, it is possible to compensate for the loss of the initial wall charges, thereby preventing the high temperature mis-discharge.

On the other hand, in the present invention, the high temperature is divided into a plurality of levels to drive. At this time, as the level is increased, that is, the temperature is increased, a high-temperature mis-discharge is prevented by supplying a DC voltage having a high voltage level to the common sustain electrode. In other words, when the ambient temperature at which the panel 61 is driven rises higher than the first high temperature, a DC voltage having a voltage level higher than the voltage level of Vs2 is supplied to the sustain driver 66 to prevent high temperature mis-discharge. .

As described above, according to the plasma display panel and the driving method thereof according to the present invention, the recombination of wall charges is prevented by setting the voltage level of the DC voltage supplied to the common sustain electrode higher during the set down period and the address period as the temperature increases. Thereby, high temperature misdischarge can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a conventional three-electrode AC surface discharge type plasma display panel.

2 is a view showing one frame of a conventional AC surface discharge type plasma display panel.

3 is a waveform diagram showing a driving waveform supplied to electrodes during the subfield shown in FIG.

4 shows wall charges formed in electrodes during an address period.

5 and 6 are diagrams showing regions in which mis-discharge is generated in a high-temperature environment in a conventional plasma display panel.

7 is a view showing a driving device of a plasma display panel according to an embodiment of the present invention.

8 is a view illustrating in detail the control unit and the DC power supply unit shown in FIG.

9A and 9B are diagrams showing voltage levels of a DC voltage supplied to a common sustain electrode according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 30Y: scan electrode

30Z: common sustain electrode 60: timing controller

61 panel 62 data driver

64: scan driver 66: sustain driver

68 control unit 70 DC power supply unit

72: temperature detection unit 74: switch control unit

Claims (9)

A plasma display panel comprising a sustain driver for supplying a DC voltage to a common sustain electrode for at least one of an initialization period and an address period. A DC power supply unit connected to the sustain driving unit and having a plurality of DC voltage sources for determining a voltage level of the DC voltage; And a control unit for sensing the ambient temperature at which the panel is driven and controlling the DC power supply unit so that the voltage of any one of the DC voltage sources can be supplied to the sustain drive unit according to the ambient temperature. A driving device of the plasma display panel. The method of claim 1, And the DC power supply unit includes a plurality of switching elements installed between the DC voltage sources and the sustain driver to be turned on and off under the control of the controller. The method of claim 2, The control unit; A temperature sensing unit for sensing an ambient temperature at which the panel is driven and generating a bit control signal corresponding thereto; And a switch controller for turning on any one of the plurality of switching elements in response to the bit control signal. The method of claim 3, wherein The temperature sensing unit generates a bit control signal different from each other in a room temperature and a high temperature environment, and separates the temperature of the high temperature environment into a plurality of temperature levels to generate the bit control signal. The method of claim 4, wherein And the switch controller controls the switching elements such that a DC voltage having a high voltage is supplied as the ambient temperature increases in response to the bit control signal. The method of claim 1, And the initialization period is a set down period. A method of driving a plasma display panel comprising supplying a DC voltage to a common sustain electrode for at least one of an initialization period and an address period. And the voltage level of the DC voltage supplied at a high temperature is set higher than the voltage level of the DC voltage supplied at a temperature below the high temperature. delete The method of claim 7, wherein Wherein the high temperature is divided into a plurality of temperature levels, and the higher the temperature level is, the higher the voltage level of the DC voltage is.