KR20050021861A - Apparatus for driving plasma display panel - Google Patents

Abstract

PURPOSE: A driving apparatus of a plasma display panel is provided to drive the PDP stably even though temperature is varied, by varying a driving waveform of the PDP adaptively to temperature variation. CONSTITUTION: A temperature sensor senses temperature of a plasma display panel(PDP). A controller generates a temperature control signal according to the temperature sensed by the temperature sensor. Voltage sources(-V1,-V2) generate a negative voltage. A voltage control circuit controls a voltage supplied to the plasma display panel in response to the temperature control signal.

Description

Driving device for plasma display panel {APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a plasma display panel, and more particularly to a method and apparatus for driving a plasma display panel.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

2 illustrates a driving waveform for driving the PDP as shown in FIG. 1.

Referring to FIG. 2, at the beginning of the reset period, a rising ramp waveform Rup in which the voltage gradually rises from the sustain voltage Vs to the setup voltage Vsetup is applied to all the scan electrodes Y simultaneously. While the rising ramp waveform Rup is supplied to the scan electrodes Y, 0 [V] is applied to the sustain electrodes Z and the address electrodes X. The setup discharge causing the formation of wall charges between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen by the rising ramp waveform (Rup). Happens. Following the rising ramp waveform Rup, a falling ramp waveform Rdn is applied to the scan electrodes Y simultaneously, in which the voltage falls from the sustain voltage Vs to the negative bias voltage -Vy. While the falling ramp waveform Rdn is supplied to the scan electrodes Y, a positive sustain voltage Vs is applied to the sustain electrodes Z, and 0 [V] is applied to the address electrodes X. . Due to the falling ramp waveform Rdn, almost no light is generated between the scan electrode Y and the sustain electrode Z, and a set-down discharge occurs as an erase dark discharge that causes the wall charges to be erased. As a result of this set-down discharge, excess wall charges are erased among the wall charges accumulated on each electrode (X, Y, Z) during setup discharge, so that wall charges remain uniformly in all cells.

On the other hand, if the negative bias voltage (-Vy), which is the lower limit voltage of the falling ramp waveform Rdn, is not set too low and is properly set, the wall charges remaining in the cell increase, so that the cell can be selected at a low address voltage even at high temperatures. .

In the address period, the scan pulse scp that drops to the negative scan bias voltage Vsc-bias is sequentially applied to the scan electrodes Y and the positive data voltage Vd synchronized with the scan pulse scp. Is applied to the address electrodes (X). As the voltage difference between the scan pulse scp and the data pulse dp and the wall voltage in the cell initialized in the reset period are added, an address discharge is generated in the cell to which the data pulse dp is applied.

During the address period, the sustain electrodes V are supplied with a positive sustain voltage Vs.

In the sustain period, the sustain pulse sus of the sustain voltage Vs is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain voltage Vs in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z at each sustain pulse su.

After the sustain discharge is completed, an erase ramp waveform ers gradually increasing to the sustain voltage Vs during the erase period is applied to the sustain electrodes Z. 0V is applied to the scan electrodes Y and the address electrodes X during this erase period. The erase ramp waveform ers erases wall charges remaining in the cell by the sustain discharge by causing an erase discharge between the scan electrode Y and the sustain electrode Z. FIG.

PDP has a problem in that the discharge characteristics become incomplete as the temperature changes. This is due to the change in the pressure in the cell due to the temperature change and the discharge voltage due to the pressure change. The discharge voltage Vf may be defined as in Equation 1 below.

Vf = p × d

Where p is pressure and d is the distance between electrodes.

When the temperature of the PDP is higher than the optimum temperature corresponding to the normal driving waveform, the pressure in the discharge cell rises and the discharge voltage Vf increases due to the pressure rise. In this case, when the PDP is driven with a normal driving voltage, it is easy to cause a miss discharge in which no discharge occurs. On the contrary, when the temperature of the PDP is lowered, the pressure in the discharge cell drops and the discharge voltage Vf decreases due to the pressure drop. In this case, when the temperature is lowered, driving the PDP with a normal driving voltage is likely to cause an erroneous discharge in which a discharge occurs in a discharge cell in which discharge should not occur.

The change in discharge characteristics with temperature can be interpreted as due to the following causes. As the ambient temperature of the PDP rises, the space charge in the cell becomes active, and recombination with other space charge or wall charge occurs. As the amount of recombination of space charge and wall charge increases, the wall voltage of the cell decreases. The decrease in the wall voltage causes an increase in the discharge voltage. On the contrary, when the ambient temperature of the PDP decreases, the amount of recombination between the space charge and the wall charge decreases, so that the wall voltage of the cell increases. An increase in the wall voltage causes a drop in the discharge voltage.

On the other hand, if the height of the partition wall is uneven, the uniformity (uniformity) of the door cells falls (stable drive at room temperature and high temperature can not be performed.

In order to solve the problem that the discharge characteristics become unstable with respect to the temperature change, methods for changing the driving voltage of the driving waveform in response to the temperature change have been proposed. One of them is a method of increasing or decreasing the pulse widths of the scan pulse scp and the data pulse dp as shown in FIG. 3. As another method, as shown in FIG. 4, the voltage Vsetup of the rising ramp waveform Rup is increased or decreased with temperature.

However, when the scan time tsc is increased as shown in FIG. 3, the address period becomes longer, so that the sustain period, which is the display period, becomes relatively short, and thus the luminance is reduced. In addition, if the address period becomes longer, the driving time is insufficient, so that the method shown in FIG. 3 cannot cope with high resolution, and it is difficult to divide or add subfields in order to reduce image quality deterioration factors such as moving picture noise.

As shown in FIG. 4, the method of varying the setup voltage Vsetup according to temperature changes the wall charges accumulated on the electrodes X, Y, and Z during setup discharge due to a change in the setup voltage Vsetup. Since -Vy) is fixed, the amount of erasing during set-down discharge becomes constant. As a result, the initialization of the cells may be uneven by the method as shown in FIG. 4. In particular, since the wall charge initialization in the cell depends on the set-down discharge, if only the setup voltage Vsetup is changed as shown in FIG. 4, the discharge characteristic may become more unstable.

Accordingly, an object of the present invention is to provide a driving method and apparatus for stably driving the PDP even when the temperature is changed by adaptively varying the driving waveform of the PDP.

In order to achieve the above object, the driving device of the PDP according to an embodiment of the present invention and the temperature sensor for sensing the temperature of the PDP; A controller for generating a temperature control signal in accordance with the temperature sensed by the temperature sensor; A voltage source for generating a negative voltage; And a voltage control circuit for adjusting the voltage supplied to the PDP in response to the temperature control signal.

The voltage source comprises a first voltage source for generating a first voltage; And a second voltage source for generating a second voltage.

The driving device of the PDP further includes a driving element for supplying a voltage from the voltage sources to the PDP under the control of the voltage control circuit.

The first voltage source and the second voltage source are connected in series with the drive element.

The voltage control circuit includes a switch element for selectively forming a current path between any one of the first voltage source and the second voltage source, and generates a control signal for controlling the drive element and the switch element. Characterized in that.

The first voltage source and the second voltage source are connected in parallel to the driving element.

The voltage control circuit includes a first switch element for selectively forming a current path between the first voltage source and the driving element; And a second switch element for selectively forming a current path between the second voltage source and the drive element, and generating a control signal for controlling the drive element and the switch element.

The voltage supplied to the PDP may be an initialization voltage for initialization.

The initialization voltage is supplied to the PDP as a falling ramp waveform in which the voltage gradually falls.

Each of the voltage sources is a zener diode.

The driving device of the PDP further includes a negative voltage source for supplying a negative voltage to the zener diode.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 8.

Referring to FIG. 5, in the driving method of the PDP according to the embodiment of the present invention, the PDP is driven by time-dividing one frame period into a plurality of subfields, and a falling ramp waveform for inducing set-down discharge in at least one subfield ( The voltage of Rdn) changes with temperature.

At the beginning of the reset period, a rising ramp waveform Rup in which the voltage gradually rises from the sustain voltage Vs to the setup voltage Vsetup is applied to all the scan electrodes Y simultaneously. While the rising ramp waveform Rup is supplied to the scan electrodes Y, 0 [V] is applied to the sustain electrodes Z and the address electrodes X. Due to the rising ramp waveform Rup, almost no light is generated between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. A setup discharge occurs with a write dark discharge that causes As a result of this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

Following the rising ramp waveform Rup, the falling ramp waveform Rdn, in which the voltages -Vy1 and -Vy2 vary depending on the temperature of the PDP, is simultaneously applied to the scan electrodes Y. While the falling ramp waveform Rdn is supplied to the scan electrodes Y, 0V is applied to the address electrodes X, and positive voltages Vz1, Vs, which vary with temperature to the sustain electrodes Z. Vz2) is applied. Due to the falling ramp waveform Rdn, almost no light is generated between the scan electrode Y and the sustain electrode Z, and a set-down discharge occurs as an erase dark discharge that causes the wall charges to be erased. As a result of this set-down discharge, excess wall charges are erased among the wall charges accumulated on each electrode (X, Y, Z) during setup discharge, so that wall charges remain uniformly in all cells.

Looking at the change in the wall charge distribution during the setup discharge and the setdown discharge, the positive wall charges on the address electrode X formed during the setup discharge are almost unchanged during the setdown discharge. The negative wall charges on the scan electrode Y, which were formed during the setup discharge, are partially reduced by the setdown discharge. The wall charges on the sustain electrode (Z) have positive wall charges at the time of setup discharge, but the negative polarity of the wall charges is accumulated as the decrease of the negative wall charge of the scan electrode (Y) during the set-down discharge. Is reversed.

The voltage application period and the voltage level of the falling ramp waveform Rdn varying with temperature during setdown discharge correct the discharge characteristics of the PDP that become unstable when the temperature changes. When the temperature of the PDP is higher than the normal use temperature, the pressure in the cell increases, the discharge voltage Vf increases, and the amount of recombination between the space charge and the wall charge in the cell increases. As the wall charges become smaller in this way, misdischarge that does not occur in a cell to which an address voltage, that is, a data voltage and a scan voltage are applied, is likely to occur. The driving method of the PDP according to the embodiment of the present invention weakens the discharge discharge between the scan electrode (Y) and the sustain electrode (Z) by lowering the voltage of the falling ramp waveform (Rdn) to only -Vy1 voltage in a high temperature environment. That is, in the high temperature environment, the set-down bias voltage between the lower limit voltage of the falling ramp waveform Rdn and the scan bias voltage Vsc-bias is adjusted to -Vy1 voltage. When the erase discharge is weakly generated, the wall charge and the space charge remaining in the cell increase, so that the discharge can be stably generated in a high temperature environment.

On the contrary, when the temperature of the PDP is lower than the normal use temperature, the pressure in the cell is lowered, the discharge voltage Vf is lowered, and the amount of recombination between the space charge and the wall charge in the cell is reduced. The driving method of the PDP according to the embodiment of the present invention erases between the scan electrode (Y) and the sustain electrode (Z) by increasing the voltage application period of the falling ramp waveform (Rdn) or lowering the voltage level to -Vy2 in a low temperature environment. Strongly induce discharge. When the erase discharge is strongly generated, the wall voltage and the space charge in the cell are lowered, so that the discharge can be stably generated even when the discharge voltage is lowered at low and room temperature.

In the address period, the scan pulse scp of the scan voltage Vsc, which falls to the scan bias voltage Vsc-bias, is sequentially applied to the scan electrodes Y, and the positive data synchronized with the scan pulse scp. The data pulse dp of the voltage Vd is applied to the address electrodes X. As the voltage difference between the scan pulse scp and the data pulse dp and the wall voltage in the cell initialized in the reset period are added, an address discharge is generated in the cell to which the data pulse dp is applied. In the cells selected by the address discharge, wall charges are generated to the extent that discharge can occur when the sustain voltage Vs is applied.

The positive sustain voltage Vs is supplied to the sustain electrodes Z so that the negative wall charges do not disappear on the sustain electrodes Z during the address period.

In the sustain period, the sustain pulse sus of the sustain voltage Vs is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain voltage Vs in the cell are added, a sustain discharge occurs between the scan electrode Y and the sustain electrode Z at each sustain pulse su.

After the sustain discharge is completed, an erase ramp waveform ers gradually increasing to the sustain voltage Vs during the erase period is applied to the sustain electrodes Z. 0V is applied to the scan electrodes Y and the address electrodes X during this erase period. The erase ramp waveform ers erases wall charges remaining in the cell as a result of the sustain discharge by causing an erase discharge between the scan electrode Y and the sustain electrode Z. FIG.

6 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 6, a driving apparatus of a PDP according to an embodiment of the present invention includes a temperature sensor 6 for sensing a temperature of the PDP, and a data driver for supplying data to address electrodes X1 to Xm of the PDP. (2), the scan driver 3 for driving the scan electrodes Y1 to Yn, the sustain driver 4 for driving the sustain electrodes Z differently according to the temperature of the PDP, and each driver ( A timing controller 1 for controlling 2, 3, and 4 and a driving voltage generator 5 for supplying driving voltages to the driving units 2, 3, and 4 are provided.

The temperature sensor 6 is installed at a position close to the PDP to sense the temperature of the PDP in real time. A temperature sensor driving circuit (not shown) for driving the temperature sensor 66 generates a temperature sensing signal St and supplies the temperature sensing signal St to the timing controller 1.

The data driver 2 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like not shown, and then data mapped to the subfield pattern for each bit is supplied by the subfield mapping circuit. The data driver 2 samples and latches data under the control of the timing controller 1, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 3 supplies the rising ramp waveform Rup during the reset period as shown in FIG. 5 under the control of the timing controller 1, and then scans the falling ramp waveform Rdn whose voltage varies depending on temperature. Yn). The scan driver 3 sequentially supplies the scan pulse scp to the scan electrodes Y1 to Yn during the address period. The scan driver 3 supplies the sustain pulse sus to the scan electrodes Y1 to Ym during the sustain period under the control of the timing controller 1.

The sustain driver 4 supplies the positive bias voltage to the sustain electrodes Z during the application period and the address period of the falling ramp waveform Rdn under the control of the timing controller 1. The sustain driver 4 alternately operates with the scan driver 3 during the sustain period under the control of the timing controller 1 to supply the sustain pulse su to the sustain electrodes Z. FIG.

The timing controller 1 receives the vertical / horizontal synchronization signals and generates timing control signals CTRX, CTRY, and CTRZ required for each of the driving units 62, 63, and 64, and generates the timing control signals CTRX, CTRY, and CTRZ. Each of the driving units 2, 3, and 4 is controlled by supplying the driving units 2, 3, and 4 to the corresponding driving units. In particular, the timing controller 1 controls the scan driver 3 so that the voltage of the falling ramp waveform Rdn varies depending on the temperature of the PDP in response to the temperature sensing signal St from the temperature sensor 6. The timing control signal CTRX supplied to the data driver 2 includes a sampling clock for sampling data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The timing control signal CTRY applied to the scan driver 3 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the scan driver 3. The timing control signal CTRZ applied to the sustain driver 4 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the sustain driver 4.

The driving voltage generator 5 generates a setup voltage Vsetup, a scan bias voltage Vsc-bias, a scan voltage Vsc, a data voltage Vd, a sustain voltage Vs, and the like of the rising ramp waveform. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

7 to 10 are circuit diagrams illustrating embodiments of the falling ramp signal generation circuit included in the scan driver 3.

7, the falling ramp signal generation circuit according to the first embodiment of the present invention includes a variable resistor VR and a capacitor C connected to the gate terminal of the N-channel MOSFET T, and an N-channel MOSFET T. ) And the first and second voltage sources (-V1, -V2) connected in series between the base voltage source (GND) and the switch element (SW) connected at both ends of the second voltage source (V2).

The variable resistor VR is connected between the gate terminal of the N-channel MOSFET T and the first control signal terminal 71 to which the set-down control signal Sd (CTRY) is supplied. The capacitor C is connected between the gate terminal and the source terminal of the N-channel MOSFET T. The set-down control signal Sd (CTRY) whose voltage gradually changes is applied to the gate terminal of the N-channel MOSFET T by the RC time constant due to the combination of the variable resistor VR and the capacitor C. FIG. Therefore, while the setdown control signal is applied to the first control terminal 71, the current flowing between the source terminal and the drain terminal through the channel of the N-channel MOSFET T gradually increases due to the RC time constant.

The first and second voltage sources V1 and V2 are respectively connected in series between the N-channel MOSFET T and the ground voltage source GND as direct current voltage sources.

The switch element SW selectively short-circuits both ends of the second voltage source -V2 in response to the temperature control signal St (CTRY) applied through the second control terminal 72, thereby reducing the falling ramp waveform Rdn. Adjust the lower limit voltage.

When the switch element SW is opened, a sum voltage of the voltage of the first voltage source -V1 and the voltage of the second voltage source -V2 is supplied to the source terminal of the N-channel MOSFET T. The output voltage of the first voltage source -V1 and the second voltage source -V2 is set such that the sum voltage is represented by the voltage -Vy1. For example, when the first voltage source -V1 is set to the -Vy2 voltage, the second voltage source -V2 is set to Vy1-Vy2. At this time, if the set-down control signal Sd (CTRY) is applied to the first control terminal 71, a current is gradually formed between the source terminal and the drain terminal of the N-channel MOSFET T in correspondence with the RC time constant. Will flow. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

When the switch element SW is closed in response to the temperature control signal St (CTRY), the voltage of the first voltage source -V1 is applied to the source terminal of the N-channel MOSFET T. At this time, when the set-down control signal Sd (CTRY) is applied to the first control terminal 71, a channel is gradually formed between the source terminal and the drain terminal of the N-channel MOSFET T in correspondence to the RC time constant. Current will flow. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

Referring to FIG. 8, the falling ramp signal generation circuit according to the second embodiment of the present invention includes a variable resistor VR and a capacitor C connected to the gate terminal of the N-channel MOSFET T, and an N-channel MOSFET T. ) And the first switch element connected between the third and fourth voltage sources (-V3, -V4) connected in parallel between the ground voltage source (GND) and the third voltage source (-V3) and the N-channel MOSFET (T). (SW1) and a second switch element (SW2) connected between the fourth voltage source (-V4) and the N-channel MOSFET (T).

Each of the third and fourth voltage sources V3 and V4 is a DC voltage source. The third voltage source -V3 generates a -Vy1 voltage, and the fourth voltage source -V4 generates a -Vy2 voltage.

The first switch device SW1 receives a current path between the third voltage source -V3 and the N-channel MOSFET T in response to the temperature control signal St (CTRY) applied through the second control terminal 72. By selectively forming, the lower limit voltage of the falling ramp waveform Rdn is adjusted to the -Vy1 voltage.

The second switch element SW2 performs a current path between the fourth voltage source -V4 and the N-channel MOSFET T in response to the temperature control signal St (CTRY) applied through the second control terminal 72. By selectively forming, the lower limit voltage of the falling ramp waveform Rdn is adjusted to -Vy2 voltage.

When the first switch element SW1 is closed and the second switch element SW2 is opened in response to the temperature control signal St (CTRY), the -Vy1 voltage generated from the third voltage source -V3 is an N-channel MOSFET (T). Is applied to the source terminal of). At this time, when the set-down control signal is applied to the first control terminal 71, the N-channel MOSFET (T) forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

When the first switch element SW1 is opened and the second switch element SW2 is closed in response to the temperature control signal St (CTRY), the -Vy2 voltage generated from the fourth voltage source -V4 is N-channel MOSFET T. Is applied to the source terminal of. At this time, when the set-down control signal is applied to the first control terminal 71, the N-channel MOSFET (T) forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

9, the falling ramp signal generation circuit according to the third embodiment of the present invention includes a variable resistor VR and a capacitor C connected to the gate terminal of the N-channel MOSFET T, and an N-channel MOSFET T. ) And first and second zener diodes D1 and D2 connected in series between the scan bias voltage source Vsc-bias and a switch element SW connected to both ends of the second zener diode D2. .

The variable resistor VR is connected between the gate terminal of the N-channel MOSFET T and the first control signal terminal 71 to which the set down signal Sd (CTRX) is supplied. The capacitor C is connected between the gate terminal and the source terminal of the N-channel MOSFET T. The set-down control signal Sd (CTRX) is gradually applied to the gate terminal of the N-channel MOSFET T by the RC time constant due to the combination of the variable resistor VR and the capacitor C. FIG. Therefore, the channel of the N-channel MOSFET T is gradually formed due to the RC time constant while the set down control signal Sd (CTRX) is applied to the first control terminal 71.

Each of the first and second zener diodes D1 and D2 is a constant voltage source and outputs a constant voltage when a voltage greater than its breakdown voltage is applied to the reverse bias so that the lower limit voltage of the falling ramp signal Rdn is constant.

The switch element SW selectively short-circuits both ends of the second zener diode D2 in response to the temperature control signal St (CTRY) applied through the second control terminal 72, thereby reducing the falling ramp waveform Rdn. Adjust the lower limit voltage.

When the switch element SW is opened, the scan bias voltage Vsc-bias is applied to the source terminal of the N-channel MOSFET T through the first and second zener diodes D1 and D2. At this time, when the set-down control signal Sd (CTRX) is applied to the first control terminal 71, the N-channel MOSFET T forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

When the switch element SW is closed in response to the temperature control signal St (CTRY), the scan bias voltage Vsc-bias is applied to the source terminal of the N-channel MOSFET T only through the first zener diode D1. At this time, when the set-down control signal Sd (CTRX) is applied to the first control terminal 71, the N-channel MOSFET T forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

Referring to FIG. 10, the falling ramp signal generation circuit according to the fourth embodiment of the present invention includes a variable resistor VR and a capacitor C connected to a gate terminal of an N-channel MOSFET T, and an N-channel MOSFET T. ) And the third and fourth zener diodes D3 and D4 connected in parallel between the scan bias voltage source Vsc-bias and the first Zener diode D3 and the first channel connected between the N-channel MOSFET T. The switch element SW1 and the second switch element SW2 connected between the fourth zener diode D4 and the N-channel MOSFET T are provided.

Each of the third and fourth zener diodes D3 and D4 outputs a constant voltage when a voltage greater than its breakdown voltage is applied to the reverse bias, thereby making the lower limit voltage of the falling ramp signal Rdn constant. The breakdown voltage of the third zener diode D3 is set by -Vy1 voltage and the breakdown voltage of the fourth zener diode D4 is set by -Vy2 voltage.

The first switch element SW1 receives a current path between the third zener diode D3 and the N-channel MOSFET T in response to the temperature control signal St (CTRY) applied through the second control terminal 72. By selectively shorting, the lower limit voltage of the falling ramp waveform Rdn is adjusted to -Vy1 voltage.

The second switch element SW2 receives a current path between the fourth zener diode D4 and the N-channel MOSFET T in response to the temperature control signal St (CTRY) applied through the second control terminal 72. By selectively shorting, the lower limit voltage of the falling ramp waveform Rdn is adjusted to -Vy2 voltage.

When the first switch element SW1 is closed and the second switch element SW2 is opened in response to the temperature control signal St (CTRY), the scan bias voltage Vsc-bias is N through the third zener diode D3. It is applied to the source terminal of the channel MOSFET (T). At this time, when the set-down control signal is applied to the first control terminal 71, the N-channel MOSFET (T) forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

When the first switch element SW1 is opened and the second switch element SW2 is closed in response to the temperature control signal St (CTRY), the scan bias voltage Vsc-bias is N-channel through the fourth zener diode D4. It is applied to the source terminal of the MOSFET (T). At this time, when the set-down control signal is applied to the first control terminal 71, the N-channel MOSFET (T) forms a channel between the source terminal and the drain terminal corresponding to the RC time constant. As a result, the falling ramp waveform Rdn is gradually supplied to the scan electrode Y through the output terminal 73 connected to the drain terminal of the N-channel MOSFET T.

Each of the switch elements SW, SW1, and SW2 may be implemented as any kind of transistor element.

As described above, the method and apparatus for driving a PDP according to the present invention uses a constant voltage circuit including a separate voltage source or a zener diode to set-down voltage for sensing the temperature of the PDP in real time and causing erasing according to the temperature change of the PDP. By minimizing the instability of the discharge characteristics of the cell generated when the temperature is changed, it is possible to minimize the miss discharge or mis-discharge in the PDP. Therefore, the driving method and apparatus of the PDP according to the present invention can stably drive the PDP even if the temperature changes by adaptively varying the driving waveform of the PDP in response to the temperature change.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a waveform diagram illustrating a driving method of the plasma display panel shown in FIG. 1.

3 is a waveform diagram illustrating a conventional method for solving the deterioration of the discharge characteristic caused by the temperature change.

4 is a waveform diagram illustrating another conventional method for solving the deterioration of the discharge characteristic caused by the temperature change.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 6 is a block diagram illustrating a driving device for generating the driving waveform shown in FIG. 5.

FIG. 7 is a circuit diagram illustrating a first embodiment of the scan driver illustrated in FIG. 6.

FIG. 8 is a circuit diagram illustrating a second embodiment of the scan driver shown in FIG. 6.

FIG. 9 is a circuit diagram illustrating a third embodiment of the scan driver illustrated in FIG. 6.

FIG. 10 is a circuit diagram illustrating a fourth embodiment of the scan driver illustrated in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

1: timing controller 2: data driver

3: scan drive unit 4: sustain drive unit

5: driving voltage generator 6: temperature sensor

D1 to D4: Zener diodes SW, SW1, SW2: Switch element

Claims (11)

A temperature sensor for sensing a temperature of the plasma display panel; A controller for generating a temperature control signal in accordance with the temperature sensed by the temperature sensor; A voltage source for generating a negative voltage; And a voltage control circuit for adjusting a voltage supplied to the plasma display panel in response to the temperature control signal. The method of claim 1, The voltage source is A first voltage source for generating a first voltage; And a second voltage source for generating a second voltage. The method of claim 2, And a driving element for supplying a voltage from the voltage sources to the plasma display panel under the control of the voltage control circuit. The method of claim 3, wherein And the first voltage source and the second voltage source are connected in series to the drive element. The method of claim 4, wherein The voltage control circuit, A switch element for selectively forming a current path between both ends of the first voltage source and the second voltage source, And a control signal for controlling the drive element and the switch element. The method of claim 3, wherein And the first voltage source and the second voltage source are connected in parallel to the driving element. The method of claim 6, The voltage control circuit, A first switch element for selectively forming a current path between the first voltage source and the drive element; A second switch element for selectively forming a current path between the second voltage source and the driving element, And a control signal for controlling the drive element and the switch element. The method of claim 1, And a voltage supplied to the plasma display panel is an initialization voltage for initializing the plasma display panel. The method of claim 8, The initialization voltage is, A driving device of a plasma display panel, characterized in that the voltage is supplied to the plasma display panel in a falling ramp waveform in which the voltage gradually falls. The method of claim 2, Each of the voltage sources, A drive device of a plasma display panel, characterized in that the zener diode. The method of claim 10, And a negative voltage source for supplying a negative voltage to the zener diode.