JPH10207427A - Driving method for plasma display panel display device and driving control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the surface temperature of a plasma display panel and to uniformalize the surface temperature as much as possible by increasing and decreasing a held discharging period length in each sub-field in one field with the same rate for each sub-field in accordance with the detected temperature of a surface of a panel. SOLUTION: A panel surface temperature detecting circuit 15 mainly consists of temperature sensor circuits, detects surface temperature of a plasma display panel 11, and supplies the detected signal to a sub-field keeping discharge times control circuit 13. The sub-field keeping discharge times control circuit 13 supplies a control signal increasing and decreasing keeping discharge period length of each sub-field with the same rate as each sub-field to a driving pulse generation circuit 4 based on a detected signal from the panel surface temperature detecting circuit 15. Furthermore, the same rate as each sub-field means that for example, when keeping discharge times is made 1/2, keeping discharge times in all sub-fields are made 1/2 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device which performs halftone display by an in-field time division driving display method,
In particular, the present invention relates to a driving method and a driving control device of a plasma display panel display device for displaying an image on a plasma display panel.

[0002]

2. Description of the Related Art A plasma display panel has a different panel structure due to a difference between two types of driving systems, a direct current (DC) system and an alternating current (AC) system. Generally, in the DC method, the electrodes are exposed above the discharge space,
The AC method is characterized in that the electrodes are covered with a dielectric layer. In the AC method, a discharge cell itself has a memory function by the action of a dielectric. For this, various documents (for example, Nikkei Electronics 10-23, 1995)
(No. 647) Special Issue “Wall-mounted TVs Will Become Popular in 2000” and the like, and detailed description is omitted here.

[0003] Since the brightness of a plasma display panel due to one discharge is very small, the operating state of both the DC system and the AC system is used as a binary display of lighting or non-lighting. Then, in order to perform multi-tone display for image display, halftone display is realized using the visual integration effect of the time-division driving display method within a field (16.6 ms). This driving display method is often used not only for plasma display panels but also for other matrix display devices such as liquid crystal panels and fluorescent display tubes.

Here, as an example of a display device that performs halftone display by the time-division driving display method in the field, 3 is used.
A conventional driving method will be described using an electrode type AC plasma display panel display device as an example. FIG.
1 is a block diagram showing an example of a general AC type plasma display panel display device.

In FIG. 5, a frame memory 1 stores an image signal (R, R) converted into a digital signal of, for example, 8 bits.
G, B signals). The frame memory 1 is composed of two field memories, and writing and reading are alternately switched for each field. If the signal form of the image signal is three separate R, G, and B signals, three frame memories are required.
When the G and B signals are combined into one system,
The frame memory 1 is composed of one. The memory write control circuit 2 inputs a write control signal to the frame memory 1 and controls writing of an image signal to the frame memory 1. The memory read control circuit 3 inputs a read control signal to the frame memory 1 and controls reading of a subfield image bit signal from the frame memory 1.

[0006] A subfield image bit signal, which is a display data signal read from the frame memory 1, is input to an address electrode drive circuit 5. The drive pulse generation circuit 4 generates various drive pulses to be supplied to the address electrodes 8, the X electrodes 9, and the Y electrodes 10 to drive the plasma display panel 11. That is, the drive pulse generation circuit 4 supplies an address electrode drive pulse to the address electrode drive circuit 5, supplies an X electrode drive pulse to the X electrode drive circuit 6, and supplies a Y electrode drive pulse to the Y electrode drive circuit 7. .

FIG. 6 is a diagram showing an example of driving waveforms for explaining a display operation by the plasma display panel display device provided with the AC type plasma display panel 11 shown in FIG. FIG. 6 shows driving waveforms supplied to the address electrodes 8 of A1 to Am, the X electrodes 9 of X, and the Y electrodes 10 of Y1 to Yn. As shown in FIG. 6, one subfield includes three types of periods: a reset period, an address period, and a sustain discharge period. It should be noted that the subfield forms a part of the field, and will be described later in detail.

First, the discharging operation in the reset period will be described in order. In the reset period in this example,
Three-stage operations of all-screen batch erasing, all-screen batch writing, and all-screen batch erasing are sequentially performed. As described above, the main reason why the reset period is constituted by the three-stage operation is to stabilize the display write discharge in the next address period after the reset period, to suppress the power consumption of the drive driver IC, and to reduce the low address. This is because a display writing discharge is performed at a high speed with a voltage.

In the above all-screen batch erasure, the display state during the sustain discharge period in the previous subfield, that is, the influence of the wall charge due to the ratio of the discharged discharge cells to the entire screen, is eliminated. Then, an erase pulse Ve for erasing only the remaining wall charge is applied to the X electrode 9, and erasing discharge is performed on all the discharge cells. In addition,
The purpose of this erase pulse is to erase only the remaining wall charges, and therefore, for example, a similar effect can be obtained with a pulse having a higher voltage and a smaller width than the erase pulse shown in FIG.

Next, in the above-described all-screen batch writing,
A write pulse having a voltage Vw at which the discharge starts only at that voltage is applied to all the Y electrodes Y1 to Yn, and the write discharge is forcibly performed between the X electrodes 9 and the Y electrodes 10 of all the discharge cells. Do. At this time, the address electrode 8 is connected to the X electrode 9
Since the potential is the same as the potential (0 V), the ions are divided into two by the address electrode 8 and the X electrode 9, and the ions accumulate on the surface of each electrode. On the other hand, in the Y electrode 10, the total number of electrons, the number of ions on the address electrode 8 and the number of ions on the X electrode 9, is accumulated on the surface.

In the above-described all-screen batch erasing, an erasing pulse is again applied to the X electrode 9, and all erasing discharges for erasing unnecessary wall charges for the display writing discharge in the address period next to the reset period are performed. Is performed on the discharge cells. Even after the erase discharge, the state where ions remain on the phosphor surface on the address electrode 8 and the same number of electrons as the ions on the address electrode 8 remain on the Y electrode 10 continues.

Next, a display operation in an address period for performing a display write discharge will be described. First, the address electrodes 8 sequentially output image bit information for n rows corresponding to the number of display lines as serial data one row at a time from the Y1 row. At this time, in each of the address electrodes A1 to Am, an address pulse is selectively applied only to the discharge cells to be displayed. On the other hand, during the address period, a sustain voltage hold pulse that is fixed at a voltage of Vs of the same potential as the sustain pulse (sustain pulse) applied in the sustain discharge period following the address period is applied to the X electrode 9. In addition,
The voltage value of the sustain pulse is set to a voltage value at which the discharge does not start with the total voltage of the wall charges remaining after the reset period and Vs.

Although the Y electrode 10 is fixed at a voltage of Va having the same potential as the address pulse during most of the address period, the Y electrode 10 has an electrode corresponding to the serial data applied to the address electrode. A scan pulse for applying a voltage of 0 V in the same phase as the address pulse is applied sequentially from Y1 to the electrode Yn line by line.
Thus, only when the address pulse is applied to the address electrode 8 and the scan pulse is applied to the Y electrode 10, the voltage Va is superimposed on the remaining wall charge after the reset period and is higher than the discharge start voltage. , A display write discharge occurs, and image bit information is written. At this time, wall charges remain in the discharge cells as in the above-described all-screen batch writing in the reset period.

In the sustain discharge period, sustain pulses for maintaining the discharge on the Y electrode 10 and the X electrode 9 are alternately applied. At this time, the address electrode 8 is fixed to 0 V, but is re-discharged (sustain discharge) only by the wall charges and the sustain pulse remaining in the discharge cell in which the image bit information is written in the address period. Therefore, in the sustain discharge period, only the discharge cells in which the image bit information has been written in the address period sustain the discharge for the number of times the sustain pulse is applied. As described above, in the AC type plasma display panel, the panel can have a memory function by remaining wall charges in the cell itself.

FIG. 7 is a diagram showing an example of an operation in the case of displaying a halftone by subfield division by the driving method shown in FIG. 7, the vertical axes Y1 to Yn indicate the number of display lines, and the horizontal axis indicates a time axis. In FIG. 7, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. The subfields are configured in order from the least significant bit) to the MSB (most significant bit). As described above, one field is divided into M subfields, and a gray scale of 2M is applied to the plasma display panel 11 by using a visual integration effect by weighting bits based on image bit information. Image representation.

Each subfield is composed of a reset period, an address period, and a sustain discharge period, as described above. The reason why the length of the sustain discharge period differs for each subfield is that the number of sustain pulses (sustain pulses) corresponding to bit weighting is applied. The number of sustain pulses actually applied is 1, 2, 2,
4,..., 128, and the pulse number N times larger (N is a positive integer) is applied in order to increase the emission luminance.

[0017]

By the way, the plasma display panel display device has a problem that the brighter the display image continues, the more the ratio of the bright screen to the whole screen continues and the longer the image continues. The surface temperature of the plasma display panel 11 tends to gradually increase. In addition, as the number of display cells increases with the same panel size (that is, the higher the definition of the panel), the rate of temperature rise increases. This is because the luminous efficiency of the plasma display panel 11 is low.

The plasma display panel 11
Surface temperature of the plasma display panel 1
If the surface temperature difference between the portion where the surface temperature is the lowest and the portion where the surface temperature is the highest on one surface is 20 degrees or more, there is a risk that the plasma display panel 11 will be broken. Further, when the surface temperature of the plasma display panel 11 increases, discharge may be activated. Even when the same driving voltage is applied, a large amount of discharge current flows, which may adversely affect the life of the plasma display panel 11. There is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a driving method and a driving method for a plasma display panel display device capable of lowering the surface temperature of a plasma display panel and making the surface temperature difference as uniform as possible. It is an object to provide a control device.

[0020]

According to the present invention, in order to solve the above-mentioned problems of the prior art, (1) one field is divided into a plurality of subfields, and a halftone display of an image signal is performed. A driving method of a plasma display panel display device, wherein the subfield includes at least an address period and a sustain discharge period, and is driven so as to perform a sustain discharge as many times as necessary for halftone display of the image signal in the sustain discharge period. Detecting the surface temperature of the plasma display panel in the plasma display panel display device, and increasing or decreasing the sustain discharge period length in each subfield in one field at the same ratio according to the detected temperature. A method for driving a plasma display panel display device is provided. A driving pulse generating circuit (4) for generating a driving pulse required to divide the data into a plurality of sub-fields and express a halftone display of an image signal. A panel surface temperature detection circuit (15) for detecting the surface temperature of the plasma display panel in the device, and controlling the drive pulse generation circuit in accordance with the temperature detected by the panel surface temperature detection circuit, thereby controlling each sub-field in one field. A driving control apparatus for a plasma display panel display device, comprising: a subfield sustaining discharge number control circuit (13) for increasing or decreasing the number of sustaining discharges in a field at the same ratio as each subfield. .

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a driving method and a driving control device of a plasma display panel display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a plasma display panel display device according to the present invention, FIG. 2 is a diagram showing an example of an operation when halftone display is performed by subfield division according to the present invention, and FIG. FIG. 4 is a diagram illustrating an example of another operation in the case of performing halftone display by subfield division, and FIG. 4 is a diagram illustrating an example of still another operation in the case of performing halftone display by subfield division in the present invention. In FIG. 1, the same portions as those in FIG. 5 are denoted by the same reference numerals.

First, the configuration of the plasma display panel display device of the present invention will be described with reference to FIG. The driving waveform of the driving method and the driving control device of the plasma display panel display device of the present invention are the same as those in FIG.

In FIG. 1, a frame memory 1 stores, for example, an image signal (R,
G, B signals). The frame memory 1 is composed of two field memories, and writing and reading are alternately switched for each field. If the signal form of the image signal is three separate R, G, and B signals, three frame memories are required.
When the G and B signals are combined into one system,
The frame memory 1 is composed of one. The memory write control circuit 2 inputs a write control signal to the frame memory 1 and controls writing of an image signal to the frame memory 1. The memory read control circuit 3 inputs a read control signal to the frame memory 1 and controls reading of a subfield image bit signal from the frame memory 1.

A subfield image bit signal, which is a display data signal read from the frame memory 1, is input to the address electrode driving circuit 5. The drive pulse generation circuit 4 generates various drive pulses to be supplied to the address electrodes 8, the X electrodes 9, and the Y electrodes 10 to drive the plasma display panel 11. That is, the drive pulse generation circuit 4 supplies an address electrode drive pulse to the address electrode drive circuit 5, supplies an X electrode drive pulse to the X electrode drive circuit 6, and supplies a Y electrode drive pulse to the Y electrode drive circuit 7. .

The panel surface temperature detecting circuit 15 mainly comprises a temperature sensor circuit, detects the surface temperature of the plasma display panel 11, and supplies a detection signal to the subfield sustain discharge number control circuit 13. The subfield sustain discharge number control circuit 13 is based on the detection signal from the panel surface temperature detection circuit 15 and is based on the sustain discharge period length of each subfield in FIG.
Is supplied to the drive pulse generation circuit 4 to increase or decrease the ratio at the same rate in each subfield. Note that the same ratio in each subfield means that, for example, when the number of sustain discharges is １ ／, the number of sustain discharges in all subfields is そ れ ぞ れ.

Specifically, when the surface temperature of the plasma display panel 11 is high, the sustain discharge period length of each subfield is controlled to be shorter, and the brightness of the image displayed on the plasma display panel 11 is reduced. make low. When the surface temperature of the plasma display panel 11 is low, as shown in FIG. 7, the length of the sustain discharge period of each subfield is controlled to be the longest, and the plasma display panel is used by using one whole field. An image is displayed on the panel 11. In this way, in the present invention, the sustain discharge period length (the number of sustain discharges) shown in FIG. 7 is set to the longest (most), and the sustain discharge period length is increased or decreased according to the surface temperature of the plasma display panel 11 for display. Thereby, the surface temperature and the surface temperature difference of the entire plasma display panel 11 can be made uniform.

In this embodiment, the number of sustain discharges is increased or decreased at the same ratio in each subfield.
Compared to a method that only reduces the number of sustain discharges in one subfield, even if the luminance is lowered, the number of display gradations, the display bit accuracy, or the contrast is not reduced, and the plasma display panel is effectively reduced. 11 can be extended.

FIG. 2 shows an example of halftone display when the sustain discharge period length of each subfield in FIG. 7 is halved. FIG. 3 shows the sustain discharge period length of each subfield in FIG. Is an example of the halftone display in the case where each is 1/4. In these display examples, the length of each subfield is made constant in advance, and only the length of the sustain discharge period is reduced based on the detection signal from the panel surface temperature detection circuit 15. Then, the remaining period after the sustain discharge period ends, which is generated by shortening the sustain discharge period length in each subfield, is defined as a pause period. 2 and 3, the period after the sustain discharge period of the subfield SF7 is shown as a pause period. However, the period after the sustain discharge period of the other subfields SF1 to SF6 and SF8 is also a pause period. is there.

FIG. 4 shows another example of halftone display when the sustain discharge period length of each subfield in FIG. 7 is halved. In FIG. 4, a reset period and an address period of the next subfield are continued immediately after the sustain discharge period of the previous subfield is completed, instead of providing a pause period for each subfield. Therefore, in this case, the subfield S
A rest period is provided at the end (right end in the figure), which is the remaining period of one field after completing F1 to SF8. Also in this case, similarly to FIGS. 2 and 3, even if the luminance is reduced, the number of display gradations, the display bit accuracy, or the contrast is not reduced.

[0030]

As described above in detail, the driving method and the driving control device of the plasma display panel display device according to the present invention detect the surface temperature of the plasma display panel, and according to the detected temperature, the temperature in one field is changed. Since the length of the sustain discharge period (the number of sustain discharges) in each subfield is increased / decreased at the same ratio in each subfield, the surface temperature of the plasma display panel can be lowered, and the surface temperature difference can be made as uniform as possible. . Moreover, there is a feature that the number of display gradations, the display bit accuracy, and the contrast are not reduced even when the luminance is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an operation in a case where halftone display is performed by subfield division according to the present invention.

FIG. 3 is a diagram illustrating an example of another operation when halftone display is performed by subfield division according to the present invention.

FIG. 4 is a diagram showing an example of still another operation in the case where halftone display is performed by subfield division in the present invention.

FIG. 5 is a block diagram showing an example of a general AC type plasma display panel display device.

FIG. 6 is a waveform diagram showing an example of a driving waveform for explaining a display operation of the AC type plasma display panel display device.

FIG. 7 is a diagram illustrating an example of an operation in a case where halftone display is performed by subfield division by the driving method illustrated in FIG. 6;

[Explanation of symbols]

 Reference Signs List 1 frame memory 2 memory write control circuit 3 memory read control circuit 4 drive pulse generation circuit 5 address electrode drive circuit 6 X electrode drive circuit 7 Y electrode drive circuit 8 address electrode 9 X electrode 10 Y electrode 11 Plasma display panel 13 Subfield maintenance Discharge count control circuit 15 Panel surface temperature detection circuit

Claims (2)

[Claims] 1. A method according to claim 1, wherein one field is divided into a plurality of sub-fields to perform halftone display of an image signal, and said sub-field is composed of at least an address period and a sustain discharge period. In a driving method of a plasma display panel display device driven to perform sustain discharge as many times as necessary for halftone display of a signal, a surface temperature of the plasma display panel in the plasma display panel display device is detected, and the detected temperature is determined according to the detected temperature. The sustain discharge period length in each subfield in one field is increased or decreased at the same ratio in each subfield. 2. A plasma display panel display device comprising a driving pulse generating circuit for generating a driving pulse required to divide one field into a plurality of subfields and express halftone display of an image signal. A panel surface temperature detection circuit for detecting a surface temperature of the plasma display panel in the display panel display device; and controlling the drive pulse generation circuit in accordance with the temperature detected by the panel surface temperature detection circuit to thereby control each sub-field in one field. A drive control device for a plasma display panel display device, comprising: a subfield sustain discharge number control circuit for increasing / decreasing the number of sustain discharges in a field at the same ratio in each subfield.