JP3379446B2 - Plasma display panel display device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for a display device such as a plasma display panel which performs halftone display by an in-field time division drive display method and a driving method thereof, and more particularly, to a sustain discharge according to a display image. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel display device that performs pulse control by changing the number of times a pulse is emitted, and a driving method thereof.

[0002]

2. Description of the Related Art A plasma display panel uses an operating state as a binary display of lighting or non-lighting. And
In order to perform multi-gradation display for image display, halftone display is realized by utilizing the visual integration effect of the time division drive display method within the field (16.6 ms). Less than,
As a conventional technique, a three-electrode AC-type plasma display panel display device that performs halftone display by the time-division drive method in the field will be described as an example.

FIG. 4 is a block diagram showing an example of a general AC type plasma display panel display device.
In FIG. 4, the frame memory 1 has, for example, image signals (R, G, B signals) converted into 8-bit digital signals.
Is entered. The frame memory 1 is composed of two field memories, and writing and reading are alternately switched for each field. When the signal form of the image signal is three systems of R, G, and B signals separately,
Three frame memories are required, and when the R, G, B signals are combined into one system, the frame memory 1 is composed of one.

The memory writing control circuit 2 inputs a writing control signal to the frame memory 1 to control writing of an image signal into the frame memory 1. The memory read control circuit 3 inputs a read control signal to the frame memory 1 to control the reading of the subfield image bit signal from the frame memory 1.

The subfield image bit signal which is the display data signal read from the frame memory 1 is input to the address electrode drive circuit 5. The drive pulse generation circuit 4 generates various drive pulses to be supplied to the address electrodes 8, the X electrodes 9, and the Y electrodes 10 in order to drive the plasma display panel 11. That is, the drive pulse generation circuit 4 supplies the address electrode drive circuit 5 with the address electrode drive pulse, the X electrode drive circuit 6 with the X electrode drive pulse, and the Y electrode drive circuit 7 with the Y electrode drive pulse. .

FIG. 5 is a diagram showing an example of drive waveforms for explaining a display operation by the plasma display panel display device shown in FIG. In FIG. 5, address electrodes 8 of A1 to Am, X electrodes 9 of X, and Y electrodes of Y1 to Yn.
The drive waveform supplied to the electrode 10 is shown. As shown in FIG. 5, one subfield is composed of three types of periods: a reset period, an address period, and a sustain discharge period. The subfield constitutes a part of the field, which will be described in detail later.

First, in the reset period, three-step operations of all-screen batch erase, all-screen batch write, and all-screen batch erase are performed in order. In this way, the reset period is 3
The main reason for being configured by the step operation is to stabilize the display writing discharge in the address period subsequent to the reset period, to suppress the power consumption of the drive driver IC, and to perform the display writing discharge at a high speed with a low address voltage. This is because. The reset period may be configured for each subfield, or may be configured once or several times for each field.

Next, in the address period, the operation of writing the image bit information, which is the display data assigned to each sub-field, sequentially for each line is performed. The address electrode 8 sequentially outputs image bit information for n rows corresponding to the number of display lines as serial data row by row from Y1 row. At this time, in each of the address electrodes A1 to Am,
The address pulse is selectively applied only to the discharge cells to be displayed.

Further, the Y electrodes 10 are sequentially arranged line by line from the electrode Y1 to the electrode Yn in the Y electrode 10, corresponding to the serial data applied to the address electrodes 8.
A scan pulse having the same phase as the address pulse and a voltage of 0 V is applied. As a result, the image bit information is written only when the address pulse is applied to the address electrode 8 and the scan pulse is applied to the Y electrode 10.

During the sustain discharge period, sustain pulses for sustaining the discharge are alternately applied to the Y electrode 10 and the X electrode 9. At this time, although the address electrode 8 is fixed at 0V, it is re-discharged (sustain discharge) only by the wall charge and the sustain pulse remaining in the discharge cell in which the image bit information is written in the address period. Therefore, in the sustain discharge period, the discharge continues only in the discharge cells in which the image bit information is written in the address period, the number of times the sustain pulse is applied.

As described above, in the AC type plasma display panel, the wall charge is left in the cell itself so that the panel has a memory function.

FIG. 6 is a diagram showing an example of an operation when halftone display is performed by subfield division by the driving method shown in FIG. The vertical axes Y1 to Yn in FIG. 6 represent the number of display lines, and the horizontal axis represents the time axis.

In FIG. 6, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into 8 subfields (SF1 to SF8) having different luminance relative ratios, and image bit information is obtained. LSB (least significant bit) to M
Subfields are sequentially formed up to SB (most significant bit). In this way, one field is divided into M subfields, and a visual integration effect by weighting bits based on image bit information is used to generate 2 M gray scales in the plasma display panel 11. Image representation.

As described above, each subfield is composed of a reset period, an address period, and a sustain discharge period. The length of the sustain discharge period differs for each subfield because the number of sustain pulses (sustain pulses) corresponding to the weighting of bits is applied. The number of sustain pulses actually applied is 1, 2,
4, ..., 128, and the number of pulses N times (N is a positive integer) is further applied in order to obtain the emission brightness.

[0015]

As described above, according to the driving method of the plasma display panel display device, one field is divided into a plurality of sub-fields having different luminance relative ratios to express the halftone display of the image signal. ing. Under the current driving conditions, even when there is no input image signal, or when there is no input image bit information of a specific subfield or a specific display line, scanning is performed during the address period and sustain discharge period of each subfield. Since a drive pulse such as a pulse or a sustain pulse is always applied every time, there is a problem in that useless power consumption that does not contribute to the display discharge consumed in the drive circuit unit occurs.

Since the sustain discharge period length is fixed due to the time constraint of one field period, the sustain discharge period length is increased to increase the peak brightness in the screen that is entirely dark or only partially bright. I couldn't. The peak brightness could not be increased due to the limitation of power consumption.

As an example, when displaying an image in which the upper and lower parts are black bands as shown in FIG. 7, drive pulses are applied also to the black bands, resulting in unnecessary power consumption. Become. The problem of wasteful power consumption increases as the number of sustain discharges spent in one field increases. Therefore, conventionally, it has been necessary to limit the number of sustain discharges to some extent, and drive so as to achieve a predetermined limited brightness level.

Therefore, it is difficult to raise the peak luminance above the limited luminance level, and by lowering the number of sustain discharges in a predetermined fixed sustain discharge period length according to the average image level, The current situation is that the peak brightness is variable. That is, conventionally, the brightness can be varied only in the direction in which the brightness level is limited in advance, and the image cannot be displayed with the brightness comparable to that of the cathode ray tube.

The above problems are not limited to the display device of the above-described system, and a plasma display in which one field is divided into a plurality of subfields having different luminance relative ratios to express a halftone display of an image signal. In the case of panel display devices, the same applies to all cases in common. Further, the above problem is not limited to the plasma display panel display device, but is a common problem in a display device that realizes halftone display by utilizing the visual integration effect of the time division drive display method in the field.

The present invention has been made in view of this problem, and it is possible to reduce unnecessary power consumption that does not contribute to display discharge, and further, it is possible to increase the peak brightness and a plasma display panel display device and its driving. The purpose is to provide a method.

[0021]

In order to solve the above-mentioned problems of the prior art, the present invention is as follows: (1) One field is divided into a plurality of sub-fields to perform halftone display of an image signal, A plasma display in which the sub-field is composed of at least an address period and a sustain discharge period, and the sustain discharge is controlled by weighting each sub-field for the number of times necessary for halftone display of the image signal in the sustain discharge period. In the panel display device, a memory that stores the image signal as an image bit signal for each subfield, a memory write control circuit that controls writing of the image signal to the memory, and a read of the image signal from the memory are performed. A memory read control circuit for controlling, and at least the plasma display panel display device. A display line image information determination circuit for determining the presence or absence of an image bit signal in each subfield is provided for each display line in the image area to be displayed, and at least one display line having no image bit signal exists. For the subfield, it is determined by the display line image information determination circuit that no image bit signal exists in the address period.
The specified display line is skipped and the image bit signal is
Provided is a plasma display panel display device characterized in that only a display line determined to be present is continuously scanned and driven, and (2) one field is divided into a plurality of subfields to provide an image signal. Of the sub-field is composed of at least an address period and a sustain discharge period, and the sub-fields are weighted by the number of times necessary for the half-tone display of the image signal in the sustain discharge period. In a method of driving a plasma display panel display device for controlling to perform sustain discharge, at least for each display line in an image region displayed by the plasma display panel display device, it is determined whether or not there is an image bit signal in each subfield. However, at least one display line with no image bit signal is In the existing subfield, the image is displayed in the address period.
Skip display lines that are determined to have no bit signal
In addition, the present invention provides a driving method of a plasma display panel display device, characterized in that only the display line determined to have the image bit signal is continuously scanned and driven.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A plasma display panel display device and a driving method thereof according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a plasma display panel display device of the present invention, FIG. 2 is a diagram showing an example of an operation when halftone display is performed by subfield division of the present invention, and FIG. It is a figure which shows an example of the drive waveform for demonstrating a display operation. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals.

In FIG. 1, an image signal (R, G, B signal) converted into, for example, an 8-bit digital signal is input to the frame memory 1 and also to the display line image information determination circuit 12. . The frame memory 1 is composed of two field memories, and writing and reading are alternately switched for each field. If the signal form of the image signal is three systems of R, G, and B signals separately, three frame memories are required.
When the G and B signals are combined into one system,
The frame memory 1 is composed of one.

The memory writing control circuit 2 inputs a writing control signal to the frame memory 1 to control writing of an image signal into the frame memory 1. The memory read control circuit 3 inputs a read control signal to the frame memory 1 to control the reading of the subfield image bit signal from the frame memory 1.

The sub-field image bit signal which is the display data signal read from the frame memory 1 is input to the address electrode drive circuit 5. The drive pulse generation circuit 4 generates various drive pulses to be supplied to the address electrodes 8, the X electrodes 9, and the Y electrodes 10 in order to drive the plasma display panel 11. That is, the drive pulse generation circuit 4 supplies the address electrode drive circuit 5 with the address electrode drive pulse, the X electrode drive circuit 6 with the X electrode drive pulse, and the Y electrode drive circuit 7 with the Y electrode drive pulse. .

The display line image information determination circuit 12 inputs the image signal input to the frame memory 1, and in every effective image area displayed on the plasma display panel 11, for each line in each subfield,
It is determined whether or not there is image bit information (image bit signal), and the display line image bit information is input to the memory read control circuit 3 and the drive pulse generation circuit 4 and the sustain discharge period drive pulse stop circuit 13. .

When the display line image information judging circuit 12 judges that there is no image bit information of the display line, the memory read control circuit 3 does not read the subfield image bit signal of the display line, but at that timing. The frame memory 1 is controlled so as to read out the subfield image bit signal of the nearest next display line where the image bit information exists. At the same time, the drive pulse generation circuit 4 generates not the drive pulse of the display line determined to have no image bit information but the drive pulse of the next next display line having the image bit information.

Further, the sustain discharge period drive pulse stop circuit 1
3 controls the drive pulse generation circuit 4 to stop the drive pulse supplied to the display line determined to have no image bit information during the sustain discharge period during the sustain discharge period.

As described above, in the display device and the driving method according to the present invention, for the subfield in which at least one display line having no image bit information exists, the read operation from the frame memory in the address period is performed. There is no display line, and only the display line having image bit information is continuously read and driven.

Here, an example of the operation according to the present invention for continuously reading and displaying only the display line in which the image bit information is present in each subfield is shown in FIG.
Will be explained. FIG. 2 is a halftone display in the case where the display image is present only in the central portion of the screen as shown in FIG. 7 in all the effective image areas displayed on the plasma display panel 11 by the display line image information determination circuit 12. An example of the operation is shown. In FIG. 2, (a)
Is a conventional operation example for comparison, and (b) is an operation example according to the present invention.

As shown in FIG. 2B, when there is no image bit information in the upper and lower parts of the screen, the data is continuous only in the central portion where the image bit information exists in the address period in each subfield. Then scan to read,
It is driven so that the sustain discharge period starts immediately after the address is completed. In this way, the total sustain discharge period assigned to one field can be set longer by (address time in upper and lower parts × number of subfields) than in the conventional case.

Here, for the sake of convenience, the total sustain discharge period is shown longer than the address period, but in reality, when the number of subfields is set to 8 to 12, the address period is longer than the total sustain discharge period. It will be much longer. Therefore, by allocating the address period of the portion having no image bit information to the total sustain discharge period of the portion having image bit information, the peak luminance of the portion having image bit information can be greatly improved. As a result, the contrast can be improved.

According to the present invention, as shown in FIG. 7, not only an image in which the upper and lower parts of the screen are black bands, but also other parts, for example, an image in which the central part of the screen is a black band Good. Further, it is effective not only when there is no image bit information in a predetermined period of a field, but also when there is no image bit information in one line in one subfield. For a subfield in which there is at least one display line having no image bit information, only the display line having image bit information is continuously scanned in the address period, and the sustain discharge of the display line having image bit information is performed. The peak brightness can be increased by lengthening the period and increasing the number of sustain pulses.

In this way, the display line image bit information is determined for each subfield, and the lengths of the address period and the sustain discharge period are changed according to the image content,
It is also possible to improve the contrast by controlling the peak brightness as high as possible.

FIG. 3 shows an example of drive waveforms supplied to each electrode for performing the halftone display operation shown in FIG. 2 (b). As shown in FIG. 3, since only the display line having the image bit information is required in the address period, the Y electrode 10
The scan pulse supplied to is not applied to the electrodes Y1 and Yn located in the upper and lower lines. At the same time, the address pulse supplied to the address electrode 8 is controlled so that the data on the lines of the electrodes Y1 and Yn are skipped, so that only the display data of the central portion that needs to be displayed is continuously read. As a result, the address period can be minimized.

Next, during the sustain discharge period, the number of sustain pulses is increased for driving as shown in FIG. However, if the number of pulses is increased as it is, useless power consumption that does not contribute to the display discharge consumed in the drive circuit unit increases. In order to prevent this, the display line image information determination circuit 1
In the display line determined to have no image bit information by 2, the sustain discharge period drive pulse stop circuit 13 stops the sustain pulse supplied to the Y electrodes 10 (Y1, Yn, etc.) as shown in FIG. Control. As a result, useless power consumption that does not contribute to the display discharge consumed in the drive circuit unit can be reduced.

By the way, in the example of FIG. 3, the application of the sustain pulse itself to the Y electrode 10 is eliminated, but the purpose is to reduce useless power consumption that does not contribute to the display discharge. The purpose can be achieved only by attenuating the sustain pulse applied during the sustain discharge period.

Further, the reduction of useless power consumption that does not contribute to the display discharge can be realized without stopping the sustain discharge pulse by the sustain discharge period drive pulse stop circuit 13. That is, the image bit information output from the display line image information determination circuit 12 is input to the X electrode drive circuit 6 and the Y electrode drive circuit 7, and the voltage value of the high voltage pulse is set in the X electrode drive circuit 6 and the Y electrode drive circuit 7. By lowering or completely reducing to 0, useless power consumption that does not contribute to the display discharge that occurs during the sustain discharge period can be attenuated. Thereby, the object of the present invention can be achieved.

In this embodiment, the plasma display panel display device provided with the AC type plasma display panel 11 has been described, but the driving method of the present invention uses the plasma display panel display device provided with the DC type plasma display panel. The same can be applied to the plasma display panel display device in which the display discharge (display writing discharge and sustain discharge) is time-division driven.

[0040]

As described above in detail, the plasma display panel display device and the driving method thereof according to the present invention include at least each display line in the image area displayed by the plasma display panel display device and each subfield. The presence or absence of the image bit signal in the inside is determined, and for the subfield in which there is at least one display line having no image bit signal, it is determined that there is no image bit signal in the address period.
And the image bit signal is determined to exist.
Since it is configured to continuously scan and drive only the selected display line, it is possible to reduce wasteful power consumption that does not contribute to the display discharge, and further, depending on the image, it is possible to reduce the power consumption from a predetermined predetermined brightness level. Can also adaptively increase the peak brightness. It also becomes possible to improve the contrast.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a plasma display panel display device of the present invention.

FIG. 2 is a diagram showing an example of an operation when a halftone display is performed by subfield division according to the present invention.

FIG. 3 is a diagram showing an example of drive waveforms for explaining a display operation according to the present invention.

FIG. 4 is a block diagram showing an example of a conventional plasma display panel display device.

FIG. 5 is a diagram showing an example of drive waveforms for explaining a display operation according to a conventional example.

FIG. 6 is a diagram showing an example of an operation when a halftone display is performed by subfield division according to a conventional example.

FIG. 7 is a diagram showing an example of an image having a display line having no image bit signal.

[Explanation of symbols]

1 frame memory 2 Memory write control circuit 3 Memory read control circuit 4 Drive pulse generation circuit 5 Address electrode drive circuit 6 X electrode drive circuit 7 Y electrode drive circuit 8 address electrodes 9 X electrodes 10 Y electrodes 11 Plasma display panel 12 Display line image information determination circuit 13 Sustain discharge period drive pulse stop circuit

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Claims (2)

(57) [Claims] 1. One field is divided into a plurality of sub-fields to perform halftone display of an image signal, the sub-fields are composed of at least an address period and a sustain discharge period, and the image is generated in the sustain discharge period. In a plasma display panel display device for controlling to perform sustain discharge by weighting each subfield for the number of times necessary for halftone display of a signal, a memory storing the image signal as an image bit signal for each subfield, A memory write control circuit for controlling the writing of the image signal to the memory; a memory read control circuit for controlling the reading of the image signal from the memory; and at least in an image area displayed on the plasma display panel display device. For each display line, the image A display line image information determination circuit for determining the presence or absence of a display signal, and the display line image information determination circuit for the subfield in which at least one display line having no image bit signal exists in the address period. Display line determined by image bit signal not present by
The plasma display panel display device is characterized in that only the display line determined to have the image bit signal is continuously scanned and driven. 2. One field is divided into a plurality of subfields for halftone display of an image signal, the subfields are composed of at least an address period and a sustain discharge period, and the image is generated in the sustain discharge period. In a driving method of a plasma display panel display device for controlling so as to perform sustain discharge by weighting each subfield for the number of times necessary for halftone display of a signal, at least in an image area displayed by the plasma display panel display device. for each display line, to determine the presence or absence of image bit signals in each sub-field, to sub-field in which the image bit signal without any display line exists at least one line, in the address period, the video bit signal Determined not to exist
A method for driving a plasma display panel display device, characterized in that the selected display line is skipped, and only the display line determined to have the image bit signal is continuously scanned and driven.