JPH10177365A - Drive controller for plasma display panel display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive controller capable of effectively executing the improvement of contrast and the reduction of power consumption. SOLUTION: One field is divided into plural sub-fields to execute the half tone display of a picture signal and each sub-field is constituted of a reset period, an address period and a holding discharge period. A sub-field picture bit information judging circuit 23 judges the existence of picture bit information in one sub-field within a picture area. A reset period drive pulse batch stop circuit 22 stops a drive pulse in the reset period as to a field judged that no picture bit information exists.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control device for a plasma display panel display device for displaying an image on the plasma display panel display device, and more particularly, to a drive control device for the plasma display panel display device.
The present invention relates to a drive control device for a plasma display panel display device that performs an auxiliary discharge (an auxiliary discharge that is not directly related to a display discharge) in addition to performing a display discharge (a display writing discharge and a sustain discharge).

[0002]

2. Description of the Related Art A plasma display panel has a different panel structure due to a difference between two types of driving systems, a direct current (DC) system and an alternating current (AC) system. Generally, in the DC method, the electrodes are exposed above the discharge space,
The AC method is characterized in that the electrodes are covered with a dielectric layer. In the AC method, a discharge cell itself has a memory function by the action of a dielectric. For this, various documents (for example, Nikkei Electronics 10-23, 1995)
(No. 647) Special Issue “Wall-mounted TVs Will Become Popular in 2000” and the like, and detailed description is omitted here.

FIG. 19 is a plan view schematically showing a three-electrode type surface discharge type plasma display panel among general AC type plasma display panels. In FIG. 19, the plasma display panel 1 has A1
To address electrodes 2, X electrodes 3, Y electrodes 4, Y1 to Yn 4, discharge cell portions 5, and barriers 6. Here, for simplicity, the number of X electrodes 3 is set to 1 with respect to the number n of Y electrodes 4, but depending on the driving conditions of the X electrodes, the number of X electrodes 3 may be changed with respect to the number n of Y electrodes 4. The number may be plural. Also, one discharge cell section 5 is shown with diagonal lines.

FIG. 20 is a partial perspective view showing an example of a cross section of the plasma display panel 1 shown in FIG. In FIG. 20, the discharge cell section 5 includes a front glass substrate 7, X
Electrode 3, Y electrode 4, dielectric layer 8, MgO (magnesium oxide) protective layer 9, barrier 6, R (red) phosphor 10 (or G (green) phosphor 11, B (blue) phosphor 12), This is a discharge space surrounded by the address electrodes 2 and the back glass substrate 13. A gas mixture of He (helium), Ne (neon), Xe (xenon) or the like is sealed in the discharge space to cause a discharge between the address electrode 2, the X electrode 3, and the Y electrode 4, and the discharge is generated. Phosphors 10 to 12
Is excited to obtain emission of R, G, B three primary colors.

FIG. 21 is a diagram showing an example of a driving waveform for explaining a display operation by the plasma display panel display device provided with the plasma display panel 1 shown in FIG. FIG. 21 shows drive waveforms supplied to the address electrodes 2 of A1 to Am, the X electrodes 3 of X, and the Y electrodes 4 of Y1 to Yn. As shown in FIG. 21, one subfield is constituted by three types of periods: a reset period, an address period, and a sustain discharge period. It should be noted that the subfield forms a part of the field, and will be described later in detail.

First, the discharging operation in the reset period will be described in order. In the reset period in this example, three-stage discharge of all-screen batch erasing, all-screen batch writing, and all-screen batch erasure is performed in order. The discharge in this reset period is called a reset discharge, and is an auxiliary discharge that is not directly related to the display discharge. As described above, the main reason that the reset period is constituted by the three-stage operation is as follows.
This is for stabilizing the display write discharge in the address period next to the reset period, and for suppressing the power consumption of the driver IC and performing the display write discharge at a high speed at a low address voltage.

In the above-described all-screen batch erasure, the display state during the sustain discharge period in the previous subfield, that is, the influence of the wall charge due to the ratio of the discharge cell portion 5 discharging to the entire screen, is prevented. Therefore, the X electrode 3
An erase pulse having a voltage Ve for erasing only the remaining wall charges is applied, and erasure discharge is performed on all the discharge cell units 5. The erase pulse has the purpose of erasing only the residual wall charges, and therefore, for example, a pulse having a higher voltage and a smaller width than the erase pulse shown in FIG. 21 has the same effect.

Next, in the above-described all-screen batch writing,
A write pulse having a voltage Vw at which the discharge starts only at that voltage is applied to all the Y electrodes Y1 to Yn, and the writing is forcibly performed between the X electrodes 3 and the Y electrodes 4 of all the discharge cell units 5. Perform discharge. At this time, the address electrode 2 is connected to the X electrode 3
Since the potential is equal to (0 V), the ions are divided into two by the address electrode 2 and the X electrode 3, and the ions accumulate on the surface of each electrode. On the other hand, the total number of electrons, the number of ions on the address electrode 2 and the number of ions on the X electrode 3, is accumulated on the surface of the Y electrode 4.

In the above-described all-screen batch erasing, an erasing pulse is again applied to the X electrode 3, and all erasing discharges for erasing unnecessary wall charges for the display writing discharge in the address period next to the reset period are performed. Discharge cell part 5
Do for Even after the erasing discharge, the state where ions remain on the phosphor surface on the address electrode 2 and the same number of electrons as the ions on the address electrode 2 remain on the Y electrode 4 is maintained.

Next, a display operation in an address period for performing a display write discharge will be described. First, the address electrode 2 sequentially outputs image bit information for n rows corresponding to the number of display lines as serial data one row at a time from the Y1 row. At this time, in each of the address electrodes A1 to Am,
An address pulse is selectively applied only to the discharge cell unit 5 to be displayed. On the other hand, during the address period, a sustain voltage hold pulse that is fixed at a voltage of Vs of the same potential as the sustain pulse (sustain pulse) applied in the sustain discharge period following the address period is applied to the X electrode 3. In addition,
The voltage value of the sustain pulse is set to a voltage value at which discharge does not start with the total voltage of the wall charges remaining after the reset period and the voltage Vs.

The Y electrode 4 is fixed at a voltage of Va, which is the same potential as the address pulse, during most of the address period. Y1 to electrode Yn
, A scan pulse for applying a voltage of 0 V in the same phase as the address pulse is applied in order one row at a time. Thus, only when the address pulse is applied to the address electrode 2 and the scan pulse is applied to the Y electrode 4, the total voltage of the address pulse and the sustain pulse is reduced by the remaining wall charge after the reset period. Since it is superimposed and becomes equal to or higher than the discharge starting voltage, a display writing discharge occurs, and image bit information is written. Further, at this time, wall charges remain in the discharge cell portion 5 as in the above-described all-screen batch writing in the reset period.

In the sustain discharge period, the Y electrode 4 and the X electrode
Sustain pulses for maintaining discharge are applied to the electrodes 3 alternately. At this time, although the address electrode 2 is fixed to 0 V, the amount of wall charges remaining in the discharge cell unit 5 in which the image bit information is written during the address period is:
Since the amount of unnecessary wall charges is larger than the amount of wall charges remaining after the reset period, re-discharge (sustain discharge) is performed only with the sustain pulse. Therefore, in the sustain discharge period, the discharge continues only as many times as the number of times the sustain pulse is applied, only in the discharge cell unit 5 in which the image bit information is written in the address period. As described above, in the AC type plasma display panel, the panel can have a memory function by remaining wall charges in the cell itself.

FIG. 22 is a diagram showing an example of the operation in the case of displaying halftone by subfield division by the driving method shown in FIG. The vertical axes Y1 to Yn in FIG. 22 indicate the number of display lines, and the horizontal axis indicates the time axis. In FIG. 22, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. The subfields are configured in order from the least significant bit) to the MSB (most significant bit). As described above, one field is divided into M subfields, and a gray scale of 2M is applied to the plasma display panel 1 by utilizing a visual integration effect by weighting bits based on image bit information. Image representation.

Each subfield is composed of a reset period, an address period, and a sustaining period, as described above. The reason why the length of the sustain period differs for each subfield is that the number of sustain pulses (sustain pulses) corresponding to bit weighting is applied. The number of sustain pulses actually applied is 1, 2, 4,
.., 128, and the N
A double (N is a positive integer) pulse number is applied.

FIG. 23 is a diagram systematically showing a driving method of a conventional plasma display panel display device by a drive control device. FIG. 23 shows a case where halftone display by subfield division shown in FIG. 22 is performed by the conventional driving method shown in FIG. 21 and all the effective image areas displayed by the plasma display panel display device have a certain field in one field. 3 schematically shows the supply situation of the pulses supplied to the electrodes 3 and 4 when no image bit information of the subfield exists.

In FIG. 23, RST is a reset period, ADR is an address period, and SUS is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is represented by “present” and “absent”.
X electrode 3 shown by, and Y electrode 4 shown by Y1 to Yn
In, the drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse,
The presence of a (sustain pulse) is indicated by “○”.

As shown in FIG. 23, for example, when no image bit information exists in only the subfield SF8, no address pulse to be supplied to the address electrode 2 in the address period is applied in the subfield SF8. Therefore, even if the sustain voltage hold pulse or the scan pulse is supplied to the X electrode 3 or the Y electrode 4, the display write discharge does not occur. Further, since no display write discharge occurs, no sustain discharge (re-discharge) occurs even if a sustain pulse is supplied to the X electrode 3 or the Y electrode 4 during the sustain discharge period.

[0018]

As can be seen from FIG. 23, when driving a three-electrode surface-discharge type plasma display panel 1 in an AC type plasma display panel, display is performed in a discharge cell unit 5. In addition to the write discharge and the sustain discharge, a full-screen write discharge and a full-screen erase discharge are always performed during the reset period of each subfield, so that there is a problem that the contrast is significantly reduced. To solve this problem, the contrast is improved by reducing the number of full-screen writing discharges or full-screen erasing discharges during the reset period, and the apparent contrast ratio is increased by increasing the white peak luminance. Has been proposed,
Not a fundamental solution.

Further, when the screen is dark as a whole, or when there is a scene change, or when only a synchronizing signal is input and the image signal is absent, the floating of black is particularly noticeable. There is also a problem that it will. In addition, this problem is not limited to the above-described AC type panel, and is not limited to a plasma display panel which performs an auxiliary discharge which is not directly related to a display discharge in addition to a display writing discharge and a sustain discharge in the same discharge cell portion. Exactly the same exists in all cases.

On the other hand, among the DC type plasma display panels, a plasma display panel having auxiliary cells for performing auxiliary discharges not directly related to display discharges, in addition to display cells for performing display write discharge and sustain discharge. Then, the black level can be made completely black by forming the auxiliary cells in a black matrix. Thus, improving the contrast, especially the black level,
This is an essential issue for a plasma display panel without an auxiliary cell.

Further, in the conventional drive control device,
Even when the input image signal is no signal or when there is no input image bit information of a specific subfield, in the address period and the sustain discharge period of each subfield,
Since a drive pulse such as a scan pulse or a sustain pulse is always applied every time, there is a problem that wasteful power consumption that does not contribute to display discharge consumed in the drive circuit unit occurs. As the number of display pixels increases to increase the definition and size of the panel, wasteful power consumption that does not contribute to display discharge consumed by the drive circuit unit increases significantly.

The present invention has been made in view of such a problem, and in addition to performing a display discharge (display writing discharge and sustain discharge), an auxiliary discharge (auxiliary discharge not directly related to the display discharge) is also performed. It is an object of the present invention to provide a plasma display panel drive control device capable of lowering a black level, improving contrast, and efficiently reducing power consumption.

[0023]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention divides one field into a plurality of subfields and performs halftone display of an image signal. Comprises a reset period, an address period, and a sustain discharge period. In the address period and the sustain discharge period, a display discharge relating to a halftone display of the image signal is performed, and in the reset period or the address period, the half tone is displayed. In a drive control device for a plasma display panel display device driven to perform an auxiliary discharge not directly related to display, a memory (14) for storing the image signal, and a memory for controlling writing of the image signal to the memory. A write control circuit (15) for reading the image signal from the memory for each subfield A memory read control circuit (16), a subfield image bit information determination circuit (23) for determining whether or not image bit information exists in one subfield, and a subfield image bit information determination circuit. A plasma display panel comprising reset period driving pulse stopping means (22) for stopping a driving pulse in the reset period for a subfield for which it is determined that the image bit information does not exist at all. A drive control device for a display device is provided. Further, for a subfield for which the subfield image bit information determination circuit determines that the image bit information does not exist at all, an address period driving pulse stopping means (24) for stopping a driving pulse in the address period; An object of the present invention is to provide a drive control device for a plasma display panel display device, further comprising a sustain discharge period drive pulse stopping means (25) for stopping a drive pulse in a sustain discharge period.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a drive control device for a plasma display panel display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of the drive control device of the present invention, FIG. 2 is a block diagram showing an example of a more detailed configuration of FIG. 1, and FIG. 3 is a timing chart for explaining the operation of FIG. FIG. 4 is a diagram showing an example of a drive waveform for explaining a display operation according to the first embodiment of the drive control device of the present invention. FIG. 5 systematically shows the first embodiment of the drive control device of the present invention. FIG. 6 is a diagram showing an example of the operation of the first embodiment of the drive control device of the present invention in the case of performing halftone display by subfield division, and FIG. 7 is a diagram showing a second embodiment of the drive control device of the present invention. FIG. 8 is a diagram showing an example of drive waveforms for explaining a display operation according to a second embodiment of the drive control device of the present invention, and FIG. 9 is a system diagram of the second embodiment of the drive control device of the present invention. FIG. 10 is a diagram showing a sub-field in a second embodiment of the drive control device according to the present invention. FIG. 11 is a diagram showing an example of an operation in the case of performing halftone display by division, FIG. 11 is a block diagram showing a third embodiment of the drive control device of the present invention, and FIG. 12 is a diagram showing a third embodiment of the drive control device of the present invention. FIG. 13 is a diagram showing an example of a drive waveform for explaining a display operation. FIG. 13 is a diagram systematically showing a third embodiment of the drive control device of the present invention.
FIG. 14 is a diagram showing an example of the operation of the third embodiment of the drive control device of the present invention when displaying halftones by subfield division, and FIG. 15 is a block diagram showing a fourth embodiment of the drive control device of the present invention. FIGS. 16 and 17 show a fourth embodiment of the drive control device according to the present invention.
FIG. 17 is a diagram showing an example of a drive waveform for explaining a display operation according to the embodiment, FIG. 17 is a diagram systematically showing a fourth embodiment of the drive control device of the present invention, and FIG. FIG. 19 is a diagram illustrating an example of an operation when halftone display is performed by subfield division in the fourth embodiment.

In the conventional drive control device, as described above,
Even if the display writing discharge and the sustain discharge related to the display discharge do not occur, during the reset period of each subfield,
Since the entire screen is always erased or written between the X electrode 3 and the Y electrode 4 every time, a reset discharge (full screen erase or full screen) is performed in the discharge cell unit 5 for each subfield regardless of the presence or absence of display discharge. (Writing). Further, even if the display writing discharge or the sustain discharge related to the display discharge does not occur, the drive pulse related to the display discharge (display writing discharge or the sustain discharge) is always applied during the address period and the sustain discharge period of each subfield. Therefore, wasteful power consumption that does not contribute to the display discharge consumed in the drive circuit unit is generated.

Therefore, if there is no bit information of a specific subfield image in one field, such as a specific test signal, a personal computer input signal, an animation image, etc., this is detected. Then, in this case, the reset discharge is stopped by stopping the drive pulse in the reset period,
Lower the black level to improve contrast. Further, power consumption is reduced by stopping driving pulses during the address period and the sustain discharge period.

<First Embodiment> First, a first embodiment of a drive control device for a plasma display panel display device of the present invention will be described. FIG. 1 shows a plasma display panel used in the plasma display panel display device of the present invention.
9 and FIG.

First, a first embodiment of the drive control device of the present invention will be systematically described with reference to FIG. In FIG. 5, RST is a reset period, ADR is an address period, S
US is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is indicated by “present” or “absent”, and the X electrodes 3 and Y1 indicated by X
The presence or absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is represented by “４” and “X” in the Y electrodes 4 indicated by Yn. FIG. 5 shows a case where no image bit information exists in only the subfield SF8 in all the effective image areas displayed by the plasma display panel display device. As can be seen from FIG. 5, when a state where no image bit information is present in the subfield is detected, supply of drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 is stopped during the reset period. By doing
All reset discharges discharged between the X electrode 3 and the Y electrode 4 are stopped.

More specifically, in the subfield SF8 in which no image bit information is present, as shown in FIG. 4, all pulses to be supplied to each of the electrodes 3 and 4 during the reset period are stopped, and In a state where no pulse is applied. In the other subfields SF1 to SF7 where the image bit information exists, as in the related art,
As shown in FIG. 21, a pulse is supplied to each of the electrodes 3 and 4 even during the reset period.

According to the driving method shown in FIG.
Similarly, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. When the subfields are configured in order from the least significant bit) to the MSB (most significant bit), FIG.
As shown in the figure, during the reset period in each subfield, the subfield S in which no image bit information is present exists.
In F8, the idle period is set, and the other subfields SF1 to SF1
In SF7, the reset period is the same as the conventional one.

Here, the configuration of the drive control device of the plasma display panel display device for realizing the first embodiment will be described with reference to FIGS. In FIG. 1, an image signal (R, G, B signal) converted into, for example, an 8-bit digital signal is input to a frame memory 14. The frame memory 14 is composed of two field memories, and writing and reading are alternately switched for each field. In the case where the signal form of the image signal has three separate R, G, and B signals, three frame memories 14 are required, and the R, G, and B signals are combined into one.
In the case of a system, the frame memory 14 is constituted by one. The memory write control circuit 15 inputs a write control signal to the frame memory 14 and controls writing of an image signal to the frame memory 14. The memory read control circuit 16 inputs a read control signal to the frame memory 14 and controls reading of a subfield image bit signal from the frame memory 14.

The subfield image bit signal, which is a display data signal read from the frame memory 14, is input to the address electrode driving circuit 18. The drive pulse generation circuit 17 generates various drive pulses to be supplied to the electrodes 2 to 4 in order to drive the plasma display panel 1. That is, the drive pulse generation circuit 17 supplies an address electrode drive pulse to the address electrode drive circuit 18, supplies an X electrode drive pulse to the X electrode drive circuit 19, and supplies a Y electrode drive pulse to the Y electrode drive circuit 20. . The address electrode drive circuit 18, the X electrode drive circuit 19, and the Y electrode drive circuit 20 convert each drive pulse into a high voltage pulse and supply it to each of the electrodes 2 to 4. Thus, the plasma display panel 1 is driven.

On the other hand, the image signal input to the frame memory 14 is a subfield image bit information determination circuit 23.
Is also entered. The subfield image bit information determination circuit 23 determines whether or not there is image bit information for each subfield in all effective image regions of the image signal input to the frame memory 14 to be displayed on the plasma display panel 1. Then, the sub-field image bit information is input to the drive pulse batch stop circuit 22 and the drive pulse generation circuit 17 during the reset period.

Drive pulse batch stop circuit 22 during reset period
Is a reset period in which all drive pulses supplied to each of the electrodes 3 and 4 are forcibly stopped during the reset period for the subfield for which the subfield image bit information determination circuit 23 determines that there is no image bit information. The drive pulse batch stop signal is supplied to the drive pulse generation circuit 17.
As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

As shown in FIG. 2, the subfield image bit information determination circuit 23 in FIG.
K flip-flop 231, D flip-flop 23
2. It comprises a selector 233. In this embodiment, since one field is divided into eight subfields in this embodiment, the number of the JK flip-flops 231 is eight, which is the number corresponding to the number of subfields in one field. The terminal J of the JK flip-flop 231 has an MSB
, The data of each bit of LSB is input, the vertical synchronization pulse VD is input to the terminal K, and the write clock CKW is input to the clock terminal. Although not shown here, this write clock CKW is also supplied to the frame memory 14 and is used as a clock for writing an image signal input to the frame memory 14.

Once a high signal is input to the terminal J during one field period, the JK flip-flop 231 holds the output from the terminal Q high during that field period. The output of each of the eight JK flip-flops 231 is the terminal D1 of the D flip-flop 232.
To D8. The vertical synchronization pulse VD is input to the clock terminal of the D flip-flop 232. This D
The flip-flop 232 operates as a delay element, and outputs the output of the JK flip-flop 231 with a delay of one field. That is, the output from the terminals Q1 to Q8 of the D flip-flop 232 is high when the image bit information of the subfield exists, and becomes low when the image bit information of the subfield does not exist at all.

The output of the D flip-flop 232 is input to terminals SF1 to SF8 of the selector 233. The memory read control signal from the memory read control circuit 16 is input to the selector 233. In response to the memory read control signal, the selector 233 sends the frame memory 1
The sub-field image bit information corresponding to the sub-field image bit signal output from No. 4 is selectively output. The image signal is stored in the frame memory 14 as 1
The image bit information of the subfield determined by the subfield image bit information determination circuit 23 is also delayed by one field by the D flip-flop 232, so that the image signal and the image bit information of the subfield are synchronized. doing.

Since the output of the selector 233 is input to the drive pulse batch stop circuit 22 for the reset period as described above, it is necessary to stop the reset discharge in the reset period for the subfield in which no image bit information exists. Can be.

The operation of the subfield image bit information determination circuit 23 shown in FIG. 2 will be further described with reference to FIG. In FIG. 3, (A) shows a vertical synchronization pulse V
D, (B)-(I) show eight JK flip-flops 23
1 Examples of output waveforms at each terminal Q, (J) to (Q)
Represents output waveforms of the terminals Q1 to Q8 of the D flip-flop 232, (R) represents a memory read control signal input to the selector 233, and (S) represents an output waveform of the selector 233.

In one field on the left side shown in FIG. 3, eight JK flip-flops 231 are shown in FIG.
When the waveforms shown in (B) to (I) are output, the D flip-flop 232 holds high or low in one field on the right side, which is the next field, as shown in FIG.
The waveforms shown in (J) to (Q) are output. In addition, 1 on the left
In the field, since the output of the D flip-flop 232 and the output of the selector 233 do not show the state of the previous field, they are hatched as shown in FIGS. 3 (J) to (Q) and (S). Indeterminate.

Then, in one field on the right side shown in FIG. 3, the waveforms shown in FIGS. 3J to 3Q are selected by the memory read control signal shown in FIG. Therefore, the output waveform of the selector 233 becomes the waveform shown in FIG. In the example shown in FIG. 3 (S), the subfields SF1, SF3, S
Since F6 to SF8 are low, these subfields have no signal, and the driving pulse during the reset period is stopped.

As described above, in a certain subfield, all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and which are generated when the input image signal is in a non-signal state are eliminated. be able to. Therefore, the floating of black is suppressed, and the sense of contrast is increased, and accordingly, the display quality is improved. Further, since the driving pulse in the reset period is stopped, wasteful power consumption that does not directly contribute to display discharge can be reduced.

<Second Embodiment> Next, a description will be given of a second embodiment of the drive control device for a plasma display panel display device according to the present invention. FIG. 1 shows a plasma display panel used in the plasma display panel display device of the present invention.
9 and FIG.

First, a second embodiment of the drive control device of the present invention will be systematically described with reference to FIG. In FIG. 9, RST is a reset period, ADR is an address period, S
US is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is indicated by “present” or “absent”, and the X electrodes 3 and Y1 indicated by X
The presence or absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is represented by “４” and “X” in the Y electrodes 4 indicated by Yn. FIG. 9 shows a case where there is no image bit information in only the subfield SF8 in all effective image areas displayed by the plasma display panel display device.

As can be seen from FIG. 9, when a state in which no image bit information is present in the subfield is detected, drive pulses (erase pulse, write pulse, By stopping the supply of (1), all reset discharges to be discharged between the X electrode 3 and the Y electrode 4 are stopped. Further, in the address period, for example, the supply of drive pulses (sustain voltage hold pulse, scan pulse) to the X electrode 3 and the Y electrode 4 is all stopped.

Specifically, in the subfield SF8 in which no image bit information is present, as shown in FIG.
Stop all the pulses to be supplied to 4 and force no pulses to be applied. In the other subfields SF1 to SF7 where the image bit information exists, as in the conventional case, a pulse is supplied to each of the electrodes 3 and 4 also in the reset period and the address period as shown in FIG.

According to the driving method shown in FIG. 8, FIG.
Similarly, in order to obtain 256 gradations (8 bits), one field (16.6 ms) is divided into eight subfields (SF1 to SF8) having different relative ratios of luminance, and the LSB (LSB) of the image bit information is divided. When subfields are configured in order from the least significant bit) to the MSB (most significant bit), FIG.
As shown by 0, the reset period and the address period in each subfield are a pause period in the subfield SF8 in which no image bit information is present, and are the conventional reset periods and address periods in the other subfields SF1 to SF7. .

Here, the configuration of the drive control device of the plasma display panel display device for realizing the second embodiment will be described with reference to FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be appropriately omitted. The subfield image bit information output from the subfield image bit information determination circuit 23 is input to the reset period drive pulse batch stop circuit 22, the address period drive pulse batch stop circuit 24, and the drive pulse generation circuit 17.

Reset period drive pulse batch stop circuit 22
Is a reset period in which all drive pulses supplied to each of the electrodes 3 and 4 are forcibly stopped during the reset period for the subfield for which the subfield image bit information determination circuit 23 determines that there is no image bit information. The drive pulse batch stop signal is supplied to the drive pulse generation circuit 17.
As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

The address period drive pulse batch stop circuit 24 includes a sub-field image bit information determination circuit 23.
For the sub-field determined to have no image bit information, the driving pulse generation circuit generates an address period driving pulse batch stop signal for forcibly stopping all the driving pulses supplied to each of the electrodes 3 and 4 during the address period. 17. Thus, the drive pulse in the address period is stopped for the subfield for which it is determined that no image bit information exists.

As described above, in the specific subfield, all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and occurred when no input image bit information is present are eliminated. be able to. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved. Further, since the driving pulses in the reset period and the address period are stopped, power consumption can be further reduced as compared with the first embodiment.

<Third Embodiment> Further, a third embodiment of the drive control device for a plasma display panel display device of the present invention will be described. The plasma display panel used for the plasma display panel display device of the present invention is the same as in FIGS.

First, a third embodiment of the drive control device of the present invention will be systematically described with reference to FIG. In FIG. 13, RST is a reset period, ADR is an address period,
SUS is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is indicated by “present” or “absent”, and the X electrodes 3 and Y1 indicated by X
The presence or absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, scan pulse, sustain pulse) is represented by “４” and “X” in the Y electrodes 4 indicated by Yn. FIG. 13 shows a case where no image bit information exists in only the subfield SF8 in all the effective image areas displayed by the plasma display panel display device.

As can be seen from FIG. 13, when a state in which no image bit information exists in the subfield is detected, the drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 are reset during the reset period. By stopping the supply, the X electrode 3 and the Y electrode 4
And all the reset discharges discharged between them are stopped. Further, in the sustain discharge period, all the supply of the driving pulse (sustain pulse) to the X electrode 3 and the Y electrode 4 is stopped.

Specifically, in the subfield SF8 in which no image bit information exists, as shown in FIG. 12, all the pulses to be supplied to the electrodes 3 and 4 in the reset period and the sustain discharge period are stopped. Then, no pulse is forcibly applied. In the other subfields SF1 to SF7 where the image bit information exists, a pulse is supplied to each of the electrodes 3 and 4 also in the reset period and the sustain discharge period as shown in FIG.

According to the driving method shown in FIG. 12, FIG.
Similarly to 2, in order to obtain 256 gradations (8 bits), 1
Field (16.6 ms) with different relative ratio of luminance 8
When the image data is divided into subfields (SF1 to SF8) and the subfields are sequentially formed from the LSB (least significant bit) to the MSB (most significant bit) of the image bit information, as shown in FIG. The reset period and the sustain discharge period are idle periods in the subfield SF8 in which no image bit information is present, and are the conventional reset periods and sustain discharge periods in the other subfields SF1 to SF7.

Here, a configuration of a plasma display panel display device for realizing the third embodiment will be described with reference to FIG. 11, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The subfield image bit information output from the subfield image bit information determination circuit 23 is output to the reset period drive pulse batch stop circuit 22 and the sustain discharge period drive pulse batch stop circuit 2
5, input to the drive pulse generation circuit 17.

Drive pulse batch stop circuit 22 during reset period
Is a reset period in which all drive pulses supplied to each of the electrodes 3 and 4 are forcibly stopped during the reset period for the subfield for which the subfield image bit information determination circuit 23 determines that there is no image bit information. The drive pulse batch stop signal is supplied to the drive pulse generation circuit 17.
As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

The sustain discharge period drive pulse batch stop circuit 25 includes a subfield image bit information determination circuit 23.
For the subfield determined to have no image bit information, the driving pulse for the sustain discharge period drive pulse collective stop signal for forcibly stopping all the drive pulses supplied to the electrodes 3 and 4 during the sustain discharge period It is supplied to the generation circuit 17. Thus, the drive pulse in the sustain discharge period is stopped for the subfield for which it is determined that no image bit information exists.

As described above, in the specific subfield, all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell unit 5 and occurred when no input image bit information exists at all are eliminated. be able to. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved. Further, since the driving pulses in the reset period and the sustain discharge period are stopped, the power consumption can be further reduced as compared with the first embodiment.

<Fourth Embodiment> Next, a description will be given of a fourth embodiment of the drive control device for a plasma display panel display device according to the present invention. The plasma display panel used for the plasma display panel display device of the present invention is the same as in FIGS.

First, a fourth embodiment of the driving method according to the present invention will be systematically described with reference to FIG. In FIG. 17, RST is a reset period, ADR is an address period, S
US is a sustain discharge period. In the address electrodes 2 indicated by A1 to Am, the presence / absence of an address pulse is indicated by “present” or “absent”, and the X electrodes 3 and Y1 indicated by X
The presence or absence of drive pulses (erase pulse, write pulse, sustain voltage hold pulse, sustain pulse) is represented by “４” and “X” in the Y electrodes 4 indicated by Yn. FIG. 17 shows a case where there is no image bit information in only the subfield SF8 in all the effective image areas displayed by the plasma display panel display device.

As can be seen from FIG. 17, when a state where no image bit information is present in the subfield is detected, drive pulses (erase pulse, write pulse) to the X electrode 3 and the Y electrode 4 during the reset period. By stopping the supply, the X electrode 3 and the Y electrode 4
And all the reset discharges discharged between them are stopped. Further, in both the address period and the sustain discharge period, X
The supply of drive pulses (sustain voltage hold pulse, scan pulse, sustain pulse) to the electrode 3 and the Y electrode 4 is all stopped.

More specifically, in the subfield SF8 in which no image bit information is present, as shown in FIG. 16, during the reset period, the address period, and the sustain discharge period, the data is supplied to the electrodes 3 and 4. All the pulses to be stopped are stopped, so that no pulse is applied. In the other subfields SF1 to SF7 where the image bit information exists, a pulse is supplied to each of the electrodes 3 and 4 also in the reset period and the sustain discharge period as shown in FIG.

According to the driving method shown in FIG.
Similarly to 2, in order to obtain 256 gradations (8 bits), 1
Field (16.6 ms) with different relative ratio of luminance 8
When the image data is divided into subfields (SF1 to SF8) and the subfields are formed in order from the LSB (least significant bit) to the MSB (most significant bit) of the image bit information, as shown in FIG. The reset period, the address period, and the sustain discharge period are idle periods in the subfield SF8 in which no image bit information is present, and are the conventional reset periods, address periods, and sustain discharge periods in the other subfields SF1 to SF7.

Here, the configuration of the plasma display panel display of the fourth embodiment will be described with reference to FIG. 15, the same parts as those of FIG. 1 are denoted by the same reference numerals, and the description thereof will be appropriately omitted. The sub-field image bit information output from the sub-field image bit information determination circuit 23 includes a reset period drive pulse batch stop circuit 22, an address period drive pulse batch stop circuit 24, a sustain discharge period drive pulse batch stop circuit 25, and a drive pulse generation. Input to the circuit 17.

Drive pulse batch stop circuit 22 for reset period
Is a reset period in which all drive pulses supplied to each of the electrodes 3 and 4 are forcibly stopped during the reset period for the subfield for which the subfield image bit information determination circuit 23 determines that there is no image bit information. The drive pulse batch stop signal is supplied to the drive pulse generation circuit 17.
As a result, the reset discharge in the reset period is stopped for the subfield for which it is determined that no image bit information exists.

The address period drive pulse batch stop circuit 24 is provided with a sub-field image bit information determination circuit 23.
For the sub-field determined to have no image bit information, the driving pulse generation circuit generates an address period driving pulse batch stop signal for forcibly stopping all the driving pulses supplied to each of the electrodes 3 and 4 during the address period. 17. Thus, the drive pulse in the address period is stopped for the subfield for which it is determined that no image bit information exists.

Further, the sustain discharge period drive pulse collective stop circuit 25 includes a subfield image bit information determination circuit 2.
For the subfield for which it is determined that there is no image bit information according to 3, the driving pulse collective stop signal for driving the sustaining discharge period for forcibly stopping all the driving pulses supplied to the electrodes 3 and 4 during the sustaining discharge period is driven. It is supplied to the pulse generation circuit 17. Thus, the drive pulse in the sustain discharge period is stopped for the subfield for which it is determined that no image bit information exists.

As described above, in a specific subfield, all auxiliary discharges (reset discharges) which are not directly related to the display discharge of the discharge cell section 5 and occurred when no input image bit information is present are eliminated. be able to. Therefore, the floating of black is suppressed, and the sense of contrast is enhanced, and accordingly, the display quality is improved. Further, since the drive pulse in all of the reset period, the address period, and the sustain discharge period is stopped, the power consumption can be further reduced as compared with the first to third embodiments.

In the first to fourth embodiments, the plasma display panel display device including the AC type plasma display panel 1 has been described. However, the drive control device of the present invention employs a plasma display panel including the DC type plasma display panel. In addition to performing display discharge (display write discharge and sustain discharge), including display panel display devices,
The present invention can be similarly applied to all plasma display panel display devices that also perform auxiliary discharge (auxiliary discharge not directly related to display discharge). For example, in a plasma display panel display device in which an auxiliary discharge not directly related to the halftone display is performed in the address period, similarly, the driving pulse related to the auxiliary discharge is stopped.

Further, the present invention relates to FIG. 1 and FIG.
It is not limited to the configuration of FIG. 7, FIG. 11, and FIG.
Various changes can be made without departing from the spirit of the present invention. As an example, in the present embodiment, the drive pulse in each period is stopped using the reset period drive pulse batch stop circuit 22, the address period drive pulse batch stop circuit 24, and the sustain discharge period drive pulse batch stop circuit 25. The following configuration may be adopted. That is, the subfield image bit information output from the subfield image bit information determination circuit 22 is input to the X electrode driving circuit 19 and the Y electrode driving circuit 20, and the X electrode driving circuit 19 and the Y electrode driving circuit 20 By setting the voltage value to 0, the drive pulse supplied (applied) to the plasma display panel 1 in each period can be stopped.

[0073]

As described in detail above, the drive control device for a plasma display panel display device of the present invention is:
A memory for storing image signals, a memory write control circuit for controlling writing of image signals to the memory, a memory read control circuit for controlling to read image bit signals from the memory for each subfield, A subfield image bit information determination circuit that determines whether image bit information exists or not, and a subfield that determines that image bit information does not exist at all by the subfield image bit information determination circuit, Since the configuration is provided with the reset period driving pulse stopping means for stopping the driving pulse, the black level can be lowered and the contrast can be improved. In addition, power consumption can be reduced. Further, if an address period driving pulse stopping unit for stopping the driving pulse in the address period and a sustain discharge period driving pulse stopping unit for stopping the driving pulse in the sustain discharge period are further provided, the power consumption can be reduced more efficiently. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 2;

FIG. 4 is a diagram showing an example of a driving waveform for explaining a display operation according to the first embodiment of the present invention.

FIG. 5 is a diagram systematically showing a first embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of an operation in a case where halftone display is performed by subfield division in the first embodiment of the present invention.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing an example of a driving waveform for explaining a display operation according to a second embodiment of the present invention.

FIG. 9 is a diagram systematically showing a second embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of an operation in a case where halftone display is performed by subfield division according to the second embodiment of the present invention.

FIG. 11 is a block diagram showing a third embodiment of the present invention.

FIG. 12 is a diagram showing an example of a driving waveform for explaining a display operation according to a third embodiment of the present invention.

FIG. 13 is a view systematically showing a third embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of an operation in a case where halftone display is performed by subfield division in the third embodiment of the present invention.

FIG. 15 is a block diagram showing a fourth embodiment of the present invention.

FIG. 16 is a diagram showing an example of a driving waveform for explaining a display operation according to a fourth embodiment of the present invention.

FIG. 17 is a diagram systematically showing a fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating an example of an operation when a halftone display is performed by subfield division according to the fourth embodiment of the present invention.

FIG. 19 is a plan view schematically showing a three-electrode surface discharge type plasma display panel.

FIG. 20 is a partial perspective view showing an example of a cross section of a three-electrode surface discharge type plasma display panel.

FIG. 21 is a diagram showing an example of a driving waveform for explaining a display operation according to a conventional example.

FIG. 22 is a diagram showing an example of an operation in the case of performing halftone display by subfield division in a conventional example.

FIG. 23 is a diagram systematically showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Plasma display panel 2 Address electrode 3 X electrode 4 Y electrode 5 Discharge cell part 14 Frame memory 15 Memory write control circuit 16 Memory read control circuit 17 Drive pulse generation circuit 18 Address electrode drive circuit 19 X electrode drive circuit 20 Y electrode drive circuit 22 Reset period drive pulse batch stop circuit (reset period drive pulse stop means) 23 Subfield image bit information determination circuit 24 Address period drive pulse batch stop circuit (address period drive pulse stop means) 25 Sustain discharge period drive pulse batch stop circuit ( Sustain discharge period drive pulse stopping means)

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[Procedure amendment]

[Submission date] March 7, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

The Y electrode 4 is fixed at a voltage of Va, which is the same potential as the address pulse, during most of the address period. Y1 to electrode Yn
, A scan pulse for applying a voltage of 0 V in the same phase as the address pulse is applied in order one row at a time. Thus, only when the address pulse is applied to the address electrode 2 and the scan pulse is applied to the Y electrode 4, the voltage Va is superimposed on the remaining wall charge after the reset period, and the discharge start voltage As described above, a display write discharge occurs, and image bit information is written. Further, at this time, wall charges remain in the discharge cell portion 5 as in the above-described all-screen batch writing in the reset period.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

In the sustain discharge period, the Y electrode 4 and the X electrode
Sustain pulses for maintaining discharge are applied to the electrodes 3 alternately. At this time, the address electrode 2 has been fixed to 0V, and re-discharge only in amounts and sub <br/> stearyl impulses wall charges remaining on the image bit information discharge cell unit 5 which is written in the address period (Sustain discharge). Therefore, in the sustain discharge period, the discharge continues only as many times as the number of times the sustain pulse is applied, only in the discharge cell unit 5 in which the image bit information is written in the address period. As described above, in the AC type plasma display panel, the panel can have a memory function by remaining wall charges in the cell itself.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

Each subfield is composed of a reset period, an address period, and a sustain discharge period, as described above. The reason why the length of the sustain period differs for each subfield is that the number of sustain pulses (sustain pulses) corresponding to bit weighting is applied. The number of sustain pulses actually applied is 1, 2, 4,
.., 128, and the N
A double (N is a positive integer) pulse number is applied.

Claims (3)

[Claims] 1. A method according to claim 1, wherein one sub-field is divided into a plurality of sub-fields to perform halftone display of an image signal, and said sub-field is composed of a reset period, an address period, and a sustain discharge period. In the plasma display panel display device, a display discharge related to the halftone display of the image signal is performed in the sustain discharge period, and an auxiliary discharge not directly related to the halftone display is performed in the reset period or the address period. In the drive control device, a memory that stores the image signal; a memory write control circuit that controls writing of the image signal to the memory; and a memory read control that controls the image signal to be read from the memory for each subfield. Circuit and image bit information in one subfield A sub-field image bit information determination circuit that determines whether or not to perform a drive pulse in the reset period for a sub-field that has determined that the image bit information does not exist at all by the sub-field image bit information determination circuit. A drive control device for a plasma display panel display device, comprising: a reset period drive pulse stopping means for stopping. 2. An address period drive pulse stopping means for stopping a drive pulse in the address period for a subfield for which the subfield image bit information determination circuit determines that the image bit information does not exist at all. 2. The drive control device for a plasma display panel display device according to claim 1, wherein the drive control device is configured as follows. 3. A sustain discharge period drive pulse stop means for stopping a drive pulse in the sustain discharge period for a subfield for which the image bit information is determined not to exist at all by the subfield image bit information determination circuit. The drive control device for a plasma display panel display device according to claim 1, further comprising: