KR100528694B1 - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel designed to reduce address time.

A driving method of a plasma display panel according to the present invention is a method of driving a plasma display panel which displays an image by dividing the image into a plurality of subfields each including an initialization period, a first address period, a second address period, and a sustain period for one frame period. To

At least one first subfield that selects an off-cell by using an erase discharge and an on-cell by using a write discharge, and at least one agent that selects off-cells among on-cells previously turned on by using an erase discharge. It is characterized by including two subfields.

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to reduce an address time.

Recently, there is a growing interest in flat panel displays that can reduce the weight and volume of cathode ray tubes. Such flat panel displays include liquid crystal displays, plasma display panels (PDPs), field emission displays, and electro-luminescence.

Among such flat panel display devices, the plasma display panel emits phosphors by 147 nm ultraviolet rays generated when the He + Xe, Ne + Xe or He + Xe + Ne gas is discharged to display images and video including characters or graphics. . The plasma display panel is not only thin and large in size, but also recently, due to technology development, the plasma display panel provides greatly improved image quality.

In particular, the three-electrode AC surface discharge type plasma display panel accumulates wall charges using a dielectric layer during discharging, thereby lowering the voltage required for discharging, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering of plasma.

Referring to FIG. 1, a discharge cell of a three-pole current alternating surface discharge plasma display panel is formed on a scan electrode (Y) and a sustain electrode (Z) formed on an upper substrate (10), and a lower substrate (18). The address electrode X is provided.

Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one side edge of the transparent electrode. 13Z). Indium tin oxide (ITO) is generally used as a material of the transparent electrodes 12Y and 12Z. As the material of the metal bus electrodes 13Y and 13Z, a metal such as chromium (Cr) is usually used. The metal bus electrodes 13Y and 13Z serve to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. An upper dielectric layer 14 and a passivation layer 16 are stacked on the upper substrate 10 on which the scan electrode Y and the sustain electrode Z are formed. In the upper dielectric layer 14, charged particles generated by gas discharge ionization gas (plasma) are accumulated. The protective layer 16 protects the upper dielectric layer 14 from sputtering of charged particles generated during gas discharge and increases the emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed.

The phosphor layer 26 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is formed to be parallel to the address electrode X to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is emitted by ultraviolet rays generated during gas discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne for discharging is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, such a three-electrode AC surface discharge type plasma display panel is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for generating discharge uniformly, an address period for selecting a Banggen cell, and a sustain period for implementing gray levels according to the number of discharges. In the case where an image is to be displayed with 265 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. Each of the eight subfields is subdivided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0, 1, 2, 3, 4, 5, 6, 7) is increased in proportion. In this way, gray levels can be implemented by using a combination of subfields having different sustain periods.

The driving method of the plasma display panel is roughly classified into a selective writing (SW) method and a selective erasing (SE) method according to whether or not the discharge cells are selected by the address discharge.

The selective write (SW) method turns off the selected discharge cells in the address period after turning off the full screen in the reset period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

In the selective writing (SW) method, the pulse width of the scan pulse supplied to the scan electrode Y should be set to about 3 us or more so that sufficient wall charges are formed in the discharge cell by the address discharge. For this reason, in the selective write (SW) method, a relatively long time is taken as an address period, and thus a sustain sustain period is insufficient.

On the other hand, the plasma display panel may generate contour noise in the moving image due to the characteristic of realizing the gray level of the image by the combination of the subfields. When pseudo contour noise occurs, the pseudo contour appears on the screen, and thus the display quality of the screen is deteriorated.

In order to solve the problem of poor display quality in the selective writing (SW) method, when the number of subfields of one frame includes 10 or more subfields, it is impossible to secure time for the sustain period. In order to overcome this problem, there is a dual scan method for driving one screen by dividing, but when driving by dividing one screen, there is another problem that the manufacturing cost is increased because the driving drive ICs have to be added as much.

The selective erase (SE) method turns off the selected discharge cells in the address period after the full screen is turned on by discharging the full screen in the reset period. Subsequently, in the sustain period, images are displayed by sustaining discharge only those discharge cells not selected by the address discharge.

In the selective erasing (SE) method, approximately 1us of selective erasing data pulses are supplied to the address electrode X so as to erase the wall charges and the space charges of the selected discharge cells during address discharge, and selective erasing to the scan electrode Y. Approximately 1us of scan pulses are supplied with which the data pulses are synchronized.

As described above, in the selective erase (SE) method, since the address period is smaller than the selective write (SW) method, the display quality can be increased by increasing the number of subfields to reduce the contour noise by increasing the address period or increasing the sustain period to increase luminance.

However, the selective erasing (SE) method has a disadvantage of low contrast because the entire surface is turned on during the entire writing period, which is a non-display period, as shown in FIG. 3. In the selective erase (SE) driving method, since the screen is bright as long as the sustain period is sufficiently secured, the screen is not clear and the image is blurred.

As described above, in the conventional plasma display panel driving method, the selective writing (SW) method cannot be driven at high speed because of an long address period. The selective erase (SE) method has the advantage of being able to drive at high speed because the address period is shorter than the selective write (SW) method, whereas the contrast is poor because the full discharge cells must be turned on during the non-display period. There are disadvantages.

In addition, since the reset period is increased due to the maximum of 12 reset pulses, the display period (sustain period) is relatively short.

In order to solve the above problems, the applicant of the present invention writes a selective write and erase (SWSE) subfield mapping (SWSE SFM) method to implement the grayscale by combining the selective write (SW) subfield and the selective erase (SE) subfield It has been proposed through the domestic patent applications No. 10-2000-0012669, 10-2000-0053214, 10-2001-0003003, 10-2001-0006492.

4 is a waveform diagram illustrating a driving waveform of a conventional selective write and erase method.

5 is a diagram illustrating stepwise formation of wall charges of the selective write subfield illustrated in FIG. 4.

4 and 5, in the conventional SWSE method, one frame is divided into a selective write (SW) section and a selective erase (SE) section. The selective writing (SW) section and the selective erasing (SE) section are divided into a plurality of subfields (SF). Each subfield has an initialization period for initializing the full screen of the panel, an address period for selecting a cell, and a selected period. It is divided into a sustain period for maintaining the discharge of the cell.

In the initialization period of the selective writing (SW) period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the initialization period. This rising ramp waveform (Ramp-up) causes a weak discharge in the cells of the full screen to form wall charges in the cells. On the other hand, a ground voltage (0V) is applied to the sustain electrodes (Z). In addition, after the rising ramp waveform Ramp-up is raised to the peak voltage Vr in the setup period, the voltage of the peak voltage Vr is supplied to the scan electrodes Y for a predetermined time. When the peak voltage Vr of the rising ramp waveform Ramp-up is maintained for a predetermined time, wall charges formed in the discharge cells are strengthened.

Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges. The necessary wall charges will remain uniform.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse data is applied as in the time point T2 of FIG. 4. In the cells selected by the address discharge, wall charges necessary for sustain discharge are formed as in the time point T3 of FIG. 4.

On the other hand, sufficient wall charges are formed on the scan electrode Y and the sustain electrode Z in the sustain electrodes Z during the set-down period and the address period, and erroneous discharges between the sustain electrode Z and the address electrode X are prevented. To prevent this, a positive DC voltage of Vz less than the sustain voltage Vs is supplied.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse (sus) is applied while the wall voltage and the sustain pulse (sus) in the cell are added. Discharge occurs.

The subfields of the selective erasing (SE) section have the same holding period, and when the cells that are ON in the last subfield of the selective writing (SW) section address addressing in the selective erasing (SE) section, It is a clear drive system that turns off and stays on otherwise.

By using the clear driving method as shown in Table 1 below, the reset pulse used in the selective write (SW) section is not necessary in the selective erase (SE) section. Therefore, the number of reset pulses is reduced by the number of selective erase subfields.

Gradation SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8 SF9 SF10 0 × × × × × × × × × × One ○ × × × × × × × × × 3 ○ ○ × × × × × × × × 7 ○ ○ ○ × × × × × × × 15 ○ ○ ○ ○ × × × × × × 31 ○ ○ ○ ○ ○ × × × × × 63 ○ ○ ○ ○ ○ ○ × × × × 111 ○ ○ ○ ○ ○ ○ ○ × × × 159 ○ ○ ○ ○ ○ ○ ○ ○ × × 207 ○ ○ ○ ○ ○ ○ ○ ○ ○ × 255 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

The reset pulse of the reset period is used only in the six selective write subfields and the selective erase method is used in the remaining six subfields to improve the luminance and reduce the addressing time to ensure the display period (sustain period).

However, the conventional SWSE method has a relatively short address period compared to other driving methods. However, even in the recent trend of high resolution and high quality, even the SWSE-based address period is long. In other words, although the address period is drastically reduced in the conventional SWSE-selective erase subfields, the address period required for the selective write subfields is relatively long, so that it is difficult to reduce the address period to correspond to high resolution and high quality. Do.

Accordingly, it is an object of the present invention to provide a plasma display panel designed to reduce address time.

In order to achieve the above object, a driving method of a plasma display panel according to a first embodiment of the present invention includes an address period for selecting a cell in parallel with an erase discharge and a write discharge.

The driving method of the plasma display panel according to the first embodiment of the present invention includes an initialization period for initializing the plasma display panel and a sustain period for displaying the selected cell.

A method of driving a plasma display panel according to a second embodiment of the present invention uses at least one first subfield to select an off-cell by using an erase discharge and an on-cell by using a write discharge, and an erase discharge. And at least one second subfield for selecting offcells among previously on cells.

The first subfield includes an initialization period for initializing the plasma display panel, a first address period for selecting the offcell using erase discharge, and a second address period for selecting the on cell using write discharge. And a sustain period for maintaining the discharge for the on cell.

The first address period includes applying an erase scan pulse to a scan electrode of a plasma display panel and applying erase data to an address electrode intersecting the scan electrode to cause the erase discharge.

The first address period further includes supplying a base voltage to the sustain electrode parallel to the scan electrode.

The second address period includes applying a common write voltage of a first polarity to a scan electrode of a plasma display panel and applying a common write voltage of a second polarity to an address electrode crossing the scan electrode to cause a write discharge. do.

In the second address period, the common write voltage of the first polarity is applied to the sustain electrode parallel to the scan electrode, and the common address of the second polarity is applied to the address electrode crossing the scan electrode and the sustain electrode parallel to the scan electrode. Applying a write voltage to cause a write discharge.

The second address period includes applying an erase scan pulse to a scan electrode of the plasma display panel and applying erase data to an address electrode intersecting the scan electrode to cause an erase discharge.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a driving method of the plasma display panel according to the present invention will be described in detail with reference to FIGS. 6 to 8.

Referring to FIG. 6, one frame period of a plasma display panel according to an embodiment of the present invention includes selective write subfields SF1 to SF6 for selecting an on-cell in parallel with an erase discharge and a write discharge. And selective erase subfields SF7 to SF12 for selecting an off-cell as an erase discharge.

Each of the selective write subfields SF1 to SF6 has an initialization period for uniformly forming a certain amount of wall charge in the cells of the full screen, a first address period for selecting an off-cell using an erase discharge, and an on-cell as a write discharge. a second address period for selecting on-cell) and a sustain period for causing sustain discharge for the selected on cell. Further, it may be included in all or part of the selective write subfields SF1 to SF6 for erasing residual charges generated by the sustain discharge following the sustain period.

Each of the selective erasing subfields SF7 to SF12 includes an address period for selecting an off cell as an erase discharge and a sustain period for causing sustain discharge for the on cells.

The number of selective write subfields and selective erase subfields included in one frame period may be adjusted as necessary.

The selective write subfields SF1 to SF6 will be described in detail.

During the reset period of the selective write subfields SF1 to SF6, ramp waveforms of rising slopes rising up to the setup voltage Vr are simultaneously applied to all scan electrode lines Y, and at the same time, 0 V or the base voltage ( GND is applied to the sustain electrode lines Z and the address electrode lines X. Light is generated between the scan electrode lines Y and the address electrode lines X and between the scan electrode lines Y and the sustain electrode lines Z in the cells of the full screen by the rising ramp waveform RPSU. Dark discharge occurs that rarely occurs. This setup discharge causes positive wall charges to accumulate on the address electrode lines X and the sustain electrode lines Z, and negative wall charges on the scan electrode lines Y. Will accumulate. The wall charges of negative polarity (−) stacked on the scan electrode lines (Y) are equal to the total amount of wall charges of positive polarity (+) stacked on the address electrode lines (X) and the sustain electrode lines (Z). After the set-up discharge has occurred, the scan electrode lines Y have a ramp ramp of a falling slope falling from a positive voltage lower than the set-up voltage Vr, for example, the sustain voltage Vs to a predetermined set-down voltage. ) Is applied to the sustain electrode lines (Z) and a direct current voltage is applied to maintain the sustain voltage (Vs). Due to the voltage difference between the falling ramp waveform Ramp-down and the DC voltage, dark discharge with little light is generated between the scan electrode lines Y and the sustain electrode lines Z. In addition, a dark discharge occurs between the scan electrode lines (Y) and the address electrode lines (Z) during a period in which the falling ramp waveform (Ramp-down) falls. The set-down discharge due to the ramp ramp down eliminates excessive wall charges that do not contribute to the address discharge among the charges generated by the ramp ramp RPSU.

In the first address period of the selective write subfields SF1 to SF6, an erase scan pulse escn of about 1 mW falling to the negative voltage is sequentially applied to the scan electrode lines Y and at the same time the erase scan pulse ( An erase data pulse of Va voltage is applied to the address electrode lines X in synchronization with escn). As the voltage difference between the erase scan pulse escn and the erase data pulse and the wall voltage in the previously accumulated cell are added, an erase discharge is generated in the cell to which the erase data pulse is applied to erase the wall charge. During the first address period, 0 V or the ground voltage GND is applied to the sustain electrode line Z so that an erase discharge can occur between the address electrode line X and the scan electrode line Y. The offcells selected by the erase discharge do not generate a discharge even when the common write voltage is applied in the second address period, and also do not occur when the sustain voltage is applied during the sustain period.

In the second address period of the selective write subfields SF1 to SF6, a negative common write pulse wscn having a larger pulse width than the erase scan pulse escn is simultaneously applied to the scan electrode lines Y and at the same time a common write. The common pulse of positive polarity synchronized with the pulse wscn is applied to the address electrode lines X and the sustain electrode lines Z. FIG. Then, write discharges occur to oncells in which the erase discharges do not occur in the first address period. When the sustain voltage is applied in the subsequent sustain period, these on cells are discharged because the wall voltage in the cell is sufficient.

In the sustain periods of the selective write subfields SF1 to SF6, sustain pulses whose number is determined according to the luminance weight are alternately applied to the scan electrode lines Y and the sustain electrode lines Z. Then, the on-cells selected by the write discharge in the second address period but not selected in the first address period are discharged every sustain pulse as the wall voltage and the external sustain voltage in the cell are added.

The erase address periods of the selective erase subfields SF7 to SF12 select an off-cell by causing an erase discharge by adding a negative erase scan pulse, a voltage difference between the erase data, and a wall voltage in the cell.

The sustain periods of the selective erase subfields SF7 to SF12 cause a discharge every sustain pulse for oncells not selected in the address period.

7 and 8 are diagrams showing clearly the discharge mechanism of the on-cell or off-cell selected during the address period of the selective write subfields SF1 to SF12.

7 shows a discharge mechanism in which an off cell selected from the selective write subfields SF1 through SF6 is selected.

Referring to FIG. 7, erase discharges occur at the time t2 when the wall charges in the cell at the time t1 immediately after the initialization period ends. In this erase discharge, the wall charges in the cell are erased. Therefore, even when the common discharge voltage is applied during the second address period, the cell in which the erasure discharge has occurred does not cause the write discharge so that no wall charge is formed. Even when an external sustain voltage is applied to the cell at the time t3 at which the sustain period starts, discharge does not occur because the wall voltage in the cell is small.

8 shows a discharge mechanism in which an on-cell selected from the selective write subfields SF1 through SF6 is selected.

Referring to FIG. 8, when the erase discharge does not occur at the time t2 and the common write voltage is applied at the time t2 ′, the write discharge occurs while the wall voltage and the external common write voltage in the cell are added. This write discharge maintains a sufficient amount of wall charges in the on-cell until the sustain period starts. When an external sustain voltage is applied to the on-cell at time t3, the external sustain voltage and the wall voltage in the cell are added to each sustain pulse. Discharge occurs every time.

In the case of using the SWSE driving method according to the present invention, an effect of shortening an address time is as follows. FIG. 9 illustrates an address driving waveform applied to each scan line during a selective write subfield period in the conventional SWSE driving method. 10 is a diagram illustrating an address driving waveform applied to each scan line during a selective write subfield period in the SWSE driving scheme according to the present invention. Referring to FIG. 9, the conventional SWSE driving scheme is optional. During the write period, write scan pulses of about 3 ms are sequentially applied to the scan electrode lines Y1 to Yn. Therefore, if the PDP has VGA (Video Graphics Array) resolution, it has 480 scan lines. Therefore, the address period during the selective writing period is 3 ms (pulse width of scan pulse) × 480 lines × 6 (subfield). Number). That is, it has an address timing of 8.64 ms. Referring to FIG. 10, in the SWSE driving method according to the present invention, about 1 is sequentially applied to the scan electrode lines Y1 to Yn during the first address period in the selective writing period. An erase scan pulse escn of about ㎲ is applied, and a common write pulse wscn is simultaneously applied to the scan electrode lines Y1 to Yn during the second address period. Therefore, in a PDP with VGA resolution, the address period during the selective write interval is {1 ms (pulse width of erased scan pulse) x 480 lines + 3 ms (pulse width of common write pulse)} x 6 (subfield). Is calculated. That is, it has an address timing of 2.89 ms. Therefore, the SWSE driving method according to the present invention can significantly reduce the address timing. Table 2 shows gray scale expressions of the plasma display panel according to the embodiment of the present invention.

Gradation SF1 (1) SF2 (2) SF3 (4) SF4 (8) SF5 (16) SF6 (32) SF7 (32) SF8 (32) SF9 (32) SF10 (32) SF11 (32) SF12 (32) 0 to 31 Binary coding × × × × × × × 32-63 Binary coding ○ × × × × × × 64 to 95 Binary coding ○ ○ × × × × × 96-127 Binary coding ○ ○ ○ × × × × 128-159 Binary coding ○ ○ ○ ○ × × × 160-191 Binary coding ○ ○ ○ ○ ○ × × 192-223 Binary coding ○ ○ ○ ○ ○ ○ × 224-255 Binary coding ○ ○ ○ ○ ○ ○ ○

As can be seen from Table 2, the plasma display panel driving method according to the embodiment of the present invention, like the conventional SWSE method, is grayscaled by binary coding using a combination of selective write subfields SF1 to SF6. In addition to the expression, gradation is expressed by linear coding using sequential selection of selective erasure subfields SF7 to SF12.

As described above, in the method of driving the plasma display panel according to the present invention, a conventional SWSE is performed by first selecting a cell by an erase method having a small pulse width in selective write subfields and secondly selecting a cell by using a common write voltage. In contrast to the method, the address time can be greatly reduced without decreasing the gray scale expression ability. As a result, the driving method of the plasma display panel according to the present invention can realize a high quality image in a high resolution plasma display panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a frame diagram illustrating a conventional method for driving a plasma display panel.

3 is a frame diagram illustrating a conventional selective erasing scheme.

4 is a waveform diagram illustrating a driving waveform of a conventional selective write and erase method.

5 is a diagram illustrating an addressing discharge mechanism of the selective write subfield illustrated in FIG. 4.

6 is a waveform diagram showing a driving waveform according to the present invention.

7 is a view showing the wall charge formation of the off-cell (Off) according to the present invention.

8 is a view showing the wall charge formation of the on (On) cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: upper substrate 18: lower substrate

Y: scan electrode Z: sustain electrode

X: address electrode 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14: upper dielectric layer

16: protective film 22: lower dielectric layer

24: partition 26: phosphor layer

Claims (9)

A method of driving a plasma display panel in which an image is displayed by time-division driving one frame period into a plurality of subfields, At least one of the subfields, And an address period for selecting a cell in parallel with an erase discharge and a write discharge. The method of claim 1, The subfield is, An initialization period for initializing the plasma display panel; And a sustain period for displaying the selected cell. A method of driving a plasma display panel in which an image is displayed by time-division driving one frame period into a plurality of subfields, At least one first subfield that selects an off-cell using erase discharge and an on-cell using write discharge; And at least one second subfield for selecting offcells among the oncells previously turned on by using the erasing discharge. The method of claim 3, wherein The first subfield is, An initialization period for initializing the plasma display panel; A first address period for selecting the offcell using the erase discharge; A second address period for selecting the on cell using the write discharge; And a sustain period for maintaining a discharge with respect to said on cell. The method of claim 4, wherein The first address period is And erasing discharge by applying an erase scan pulse to a scan electrode of the plasma display panel and simultaneously applying erase data to an address electrode intersecting the scan electrode. The method of claim 5, The first address period is And supplying a ground voltage to the sustain electrode parallel to the scan electrode. The method of claim 4, wherein The second address period is Applying a common write voltage of a first polarity to a scan electrode of the plasma display panel and applying a common write voltage of a second polarity to an address electrode intersecting the scan electrode to cause the write discharge. A method of driving a plasma display panel. The method of claim 7, wherein The second address period is The common write voltage of the first polarity is applied to the sustain electrode parallel to the scan electrode, and the common write voltage of the second polarity is applied to the address electrode crossing the scan electrode and the sustain electrode parallel to the scan electrode. And driving the write discharge by applying a light source to the plasma display panel. The method of claim 4, wherein The second address period is And erasing discharge by applying an erase scan pulse to a scan electrode of the plasma display panel and simultaneously applying erase data to an address electrode intersecting the scan electrode.