KR100373528B1 - Method of Driving Plasma Display Panel in High Speed - Google Patents

Abstract

The present invention relates to a high speed driving method of a plasma display panel which can drive a plasma display panel at high speed and improve contrast.

A high speed driving method of a plasma display panel according to the present invention comprises the steps of setting a gray value of a plurality of subfields included in an n (n is an arbitrary natural number) frame; and setting a gray level value of at least one subfield among the subfields included in the n + 1th frame differently from a gray level value of the subfields included in the n frame.

Description

{Method of Driving Plasma Display Panel in High Speed}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed driving method of a plasma display panel, and more particularly, to a high speed driving method of a plasma display panel capable of driving a plasma display panel at high speed and improving contrast.

Plasma Display Panels (hereinafter referred to as "PDPs") display images containing characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated upon discharge of He + Xe or Ne + Xe inert mixed gases. do. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided. Each of the scan / sustain electrode 30Y and the common sustain electrode 30Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is formed on one edge of the transparent electrode. Bus electrodes 13Y and 13Z. The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for generating discharge uniformly, an address period for selecting a discharge cell, and a sustain period for implementing gradation according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Will increase. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge in the address period.

In the selective write driving method, the full screen is turned off in the reset period, and then the discharge cells selected in the address period are turned on. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge. In the selective write driving method, the pulse width of the scan pulse supplied to the scan / sustain electrode 30Y is set to approximately 3 [mu] s or more in order to form sufficient wall charges in the discharge cells during the address discharge.

If the PDP has a resolution of VGA (Video Graphics Array), it has a total of 480 scan lines. In this case, when the selective write driving method includes eight subfields within one frame period (16.67 ms), the total address period required in one frame is 11.52 ms. In contrast, the sustain period is assigned 3.05 ms in consideration of the vertical synchronization signal Vsync. In other words, the address period requires 11.52 ms calculated as 3 ms (pulse width of scan pulse) x 480 lines x 8 (number of subfields) per frame. The sustain period is obtained by subtracting an address period of 11.52 ms per frame, a one-time reset period of 0.3 ms, an erase period of 100 ms x 8 subfields = 0.8 ms, and a 1 ms vertical sync signal (Vsync) margin (16.67 ms- 11.52㎳-0.3㎳-1㎳-0.8㎳) the remaining period is 3.05㎳.

On the other hand, in the PDP, contour noise may be generated in a moving picture because of the characteristic of realizing the gray level of the image by the combination of subfields. If pseudo contour noise occurs, the pseudo contour appears on the screen, and thus the display quality is degraded. For example, if the left half of the screen is displayed with a gradation value of 128 and the right half of the screen is displayed with a gradation value of 127, and then the screen is moved to the left side, peak white (Peak White) is displayed at the boundary between the gradation values 128 and 127. That is, a white band appears. On the contrary, when the left half of the screen is displayed with a gradation value of 128 and the right half of the screen is displayed with a gradation value of 127, the screen is moved to the right. A black band will appear. As a method for removing the moving picture pseudo-contour noise, one subfield is divided to add one or two subfields, a sequence of subfields is rearranged, a subfield is added, and a sequence of subfields is added. The rearrangement method and error diffusion method have been proposed. However, in the selective writing method, when a subfield is added to remove moving picture pseudo contour noise, the sustain period is insufficient or cannot be allocated, and thus driving is impossible. In fact, in the selective write driving method, if two subfields of the eight subfields are divided to form one frame with ten subfields, there is no time that can be allocated to the sustain period. In other words, the address period is 14.4 ms calculated as 3 ms (pulse width of scan pulse) x 480 lines x 10 (number of subfields) per frame. In contrast, the sustain period includes an address period of 14.4 ms per frame, one reset period of 0.3 ms, an erase period of 100 ms x 10 (number of subfields) = 1 ms, and a vertical sync signal (Vsync) margin period of 1 ms. Minus (16.67㎳-14.4㎳-0.3㎳-1㎳-1㎳) is -0.03㎳.

As described above, the selective write driving method can secure a sustain period of about 3 ms when one frame is composed of eight subfields. Cannot be allocated and driving becomes impossible. In order to overcome this problem, there is a method of split-driving one screen, but since drive drive integrated circuits (ICs) have to be added as much as that, another problem of increased manufacturing cost occurs. On the other hand, in the case of the selective writing method, when one frame is composed of eight subfields, when the screen is turned on for the entire display period of 3.05 ms, light of 300 cd / m2 corresponding to the brightness of the peak white is emitted. Occurs. On the other hand, if the screen is turned on only during one reset period in one frame and the screen is not turned on at all in the sustain period, 0.7 cd / m 2 of light corresponding to black is generated. Therefore, the darkroom contrast ratio of the selective writing method is about 430: 1.

In the selective erasing driving method, the entire screen is turned on by writing discharge in the reset period, and then the selected discharge cells are turned off in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells not selected by the address discharge. In the selective erasing driving method, approximately 1 [mu] s of selective erase data pulses are supplied to the address electrode 20X so as to erase the wall charges and the space charges of the selected discharge cells during the address discharge. At the same time, the scan / sustain electrode 30Y is supplied with approximately 1 [mu] s scan pulse synchronized with the selective erase data pulse. If the PDP has a VGA (Video Graphic Array) resolution, the selective erasing method includes eight subfields within one frame period (16.67 ms), so that only 3.84 ms of address period is required in one frame. do. In contrast, the sustain period can be sufficiently allocated to about 10.73 ms in consideration of the vertical synchronization signal Vsync. In other words, the address period is 3.84 ms calculated as 1 ms (pulse width of scan pulse) x 480 lines x 8 (number of subfields) per frame. The sustain period is 3.84 ms address period per frame, 0.3 ms reset period, 1 ms vertical sync signal (Vsync) margin, and 100 ms x 8 (number of subfields) = 0.8 ms front lighting. The remaining period, minus the period (16.67㎳-3.84㎳-0.3㎳-1㎳-0.8㎳), is 10.73㎳.

In this manner, in the selective erasing driving method, the sustain period as the display period can be secured even if the number of subfields is increased as the address period is small. For example, if the number of subfields is increased to 10 within one frame, the address period is 4.8 ms calculated as 1 ms (pulse width of scan pulse) x 480 lines x 10 (number of subfields) per frame. In contrast, the sustain period includes an address period of 4.8 ms per frame, a one-time reset period of 0.3 ms, a vertical sync signal (Vsync) margin of 1 ms, and 100 ms x 10 (number of subfields) = 1 ms front lighting. (Writing) minus (16.67 기간 -4.8㎳-0.3㎳-1㎳-1㎳) is 9.57㎳. Therefore, even if the selective erasing driving method increases the number of subfields to 10, the sustaining period of three times or more can be ensured in the selective writing method than when the number of subfields is eight, so that a bright screen with 256 gray levels can be realized. Will be. However, the selective erasing method has a disadvantage in that the contrast is lowered because the full screen is written in the front lighting period which is the non-display period. For example, if a frame is composed of ten subfields SF1 to SF10 as shown in FIG. 2, when the full screen is turned on in the display period of 9.57 ms, the 950cd / m2 corresponding to the peak white brightness is applied. Light is generated. In addition, the brightness of 0.7 cd / m2 generated during one reset period in one frame and the brightness of 1.5 cd / m 2 × 10 (number of subfields) = 15 cd / m2 generated in the front lighting period are 15.7 cd / m 2. Is the brightness corresponding to black. Therefore, when one frame includes 10 subfields SF1 to SF10, the contrast ratio of the selective erasing driving method is 950: 15.7 = 60: 1, so the contrast becomes poor. As a result, in the selective erasing method, since the screen is bright as long as the sustain period is sufficiently secured, the contrast is reduced, and the screen is not clear but feels cloudy.

In order to overcome this problem of poor contrast, a method of completely writing only once per frame and discharging unnecessary discharge cells in each subfield has been proposed. However, in this method, since the next subfield can be driven only when the previous subfield must be turned on, there is a problem in that the image quality is poor because the number of gray scales below is only the number of subfields + 1. That is, if one frame includes 10 subfields, the number of gray levels is 11 as shown in Table 1 below.

Gradation SF1 (1) SF2 (2) SF3 (4) SF4 (8) SF5 (16) SF6 (32) SF7 (48) SF8 (48) SF9 (48) SF10 (48) 0 × × × × × × × × × × One ○ × × × × × × × × × 3 ○ ○ × × × × × × × × 7 ○ ○ ○ × × × × × × × 15 ○ ○ ○ ○ × × × × × × 31 ○ ○ ○ ○ ○ × × × × × 63 ○ ○ ○ ○ ○ ○ × × × × 111 ○ ○ ○ ○ ○ ○ ○ × × × 159 ○ ○ ○ ○ ○ ○ ○ ○ × × 207 ○ ○ ○ ○ ○ ○ ○ ○ ○ × 255 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○

Here, 'SFx (y)' means the x-th subfield and its weight y. '○' indicates a state in which the corresponding subfield is turned on and "x" indicates a state in which the corresponding subfield is turned off.

In this case, since all combinations of red, green, and blue are expressed only 1331 colors, the color expressing ability is remarkably insufficient compared to 16.7 million colors. This type of PDP occurs at 950 cd / m² peak white when full screen is turned on in the display period of 9.57㎳, and at 0.7cd / m² brightness and one front lighting period in one reset period. It has a dark contrast ratio of 430: 1 by means of 2.2 cd / m 2 of black plus 1.5 cd / m 2 of brightness.

As described above, in the conventional PDP driving method, the selective writing method cannot be driven at high speed because the data pulse and the scan pulse for selectively turning on the discharge cells during the address period must have a pulse width of 3 s or more. The selective erase method has the advantage of being able to drive at high speed since the data pulse and the scan pulse for selectively turning off the discharge cells are approximately 1 [mu] s, compared to the selective write method. There is a disadvantage of poor contrast because they turn on.

Accordingly, an object of the present invention is to provide a high speed driving method of a plasma display panel capable of driving a plasma display panel at high speed and improving contrast.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing a frame structure of a conventional plasma display panel.

3 is a diagram illustrating a frame configuration of a plasma display panel according to an embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating a driving waveform supplied to each of the subfields shown in FIG. 3. FIG.

FIG. 5 is a diagram showing a gray scale expression method in a subfield of a frame shown in FIG. 3; FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode

In order to achieve the above object, a high-speed driving method of a plasma display panel according to the present invention includes the steps of setting a gray value of a plurality of subfields included in an n (n is an arbitrary natural number) frame; and setting a gray level value of at least one subfield among the subfields included in the n + 1th frame differently from a gray level value of the subfields included in the n frame.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5.

Referring to FIG. 3, one frame of the PDP according to the present invention includes 10 subfields WSF1 to WSF4 and ESF5 to ESF10 to reduce video pseudo contour noise, and is driven by a selective writing method. WSF1 to WSF4 and subfields ESF5 to ESF10 driven by the selective erasing scheme. The first subfield WSF1 is divided into a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustaining the discharge cells selected by the address discharge, and an erasing period for erasing the sustain discharge. Each of the second and third subfields WSF2 to WSF3 is divided into an optional write address period, a sustain period, and an erase period. The fourth subfield WSF4 is divided into an optional write address period and a sustain period. In the first to fourth subfields WSF1 to WSF4, the selective write address period and the erase period are the same for each subfield, while the luminance relative ratio increases at a predetermined ratio. At this time, the fourth subfield WSF4 is set to a luminance relative ratio of 2 ⁵ . The fifth to tenth subfields ESF5 to ESF10 sustain sustain discharge of discharge cells other than the discharge cells selected by the address discharge and the selective erase address period for turning off the selected discharge cells without a full-surface writing over-writing period. Divided into periods. In the fifth to tenth subfields ESF5 to ESF10, the selective erase address period and the sustain period are set to be the same. Here, the sustain period of the fifth to tenth subfields ESF5 to ESF10 is set to a luminance relative ratio of 2 ⁵ so as to have the same luminance relative ratio as that of the fourth subfield WSF4.

4 is a waveform diagram illustrating a driving waveform of a PDP according to an embodiment of the present invention.

Referring to FIG. 4, selective write data SWD is supplied to the address electrode lines X during the address period of the first to fourth subfields WSF1 to WSF4, and the fifth to tenth subfields ( The selective erase data SED is supplied during the address period of ESF5 to ESF10. The scan / sustain electrode lines Y are supplied with approximately 3 ms of scan pulse -SWSCN during the address period of the first to fourth subfields WSF1 to WSF4, and the fifth to tenth subfields (S). During the address period of ESF5 to ESF10, approximately 1 ms of scan pulse (-SESCN) is sequentially supplied.

First, as the reset period of the first subfield WSF1 starts, the positive reset pulse RSTP is commonly supplied to the common sustain electrode lines Z. Subsequently, the positive ramp wave RPS1, the negative pulse -CRP, and the positive ramp wave RPS2 are sequentially supplied to the scan / sustain electrode lines Y. Then, the discharge cells of the full screen are uniformly accumulated wall charges due to the reset discharge and are turned off by discharging, holding and erasing the lamp waves RPS1 and RPS2 and the negative pulse (-CRP). Subsequently, in the address period of the first subfield WSF1, the selective write data SWD corresponding to the logic value “1” of the video data is supplied to the address electrode lines X. FIG. In synchronism with this selective write data SWD, negative scan pulses -SWSCN having a pulse width of approximately 3 ms are sequentially supplied to the scan / sustain electrode lines Y sequentially. The voltage discharge between the selective write data SWD and the scan pulse -SWSCN causes an address discharge to occur between the address electrode lines X and the scan / sustain electrode lines Y. Then, the discharge cells corresponding to the logic value "1" of the video data are selected by the address discharge. Only the discharge cells selected in this manner generate wall charges and space charges. Accordingly, the wall voltage level of the selected discharge cells is raised to a sustain voltage level at which sustain discharge can occur when a sustain pulse is supplied. In the sustain period, sustain pulses SUSP are alternately supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. As the sustain pulse SUSP and the wall voltage in the selected discharge cells are added, the selected discharge cells are sustained. In the erasing period of the first subfield WSF1, the positive ramp wave RPS1, the negative pulse -CRP, and the positive ramp RPS2 are applied to the scan / sustain electrode lines Y as in the reset period. Supplied. The full discharge cells are then turned off. The second and third subfields WSF2 to WSF3 are driven by being divided into an optional write address period, a sustain period, and an erase period like the first subfield WSF1 except that the reset period is omitted and only the sustain period is different. The fourth subfield WSF4 is turned on when the fifth subfield ESF5 is turned on according to the gray value because the fifth subfield ESF5 is driven by a selective erasure method. As a result, the erase period of the fourth subfield WSF4 is omitted.

The fifth subfield ESF5, which is the first subfield driven by the selective erasure method, starts with the selective erasure address period. In the selective erase address period, selective erase data SED corresponding to a logic value "0" of the video data is supplied to the address electrode lines X. In synchronization with this selective erasing data SED, negative scan pulses -SESCN having a pulse width of approximately 1 [mu] s are sequentially supplied to the scan / sustain electrode lines Y line by line. The voltage discharge between the selective erase data SED and the scan pulse −SESCN causes an address discharge to occur between the address electrode lines X and the scan / sustain electrode lines Y. Then, the discharge cells corresponding to the logic value "0" of the video data are selected and turned off by the address discharge. Only the selected discharge cells are recombined wall charges and space charges by selective erase address discharge. Accordingly, the wall voltage level of the discharge cells selected by the selective erasure address discharge falls to a voltage level at which sustain discharge cannot occur even when a sustain pulse is supplied. In the sustain period of the fifth subfield ESF5, the sustain pulse SUSP is alternately supplied to the scan / sustain electrode lines Y and the common sustain electrode lines Z. FIG. The sustain pulse is generated by adding the sustain pulse SUSP and the wall voltage in the discharge cells not selected by the address discharge. Like the fifth subfield ESF5, the sixth to tenth subfields ESF6 to ESF10 are turned on only when the previous subfield is turned on, and unnecessary discharge cells are turned off every subfield.

Table 2 below shows the gradation levels expressed in the first to tenth subfields WSF1 to WSF4 and ESF5 to ESF10.

Subfield One 2 3 4 5 6 7 8 9 10 n frames 2 8 16 32 32 32 32 32 32 32 n + 1 frames 4 16 16 32 32 32 32 32 32 32

As can be seen from Table 2, in the present invention, the gradation value of the nth (n is odd or even) frame is different from the gradation value of the n + 1th frame. In the nth frame, the grayscale value increases at a ratio of 2n (n = 1,4,8,16, ..., 16), and in the n + 1th frame, the grayscale value is 2n (n = 2,8,8,16, …, 16 increases. That is, it can be seen that gray levels of the first and second subfields WSF1 and WSF2 of the nth frame and the n + 1th frame are different. In the present invention, the first to fourth subfields WSF1 to WSF4 are binary coded, and the fifth to tenth subfields ESF5 to ESF10 are linearly coded. That is, each of the fifth to tenth subfields ESF5 to ESF10 driven by the selective erasing method must turn on the previous subfield so that unnecessary discharge cells can be turned off whenever the subfields are consecutive. For example, in order for the fifth subfield ESF5 to be turned on, the fourth subfield WSF4 which is the previous subfield must be turned on. After the fourth subfield WSF4 is turned on, the unnecessary discharge cells are turned off in the fifth to tenth subfields ESF5 to ESF10. Accordingly, the fifth subfield ESF5 does not need a separate writing discharge for the selective erase address. In addition, since the sixth to tenth subfields ESF6 to ESF10 may be turned on only when the previous subfield is turned on, discharge cells may be selectively taken out without front lighting. The gray scale representation method of the present invention will be described in detail with reference to FIG. First, in order to express the gray level value of "1", the first subfield WSF1 of the nth frame is turned on and the n + 1th frame is turned off. That is, since the first subfield WSF1 of the nth frame is turned on, the weight of "2" is represented, and since the n + 1th frame is turned off, the weight of "0" is represented. In this case, since the gray scale is integrated and expressed in the human eye, a gray scale of “1”, which is half the sum of the weights of the nth frame and the n + 1 frame, is expressed. At this time, since the fourth subfields WSF4 of the nth and n + 1 frames are not turned on, the fifth to tenth subfields ESF5 to ESF10 driven by the selective erasing method are not turned on. In order to express the gray scale of "16", the third subfield WSF3 of the nth and n + 1 frames is turned on. That is, since the third subfields WSF3 of the nth and n + 1 frames each have a weight of "16", the "16" gray value, which is half the sum of the weight sums of the nth and n + 1 frames, is expressed. At this time, since the fourth subfields WSF4 of the nth and n + 1 frames are not turned on, the fifth to tenth subfields ESF5 to ESF10 driven by the selective erasing method are not turned on. In order to express the gray level of "32", the fourth subfield WSF4 of the nth and n + 1 frames is turned on. That is, since the fourth subfields WSF4 of the nth and n + 1 frames each have a weight of "32", a "32" gray level, which is half the sum of the nth and n + 1 frames, is expressed. At this time, the fifth subfield ESF5 of the nth and n + 1 frames is not turned on. In order to express a gray level of "64", the fourth subfield WSF4 and the fifth subfield ESF5 of the nth and n + 1 frames are turned on. That is, since the fourth subfield WSF4 and the fifth subfield ESF5 of the nth and n + 1 frames each have a weight of "32", the half value of the sum of weights of the nth and n + 1 frames is " A 64 "gradation is represented. At this time, the sixth subfield ESF6 is not turned on. That is, in the present invention, 256 gray levels are expressed by applying different weights to the nth frame and the nth + 1th frame.

If a frame includes the selective write subfields WSF1 to WSF4 and the selective erase subfields EFS5 to ESF10, the address is when the PDP has a VGA resolution, that is, a scanning line of 480 lines. The period requires a total of 8.64 ms. In contrast, the sustain period is required to be 6.43 ms. In other words, the address period is 5.76 ms and 1 ms (pulse width of selective erase scan pulse) calculated as 3 ms (pulse width of selective write scan pulse) x 480 lines x 4 (number of selective write subfields) per frame. 8.64 ms is required, which is the sum of 2.88 ms calculated as x480 lines x 6 (the number of selective erasure subfields). The sustain period is obtained by subtracting an address period of 8.64 ms per frame, one reset period of 0.3 ms, an erase period of 100 ms x 3 (number of subfields) = 0.3 ms, and a 1 ms vertical sync signal (Vsync) margin. 16.67㎳-8.64㎳-0.3㎳-1㎳-0.3㎳) The remaining period is 6.43㎳. Therefore, the PDP driving method according to the present invention not only reduces pseudo contour noise in a video by increasing the number of subfields, but also adds 8 subfields within one frame in the conventional selective writing method. The sustain period is extended from 3.05 Hz to 6.43 Hz when included.

If a frame includes the selective write subfields WSF1 to WSF4 and the selective erase subfields EFS5 to ESF10, the peak white brightness when the full screen is turned on in the display period of 6.43 ms When light of about 640 cd / m 2 corresponding to the light is generated and the screen is turned on by the reset discharge only in one reset period within one frame, 0.7 cd / m 2 corresponding to black is generated. Therefore, since the dark contrast ratio of the PDP driving method according to the present invention is 910: 1, the contrast ratio of the selective writing method including eight subfields in one frame is more than twice as large.

As described above, according to the high-speed driving method of the plasma display panel according to the present invention, one frame is driven by being divided into subfields driven by the selective writing method and subfields driven by the selective erasing method without a front writing period. In addition, the gray value of the n (n is odd or even) frame and the sum of the gray value of the n + 1th frame are set differently, and the sum of the nth frame and the n + 1 frame gray value is divided by 2 to divide the gray level. Will be represented. Accordingly, the high-speed driving method of the plasma display panel according to the present invention can significantly shorten the address period and sufficiently secure the sustain period as compared to the selective write method. Therefore, even if the number of subfields is increased to reduce the video pseudo contour noise, As well as being capable of high speed driving, it is suitable for driving high resolution panels. In the PDP driving method according to the present invention, the period in which the discharge occurs in the non-display period is only one reset period and the display period can be sufficiently secured, resulting in a higher contrast ratio than the selective write method and the selective erase method. Furthermore, the PDP driving method according to the present invention can express 256 gray levels.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

In a driving method of a plasma display panel in which one frame is divided into a plurality of subfields, and the subfields are divided into a reset period, an address period, and a sustain period. Setting a gray value of a plurality of subfields included in the n-th frame (where n is an arbitrary natural number); And setting a gray level value of at least one subfield among the subfields included in the n + 1th frame differently from a gray level value of the subfields included in the n frame. High speed driving method of panel. The method of claim 1, A plurality of selective write subfields in which the frame turns on selected discharge cells in the address period; And a plurality of selective erasing subfields for turning off the selected discharge cells in said address period. The method of claim 2, And the gradation is displayed by the linear coding in which the selective erasure subfields are turned on before the next subfield is turned on. The method of claim 2, Among the selective write subfields, a first subfield includes a reset period for initializing a full screen, an optional write address period for selectively turning on discharge cells, a sustain period for indicating discharge cells turned on in the address period, and a full-screen discharge. Divided by the erasing period of turning off the cells; Among the selective write subfields, the last subfield adjacent to the selective erase subfield is divided into the selective write address period and the sustain period; And among the selective write subfields, subfields between the first and last subfields are divided into the selective write address period, the sustain period, and the erase period. The method of claim 4, wherein Wherein the selective write address period and the erase period are the same in every subfield, while the sustain period is set differently in every subfield. The method of claim 2, And the selective erasing subfields are divided into a selective erasing address period for selectively turning off discharge cells and a sustain period for displaying discharge cells other than the discharge cells turned off in the address period. The method of claim 6, And the sustain period of each of the selective erasing subfields is set to be the same. The method of claim 2, The selective write subfields are composed of four, The selective erasing subfields are composed of six fast driving method of the plasma display panel. The method of claim 8, The optional write subfields are positioned consecutively, And the selective erasing subfields are successively positioned behind the selective writing subfields. The method of claim 8, The gray value of the nth frame is set to 2a (a = 1, 4, 8, 16, 16, 16, 16, 16, 16, 16), The gray value of the n + 1th frame is set to 2a (a = 2, 8, 8, 16, 16, 16, 16, 16, 16, 16). The method of claim 1, And a gray level is expressed using the sum of the nth frame and the n + 1th frame grayscale values.