KR100488456B1 - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can improve display quality.

A method of driving a panel on a plasma display according to the present invention is a method of driving a plasma display panel in which a scan electrode, a sustain electrode, and an address electrode are formed and an image is displayed by dividing one frame period into a plurality of subfields. Applying to erase the charged particles in the cell, initializing the cell using a ramp signal, and selecting an off-cell to be turned off from the cells.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel capable of improving display quality.

Recently, there is a growing interest in flat panel displays that can reduce the weight and volume of cathode ray tubes. Such flat panel displays include liquid crystal displays, plasma display panels (PDPs), field emission displays, and electro-luminescence.

Among such flat panel display devices, the plasma display panel emits phosphors by 147 nm ultraviolet rays generated when the He + Xe, Ne + Xe or He + Ne + Xe gas is discharged, thereby displaying images and videos including characters or graphics. . The plasma display panel is not only thin and large in size, but also recently, due to technology development, the plasma display panel provides greatly improved image quality.

In particular, the three-electrode AC surface discharge type plasma display panel accumulates wall charges using a dielectric layer during discharging, thereby lowering the voltage required for discharging, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering of plasma.

1 is a perspective view showing a discharge cell structure of a three-electrode AC surface discharge type plasma display panel.

Referring to FIG. 1, a discharge cell of a three-pole current alternating surface discharge plasma display panel is formed on a scan electrode (Y) and a sustain electrode (Z) formed on an upper substrate (10), and a lower substrate (18). The address electrode X is provided.

Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed on one side edge of the transparent electrode. 13Z). Indium tin oxide (ITO) is generally used as a material of the transparent electrodes 12Y and 12Z. As the material of the metal bus electrodes 13Y and 13Z, a metal such as chromium (Cr) is usually used. The metal bus electrodes 13Y and 13Z serve to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 on which the scan electrode Y and the sustain electrode Z are formed. In the upper dielectric layer 14, charged particles generated by gas discharge are accumulated as wall charges. The protective layer 16 protects the upper dielectric layer 14 from sputtering of charged particles generated during gas discharge and increases the emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. FIG. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed.

The phosphor layer 26 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is formed to be parallel to the address electrode X to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is emitted by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). An inert mixed gas such as He + Xe, Ne + Xe, or He + Ne + Xe for discharging is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

2 is a frame configuration diagram for driving a conventional plasma display panel.

Referring to FIG. 2, such a three-electrode AC surface discharge type plasma display panel is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for generating discharge uniformly, an address period for selecting a Banggen cell, and a sustain period for implementing gray levels according to the number of discharges. When the image is to be displayed with 265 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0, 1, 2, 3, 4, 5, 6, 7) is increased in proportion. As such, gray scales can be implemented by combining subfields having different sustain periods.

Plasma display panels require high definition, high brightness, high contrast ratio, low contour noise, and the like to realize high quality images. For this purpose, the plasma display panel should reduce the address period which is the non-display period and sufficiently secure the sustain period which is the display period. However, the plasma display panel has a problem in that the address period becomes longer when the number of pixels is increased for high resolution, and the sustain period cannot be secured by the increased address period.

The driving method of the plasma display panel is roughly classified into a selective writing (SW) method and a selective erasing (SE) method according to whether or not the discharge cells are selected by the address discharge.

The conventional selective write (SW) method initializes the full screen in the reset period and selects on cells that are turned on in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge the on cells selected by the address discharge.

In the selective writing (SW) method, the pulse width of the scan pulse supplied to the scan electrode Y should be set to about 3 us or more so that sufficient wall charges are formed in the discharge cell by the address discharge. For this reason, in the selective write (SW) method, since the pulse width required for the address is long, the address period is relatively long, and thus the sustain period is difficult to secure.

On the other hand, in the plasma display panel, contour noise is generated in a moving image due to the characteristic of realizing the gray level of an image by a combination of subfields. When contour noise occurs, the contour appears on the screen, and thus the display quality of the screen is degraded.

In order to solve the problem of poor display quality in the selective writing (SW) method, the number of subfields may be increased by dividing a subfield of one frame. If a subframe is divided into ten or more subfields, the address period becomes longer as the number of subfields increases, making it difficult to secure time for the sustain period. In order to overcome this problem, there is a dual scan method for driving one screen by dividing, but when driving by dividing one screen, there is another problem that the manufacturing cost is increased because the driving drive ICs have to be added as much.

The conventional selective erase (SE) method turns off the discharge cells selected in the address period after turning on the full screen by turning on the full screen in the reset period of all subfields in one frame. Subsequently, in the sustain period, images are displayed by sustaining discharge only discharge cells not selected by the address discharge.

However, the conventional selective erasing (SE) method has a disadvantage in that the contrast ratio is low because the full screen is turned on in the entire writing period, which is a non-display period for each subfield. In the selective erasing (SE) driving method, since the screen is bright as long as the sustain period is sufficiently secured, the contrast ratio is bad, so that the screen is not clear and the image is blurred.

3 is a view showing a drive waveform of a panel on a conventional plasma display of the selective write method.

Referring to FIG. 3, the selective write plasma display panel is driven by a rearrangement period for initializing the full screen, an address period for selecting a cell, a sustain period for maintaining the discharge of the selected cell, and an erase period.

In the reset period, the rising ramp waveform Ramp-Up is applied to all the scan electrodes Y simultaneously. The rising ramp waveform causes a priming discharge to occur between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen. Due to the priming discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

During the set-down period, after the rising ramp waveform is applied to the air, the falling ramp waveform (Ramp-Down) starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform to the ground voltage (GND). Is applied simultaneously. At the same time, a positive sustain voltage Vs is applied to the sustain electrode Z which is a common electrode, and 0 [V] is applied to the address electrode X. When the falling ramp waveform is applied, a setdown discharge is generated between the scan electrode Y and the sustain electrode Z. This set-down discharge eliminates excessive wall charges unnecessary for the address discharge among the wall charges generated during the setup period.

In the address period, a negative scan pulse is sequentially applied to the scan electrodes Y, and a positive data pulse is applied to the address electrodes X in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage due to the wall charge generated during the reset period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

On the other hand, the sustain electrode Z is supplied with a positive DC voltage Vs during the set down period and the address period.

In the sustain period, a sustain pulse is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied.

In the erase period, a ramp waveform Ramp ers having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase the wall charge remaining in the cells turned on by the sustain discharge.

4 is a view illustrating a driving waveform of a conventional selective erasing plasma display panel.

Referring to FIG. 4, a plurality of subfields included in one frame of the plasma display panel are driven by being divided into a reset period, an address period, and a sustain period.

During the reset period, a reset discharge is generated in all the discharge cells in the plasma display panel to turn on the discharge cells. In the address period, the discharge cells that are turned on in the reset period are selectively turned off. In the sustain period, sustain discharge occurs in discharge cells not selected in the address period.

In the reset period, a negative pulse (-Py) and a positive pulse (Py) are supplied to the scan electrode (Y), and a positive pulse (Pz) is supplied to the sustain electrode (Z). ) Is supplied. In addition, the ground potential GND is supplied to the address electrode X in the reset period. Here, the negative pulse -Py is set to the same voltage as the sustain voltage Vs. In addition, the positive pulse Pz is set to a voltage higher than the sustain voltage Vs. Thus, when the negative pulse (-Py) and the positive pulse (+) pulse Pz are supplied to the scan electrode Y and the sustain electrode Z during the reset period, reset discharge occurs in the discharge cells. do. Accordingly, the negative electrode (+) wall charges are formed on the scan electrode (Y) supplied with the negative (−) pulse, and the sustain electrode (supplied with the positive (+) pulse (Pz) is formed. In Z), positive (-) wall charges are formed.

During the address period, scan pulses of approximately 1 us are sequentially supplied to the scan lines Y so as to erase the wall charges of the selected discharge cells. In addition, the data electrodes Dp synchronized with the scan pulses are supplied to the address electrodes X. At this time, in the discharge cells supplied with the data pulse Dp, an address discharge, that is, an erase discharge occurs, and the discharge cells are turned off. Here, the erase scan pulse of negative polarity (-) drops to a scan voltage (-Vy) equal to or less than the ground voltage (GND).

In the sustain period, the sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. When a sustain pulse is supplied to the scan electrodes Y and the sustain electrodes Z, sustain discharge is generated in discharge cells not selected in the address period. In this case, the gray level value corresponding to the luminance weight is expressed by adjusting the number of sustain discharges.

As described above, in the selective erase (SE) method, since the address period is smaller than that of the selective write (SW) method, the display quality can be improved by increasing the number of subfields to reduce the contour noise by increasing the address period or increasing the sustain period to increase luminance.

On the other hand, Japanese Patent Application Laid-Open No. 2001-135238 increases the xenon (Xe) content to 5% or more in the discharge gas enclosed in the PDP, so that the driving voltage is higher than that of the conventional low density Xe panel, but the luminance is high. Disclosed is a plasma display panel which can further increase the. However, the high-density Xe panel has a problem in that the address discharge time is long because the jitter of the address period increases as the content of Xe increases.

As described above, in the conventional plasma display panel driving method, the selective writing (SW) method cannot be driven at high speed because of an long address period.

The selective erase (SE) method has the advantage of being able to operate at high speed because the address period is shorter than the selective write (SW) method, whereas the contrast ratio is bad because the discharge cells of the full screen must be turned on during the non-display period. There are disadvantages.

In addition, due to the high voltage pulse, all cells of the panel have difficulty in forming wall charges under the same conditions, thereby deteriorating the uniformity of the panel. In order to solve this problem, a method of replacing a waveform of a reset period with a ramp waveform has been proposed, but there is a problem in that an extra pulse needs to be applied to form a wall charge suitable for an address.

Therefore, there is a demand for a method of driving a plasma display panel that can improve display quality while driving the plasma display panel at high speed.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel which can improve display quality.

In order to achieve the above object, a driving method of a plasma display panel according to the present invention is a driving method of a plasma display panel in which a scan electrode, a sustain electrode, and an address electrode are formed and display an image by dividing one frame period into a plurality of subfields. The method may include erasing charged particles in a cell by applying an erase pulse, initializing the cell by using a ramp signal, and selecting an off cell to be turned off among the cells.

The method of driving a plasma display panel according to the present invention includes supplying the reset signal to the sustain electrode, supplying a predetermined DC voltage to the scan electrode while the reset signal is supplied to the sustain electrode, And supplying a base voltage to the address electrode while a reset signal is supplied to the sustain electrode.

The DC voltage is characterized in that the positive sustain voltage.

The reset signal includes a ramp waveform of rising slope and a ramp waveform of falling slope.

The ramp waveform of the rising slope is supplied to the sustain electrode after the ramp waveform of the falling slope is supplied.

The absolute value of the voltage of the ramp waveform of the falling slope is greater than the sustain voltage.

The ramp waveform of the falling slope is applied to the sustain electrode and a positive DC voltage is applied to the scan electrode to cause surface discharge between the scan electrode and the sustain electrode and to face the discharge discharge between the sustain electrode and the address electrode. It is characterized by causing.

The surface discharges accumulate negative wall charges on the scan electrodes and the positive wall charges accumulate on the sustain electrodes, and the positive wall charges accumulate on the address electrodes on the address electrodes by the opposite discharges. A negative wall charge is accumulated at a position opposite to the sustain electrode.

After supplying the ramp waveform of the falling slope, the voltage of the sustain electrode is raised to a predetermined voltage, and the ramp waveform of the rising slope is supplied to the sustain electrode to cause a counter discharge between the sustain electrode and the address electrode. It is done.

The polarity of the wall charges on the address electrode formed at the position opposite to the sustain electrode is reversed by the opposite discharge.

The ramp waveform of the rising slope is supplied to the sustain electrode after the wall charge polarity on the address electrode is inverted.

The predetermined voltage value supplied to the sustain electrode has a ground voltage GND or a positive value.

When the ramp waveform of the rising slope is supplied to the sustain electrode, opposite discharge is generated between the address electrodes to form wall charges having the same polarity on the sustain electrode and the address electrode.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a driving method of the plasma display panel according to the present invention will be described in detail with reference to FIGS. 5 to 8.

5 is a frame diagram for driving a selective plasma display panel according to the present invention.

Referring to FIG. 5, the selective erasure (SE) method according to the present invention includes a reset period for initializing the full screen of the panel, an address period for selecting a cell, a sustain period for maintaining the discharge of the selected cell, and remaining in the discharge cell. It is divided into an erasing period for erasing wall charges.

The selective erase (SE) method according to the present invention turns off the selected discharge cells in the address period after the full screen is turned on by turning on the full screen in the reset period of the subfield. Subsequently, in the sustain period, images are displayed by sustaining discharge only discharge cells not selected by the address discharge. In addition, in the last subfield of one frame, erase pulses are applied to the sustain electrode Z to erase wall charges remaining in the discharge cell.

6 is a view showing a driving waveform of the plasma display panel according to the present invention.

7A and 7B are diagrams showing wall charge distribution in the reset period according to the driving waveform of the present invention.

6 and 7, a plurality of subfields included in one frame of the plasma display panel are driven by being divided into a reset period, an address period, a sustain period, and an erase period.

In the reset period, a reset discharge is generated in all the discharge cells in the plasma display panel to turn on the discharge cells.

In the address period, a selective erase pulse is applied to the address electrode X and the scan electrode Y to selectively erase wall charges of the discharge cells turned on in the reset period.

In the sustain period, sustain pulses are alternately applied to sustain electrodes and scan electrodes of discharge cells not selected in the address period.

In the erase period, erase pulses (erase puls) are supplied to the sustain electrode Z to erase wall charges remaining in the discharge cells.

The reset period is divided into a set-down period for supplying ramp-down pulses to the sustain electrode Z and a setup period for supplying ramp-up pulses.

In the set down period and the setup period, the positive electrode pulse having the Voy voltage value is supplied to the scan electrode Y.

In the set down period, the sustain electrode Z is supplied with a negative (-) ramp-down pulse whose voltage value gradually decreases with time. Here, the negative (-) rampdown pulse is set to the negative (-) voltage of the V1z voltage value higher than the absolute value of the sustain voltage (Vs).

Discharges when the positive polarity (+) pulse is supplied to the scan electrode (Y) and the negative (-) rampdown pulse is supplied to the sustain electrode (Z) during the set-down period during which the ramp-down pulse having a voltage value of V1z is supplied. Reset discharge occurs in the cells. Therefore, a negative wall charge is formed on the scan electrode Y to which the positive positive Voy pulse is supplied, and a rampdown pulse of the negative V1z voltage is supplied to the scan electrode Y. The positive electrode wall charges are formed on the sustain electrode Z.

The absolute value of the voltage value of the ramp-down pulse having the V1z voltage value of the negative polarity (-) supplied to the sustain electrode Z is higher than the pulse having the positive polarity (+) Voy voltage supplied to the scan electrode Y. Because of the large voltage, counter discharge occurs between the sustain electrode Z and the address electrode X. When the counter discharge occurs between the scan electrode Y and the address electrode X, as shown in FIG. 7A, the address electrode X has a polarity opposite to that of the wall charges formed on the scan electrode Y and the sustain electrode Z on the upper plate. Branches form wall charges.

When the set-down period in which the ramp-down waveform is supplied is changed from the set-up period in which the ramp-up waveform is supplied, the sustain electrode Z is supplied with a voltage V0z having a base low voltage GND or a positive value. This Voz voltage reduces the intensity of the emission by lowering the slope of the ramp-up pulse during the setup period.

In the setup period, the sustain electrode Z is supplied with a ramp-up pulse of positive polarity, in which the voltage value gradually increases over time. After the ramp-down pulse V1z rises to the positive V0z voltage value, the positive ramp-up pulse of the V2z voltage value of the setup period is supplied to the sustain electrode Z.

The positive (+) ramp-up pulse of the V2z voltage value during the setup period is set to an absolute voltage higher than the sustain voltage Vs. As described above, when a positive polarity (+) pulse is supplied to the scan electrode (Y) and the sustain electrode (Z) and a ground voltage (GND) is supplied to the address electrode (X) during the setup period in which the ramp-up pulse is supplied, the sustain electrode ( A counter discharge occurs between Z) and the address electrode X. When the ramp-up pulse, in which the voltage value gradually increases, is supplied to the sustain electrode Z, the intensity of light emission is reduced.

The amount of wall charge can be easily adjusted by changing the voltage values V0z, V1z, and V2z applied to the sustain electrode Z.

When a counter discharge occurs between the sustain electrode Z and the address electrode X, the wall charge on the address electrode X under the sustain electrode Z is negative and the wall charge of the negative polarity is positive as shown in FIG. 7B. A micro discharge is generated in which the wall charge of the positive polarity (+) on the sustain electrode (Z) is slightly reduced and the wall charge is changed to the positive wall charge.

Reset discharge occurs in the discharge cells. Therefore, a negative wall charge is formed on the scan electrode Y supplied with the positive (+) Voy pulse, and a positive wall charge is formed on the sustain electrode (Z) supplied with the ramp-up pulse of the positive (+). Polar wall charges are formed.

In the address period, a negative scan pulse is sequentially applied to the scan electrodes Y, and a positive data pulse is applied to the address electrodes X in synchronization with the scan pulse. In the cells that are not selected by the address discharge in the address period, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed.

In the sustain period, a sustain pulse is applied to the scan electrodes Y and the sustain electrodes Z alternately. In a cell not selected by the address discharge during the address period, a sustain discharge, that is, a display discharge, is generated between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied while the wall voltage and the sustain pulse in the cell are added. Get up.

In the erasing period, a ramp waveform having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase wall charges remaining in the cells turned on by the sustain discharge.

8 is a graph illustrating a discharge current in an address period of a plasma display panel according to the present invention.

Referring to FIG. 8, when the driving waveform of the plasma display panel according to the present invention is applied, the address time of the on and off cells is substantially reduced by accumulating uniform wall charges in the discharge cells during the reset period. It becomes constant and shortens an address time.

In the driving method of the plasma display panel according to the present invention, the erase pulse is applied to the erase period to initialize the cell, and then the ramp up pulse is continuously supplied to the sustain electrode in the reset period. The ramp-down pulse is supplied to generate a discharge between the scan electrode and the sustain electrode, and then the ramp-up pulse is supplied to cause the counter discharge to occur between the sustain electrode and the address electrode. When opposite discharge is generated between the sustain electrode and the address electrode, positive wall charges are formed on the address electrode as a whole.

As described above, the driving method of the plasma display panel according to the present invention improves the contrast ratio by reducing the intensity of light emitted during the reset period by supplying the ramp down pulse and the ramp up pulse to the sustain electrode during the reset period.

In the method of driving a panel to a plasma display according to the present invention, a lamp-down pulse is supplied during a reset period, and then a ramp-up pulse is continuously supplied to accumulate uniform wall charges in a discharge cell. The address time of (Off cell) becomes substantially constant, and the address time is shortened. In addition, the driving method of the plasma display panel according to the present invention shortens the address time to increase the content of Xe gas, thereby improving driving efficiency of the plasma display panel, thereby improving luminance.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a three-electrode AC surface discharge type plasma display panel.

2 is a frame configuration diagram for driving a conventional plasma display panel.

3 is a view illustrating a driving waveform of a conventional plasma display panel of a selective writing method.

4 is a view illustrating a driving waveform of a conventional selective erasing plasma display panel.

5 is a frame configuration diagram for driving the plasma display panel of the selective erasing method according to the present invention.

6 is a view showing a driving waveform of the selective erasing plasma display panel according to the present invention.

7A and 7B are diagrams showing wall charge distribution in the reset period according to the driving waveform of the present invention.

8 is a graph illustrating a discharge current in an address period of a plasma display panel according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: upper substrate 18: lower substrate

Y: scan electrode Z: sustain electrode

X: address electrode 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14: upper dielectric layer

16: protective film 22: lower dielectric layer

24: partition 26: phosphor layer

Claims (13)

A scan electrode, a sustain electrode, and an address electrode are formed and time-division-driven one frame period into a plurality of subfields, wherein at least one subfield is a reset step of initializing a cell and selecting an off cell to be turned off from among the cells. A driving method of a plasma display panel comprising an address step and an erase step of erasing charged particles in the cell. The reset step The sustain electrode is supplied with a ramp waveform that gradually decreases from a base voltage to a negative voltage whose absolute value is greater than the sustain voltage, and is greater than the sustain voltage at any one of the base voltage and the positive voltage following the falling ramp waveform. Supplying a ramp waveform that gradually rises to a positive voltage; Applying a positive voltage to the scan electrode; And applying a ground voltage to the address electrode. delete delete delete delete delete The method of claim 2, The ramp waveform of the falling slope is applied to the sustain electrode and a positive DC voltage is applied to the scan electrode to cause surface discharge between the scan electrode and the sustain electrode and to face the discharge discharge between the sustain electrode and the address electrode. Method of driving a plasma display panel, characterized in that. The method of claim 7, wherein The wall discharges accumulate negative wall charges on the scan electrodes and the positive wall charges accumulate on the sustain electrodes. And the positive wall charges accumulate on the address electrode at positions opposite to the scan electrodes and the negative wall charges at the positions opposite to the sustain electrodes on the address electrodes. The method of claim 7, wherein After supplying the ramp waveform of the falling slope, the voltage of the sustain electrode is raised to a predetermined voltage, and the ramp waveform of the rising slope is supplied to the sustain electrode to cause a counter discharge between the sustain electrode and the address electrode. A drive method of a plasma display panel. The method of claim 9, And inverting the polarity of the wall charges on the address electrodes formed at the positions opposite to the sustain electrodes by the opposite discharges. The method of claim 9, And a ramp waveform of the rising slope is supplied to the sustain electrode after the wall charge polarity on the address electrode is inverted. delete The method of claim 11, When the ramp waveform of the rising slope is supplied to the sustain electrode, opposite discharge is generated between the address electrodes to form wall charges having the same polarity on the sustain electrode and the address electrode. Way.