KR100525733B1 - Method and Apparatus for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to reduce an address period and stabilize a discharge.

The method and apparatus for driving the plasma display panel select a cell by supplying a scan voltage to the scan electrode and a data voltage to the address electrode during the address period, and supply a DC bias voltage to the sustain electrode, and between the address period and the sustain period. The voltage of the scan electrode is lowered and the voltage on the sustain electrode is maintained at the DC bias voltage. During the sustain period, sustain pulses are alternately supplied to the scan electrode and the sustain electrode.

Description

Method and apparatus for driving plasma display panel {Method and Apparatus for Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to reduce an address period and stabilize discharge.

Plasma Display Panels (hereinafter referred to as "PDPs") display an image including characters or graphics by emitting phosphors by ultraviolet rays of 147 nm generated upon discharge of He + Xe or Ne + Xe gas. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. 20X).

Each of the scan electrode 30Y and the sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y, which are formed at one edge of the transparent electrode, respectively. 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 on which the scan electrode 30Y and the sustain electrode 30Z are formed. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 protects the upper dielectric layer 14 from sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The address electrode 20X is formed in the direction crossing the scan electrode 30Y and the sustain electrode 30Z. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed. The phosphor layer 26 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is formed to be parallel to the address electrode 20X to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited and emitted by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. When the image is to be displayed in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ in each subfield (where n = 0,1,2,3,4,5,6, 7) is increased in proportion. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of a PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge.

The selective write method turns off all cells during the reset period and selects on-cells that should be turned on during the address period. The selective writing method displays an image by maintaining the discharge of the on cells selected by the address discharge during the sustain period.

The selective erase method turns on all cells during the reset period and selects off-cells that should be turned off during the address period. The selective erasing method displays an image by maintaining the discharges of the on cells except the off cells selected by the address discharge during the sustain period.

The selective write method generally has a wider range of gradation expressions than the selective erase method, but has a disadvantage of longer address period than the selective erase method. On the other hand, the selective erasing method is advantageous for high-speed driving, but all the cells are turned on during the reset period, which is the non-display period.

Patent Application No. 10-2000-0012669, Patent Application No. 10-2000-0053214, the so-called 'SWSE method' having advantages that are superior to the advantages of each of the selective writing method and the selective erasing method, Patent Application No. 10-2001-0003003, Patent Application No. 10-2001-0006492, Patent Application No. 10-2002-0082512, Patent Application No. 10-2002-0082513, Patent Application No. 10-2002-0082576, etc. Proposed through. The drive signal of the SWSE method is shown in FIG. 3.

Referring to FIG. 3, the SWSE method divides one frame period into a plurality of selective write subfields SW and a plurality of selective erase subfields SE to drive the PDP.

In the reset period of the selective write subfield SW, all of the scan electrodes Y are supplied with a ramp waveform Ruy of a rising slope at which the voltage rises up to the setup voltage Vsetup. At the same time, 0 V or the ground voltage GND is supplied to the sustain electrodes Z and the address electrodes X. The write dark discharge (Dark discharge) between the scan electrodes (Y) and the address electrodes (X) and between the scan electrodes (Y) and the sustain electrodes (Z) in the cells of the full screen by the rising ramp waveform (Ruy) ) Takes place. The write dark discharge causes positive wall charges to be accumulated on the address electrodes X and the sustain electrodes Z, and negative wall charges to be accumulated on the scan electrodes Y. . After the write dark discharge has occurred, the scan electrode Y is supplied with the falling ramp waveform Rdy of the falling slope from which the voltage is lowered from the sustain voltage Vs to the approximately negative voltage, and at the same time, the sustain voltage Z is sustained. DC bias voltage DCz of (Vs) is supplied. Due to the voltage difference between the falling ramp waveform Rdy and the DC bias voltage DCz, an erase arm is formed between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes Z. Discharge occurs. This erasure dark discharge erases the excess wall charges that do not contribute to the address discharge among the wall charges generated by the rising ramp waveform Rdy, so that the wall charge remains uniformly in the cells of the entire screen.

In the address period of the selective write subfield SW, write scan pulses scw are sequentially supplied to the scan electrodes Y, and at the same time, write data pulses dw synchronized with the write scan pulses scw are applied to the address electrodes. Supplied to X). The DC bias voltage DCz is continuously supplied to the sustain electrodes Z. As the voltage difference between the write scan pulse scw and the write data pulse dw and the wall voltage initialized during the reset period are added, a write discharge occurs in the on cells to which the write data pulse dw is supplied. The write discharge accumulates positive wall charges on the scan electrodes Y, and inverts the polarities of the wall charges to positive polarities, and negative wall charges are accumulated on the sustain electrodes Z and the address electrodes X. FIG.

During the sustain period of the selective write subfield SW, the sustain pulse sus of the sustain voltage Vs is alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. Each time the sustain pulse is supplied, sustain discharge occurs in the on cells selected in the write address period.

After the last sustain discharge, an erase ramp waveform ers gradually supplied to the sustain voltage Vs is supplied. The erase ramp waveform ers erases the discharge in the on-cell and erases the wall charges generated by the sustain discharge.

In the address period of the selective erasing subfield SE, an erase scan pulse sce is sequentially supplied to the scan electrodes Y, and an erase data pulse de synchronized with the erase scan pulse sce is generated. Supplied to X). During this address period, 0 V or the ground voltage GND is supplied to the sustain electrodes Z. As the voltage difference between the scan pulse sce and the erase data de and the wall voltage in the cells are added, an erase discharge is generated in the off-cells to which the erase data pulse SED is supplied. By this erase discharge, the wall charges in the off cells are erased to such an extent that a discharge does not occur even when a sustain voltage is supplied.

In the sustain period of the selective erasing subfield SE, the sustain pulse sus of the sustain voltage Vs is alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. Each time such a sustain pulse is supplied, sustain discharge occurs in the on-cells not selected in the erase address period.

The biggest difference between the selective write subfields SW and the selective erase subfields SE of the SWSE method is in the address discharge characteristic. In the selective write subfields SW, a strong discharge is necessary because the polarity of the wall charges on the scan electrodes Y and the sustain electrodes Z must be reversed or inverted by the address discharge in the on-cells to cause the sustain discharge. For this reason, since the address discharge time for causing the write address discharge is relatively long, the address period is long. On the other hand, in the selective erasure subfields SE, the wall charge amount is reduced rather than reversing the polarity of the wall charges on the scan electrodes Y and the sustain electrodes Z. FIG. For this reason, since the address discharge time for causing the erase address discharge is shorter than the write address discharge, the address period can be relatively short.

However, the driving method of the PDP has a problem that the address period is long due to the address discharge delay and the discharge becomes unstable at low gradation. If the address period becomes longer, the sustain period is relatively reduced within the limited frame period, so that more subfields are added within one frame period in order to reduce luminance and reduce image quality deterioration factors such as video pseudo contour noise. it's difficult. The discharge instability at low gradation will be described in detail as follows. In general, the number of sustain pulses does not coincide with the number of discharges. This is because when the sustain pulse is generated initially, the discharge becomes unstable, and after that, when the sustain pulse is generated, the discharge gradually stabilizes, thereby increasing the luminance. In other words, discharge may not occur when a sustain pulse occurs initially. Therefore, in low gradation, since the number of continuous sustain pulses is small, it is difficult to occur in a stable state of discharge.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP that reduces address periods and stabilizes discharge.

The present invention provides a method of driving a plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes and time-dividing one frame period into a reset period, an address period and a sustain period. A first step of supplying a scan voltage to the scan electrode and a data voltage to the address electrode to select a cell and supplying a DC bias voltage to the sustain electrode during the address period; A second step of lowering the voltage of the scan electrode to a base voltage and maintaining the voltage on the sustain electrode as the DC bias voltage until a time point t0 when the first sustain pulse is applied after the address period elapses; And a third step of causing sustain discharge by alternately supplying sustain pulses to the scan electrode and the sustain electrode during the sustain period. In the third step, the first sustain pulse supplied to the scan electrode from the time point t0 is generated. The DC bias voltage supplied to the time point t1 and t2 is maintained, and the DC bias voltage supplied to the time point t1 is lowered from the time point t1 to the electromotive voltage, so that the base voltage is maintained until the time point t2. An apparatus for driving a plasma display panel having an electrode, a plurality of sustain electrodes and a plurality of address electrodes, and time-dividing one frame period into a reset period, an address period and a sustain period, wherein a scan voltage is supplied to the scan electrode during the address period. Supplying a data voltage to the address electrode Select the cell, and a first driver for supplying a direct current bias voltage to the sustain electrode; A second driver configured to lower the voltage of the scan electrode to a base voltage and maintain the voltage on the sustain electrode as the DC bias voltage until a time point t0 when the first sustain pulse is applied after the address period elapses; And a third driving unit configured to alternately supply sustain pulses to the scan electrode and the sustain electrode during the sustain period to cause sustain discharge, wherein the driving unit starts the first sustain pulse supplied to the scan electrode from time t0 to time t1. And the DC bias voltage supplied until the time t2 and lowering the DC bias voltage supplied from the time t1 to the electromotive voltage from the time t1 to maintain the base voltage until the time t2. Advantages will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 8.

Referring to FIG. 5, a method of driving a PDP according to an embodiment of the present invention includes a selective write subfield WSF including first and second subfields SF1 and SF2 of low gradation and a first frame period. The PDP is driven by time division into selective erasure subfields ESF including the third through twelfth subfields SF3 through SF12.

The first subfield SF1 includes a reset period for uniformly forming a predetermined amount of wall charges in the cells of the full screen, a write address period for selecting on-cells using a write discharge, and a selected on cell. A sustain period for causing sustain discharge and an erase period for erasing wall charge remaining in the cell by the sustain discharge. The second subfield SF2, which is the last subfield of the selective write subfield WSF, includes the reset period, the write address period, and the sustain period except the erase period.

Each of the third to eleventh subfields SF3 to SF11 includes an erase address period for selecting off-cells as an erase discharge and a sustain period for causing sustain discharge for the oncells. The twelfth subfield SF12, which is the last subfield of the selective erasing subfield ESF, includes the erasing address period and the sustain period, and further includes an erasing period at the last stage.

The luminance weights assigned to the respective subfields SF1 to SF12 are given as follows. The luminance weight of the first subfield SF1 is 2 ⁰ (1), the luminance weight of the second subfield SF2 is 2 ¹ (2), and the luminance weight SF3 of the third subfield is 2 ² (4). The luminance weights of the fourth subfield SF4 are 2 ³ (8), and the luminance weights of the fifth subfield SF5 are 2 ⁴ (16), respectively. The luminance weights of the sixth to twelfth subfields SF6 to SF12 are equally given to 2 ⁵ (32), respectively.

The first and second subfields SF1 and SF2, which are the selective write subfields WSF, express grayscales with binary coding that does not depend on the previous cell state. In contrast, the third to twelfth subfields SF3 to SF12 which are the selective erasing subfield ESF represent grayscales by linear coding for selecting offcells among oncells turned on in the previous subfield.

Only the first and second subfields SF1 and SF2 having the low luminance weight are set to the selective write subfield SF1 and the other subfields SF3 to SF12 are the selective erase subfields SF3 to SF12. Is set to).

In the method and apparatus for driving a PDP according to the present invention, among the subfills disposed within one frame period, the number of the selective write subfields WSF having a relatively long address period has the first and second subfields SF1 and SF2. Since the two small subfields, i.e., are selective erase subfields (ESF) having a relatively short address period, the address period can be reduced compared to the conventional selective write method or the SWSE method. If the address period is reduced in this way, the sustain period or additional subfields can be allocated as much as that time.

However, since the selective write subfields WSF are composed of low gradation subfields having low luminance weight, sustain discharge is unstable and there is a disadvantage in that the discharge of the subsequent selective write subfields WSF may be unstable. In other words, assuming that the luminance weight and the sustain pulse coincide with each other, there are two sustain pulses in the second subfield SF2, which is the last subfield of the selective write subfields SWF, so that the sustain discharge is stabilized. Difficult and subsequent address discharge of the selective erase subfield may become unstable. On the other hand, in the SWSE method, a luminance weight is given to 2 ⁵ (32) in the last subfield of the selective write subfield, and thus the number of sustain pulses is 32, so that the sustain discharge can be stably generated.

The method and apparatus for driving a PDP according to the present invention stabilizes the discharge by supplying a driving waveform as shown in FIG. 5 to the PDP in each of the selective write subfields WSF with low luminance weights.

Referring to FIG. 5, in the reset period of the selective write subfield WSF, the ramp waveform Ruy of the rising slope at which the voltage rises up to the setup voltage Vsetup is simultaneously supplied to all the scan electrodes Y. At the same time, 0 V or the ground voltage GND is supplied to the sustain electrodes Z and the address electrodes X. A write dark discharge occurs between the scan electrodes Y and the address electrodes X and between the scan electrodes Y and the sustain electrodes Z in the cells of the full screen by the rising ramp waveform Ru. The write dark discharge causes positive wall charges to be accumulated on the address electrodes X and the sustain electrodes Z, and negative wall charges to be accumulated on the scan electrodes Y. . After the write dark discharge has occurred, the scan electrodes Y have a falling ramp waveform having a falling slope in which the voltage starts to decrease from the sustain voltage Vs to the base voltage GND or 0 V or the negative voltage (-Vr). At the same time as Rdy is supplied, the DC bias voltage DCz of the sustain voltage Vs is supplied to the sustain electrodes Z. Due to the voltage difference between the falling ramp waveform Rdy and the DC bias voltage DCz, an erase arm is formed between the scan electrodes Y and the sustain electrodes Z and between the scan electrodes Y and the address electrodes Z. Discharge occurs.

This erasure dark discharge erases the excess wall charges that do not contribute to the address discharge among the wall charges generated by the rising ramp waveform Rdy, so that the wall charge remains uniformly in the cells of the entire screen.

In the address period of the selective write subfield WSF, the write scan pulse scw of the negative scan voltage (-Vy) is sequentially supplied to the scan electrodes Y, and the positive polarity is synchronized with the write scan pulse scw. The write data pulse dw of the data voltage Vd is supplied to the address electrodes X. In addition, the DC bias voltage DCz of the positive sustain voltage Vs is continuously supplied to the sustain electrodes Z. As the voltage difference between the write scan pulse scw and the write data pulse dw and the wall voltage initialized during the reset period are added, a write discharge occurs in the on cells to which the write data pulse dw is supplied. The write discharge causes positive wall charges to accumulate on the scan electrodes Y, and the polarities of the wall charges are reversed to positive polarities, and negative wall charges accumulate on the sustain electrodes Z and the address electrodes X. do.

At the beginning of the sustain period from the end of the address period to the time t0, the ground voltage GND or 0V is supplied to the scan electrodes Y and the address electrodes Z. During this period, the DC bias voltage DCz of the sustain voltage Vs is continuously supplied to the sustain electrodes Z.

In the sustain period, the first sustain pulse sus1 is supplied to the scan electrodes Y and the base voltage GND or 0V is supplied to the scan electrodes Y during the period from time t0 to time t2. The DC bias voltage DCz of the sustain voltage Vs is continuously supplied to the sustain electrodes Y during a period from time t0 to time t1 corresponding to approximately an initial 1/2 period of the first sustain pulse sus1. That is, the positive sustain voltage Vs is simultaneously supplied to the scan electrodes Y and the sustain electrodes Z during the period from time t0 to time t1. Subsequently, the ground voltage GND or 0V is supplied to the sustain electrodes Y during the period from the time t1 to the time t2 corresponding to approximately the second half period of the first sustain pulse sus1. During the period from the time point t1 to the time point t2, the first sustain discharge occurs between the scan electrodes Y and the sustain electrodes Z as the wall voltage and the sustain pulse voltage are added in the cell.

The first sustain pulse sus1 is supplied to the scan electrodes Y during the period from time t0 to time t1, but no discharge occurs because no voltage difference is generated between the scan electrodes Y and the sustain electrodes Z. . The period from time t0 to time t1 maintains the voltage on the sustain electrodes Z at the positive sustain voltage Vs as shown in FIG. 6B so that the negative wall charges on the sustain electrodes Z may be decayed. It prevents the loss. This will be described in detail with reference to FIGS. 6A and 6B. In the conventional selective write subfield SW as shown in FIG. 3, the base voltage GND or 0 V is simultaneously supplied to the scan electrodes Y and the sustain electrodes Z when the address period ends, that is, when the address discharge ends. . At this time, as the positive voltage applied to the sustain electrodes Z is lowered to the base voltage GND or 0 V, the suction electrostatic force between the sustain electrodes Z and the negative wall charges is lowered. Some of the negative wall charges on) may fall off as shown in FIG. 6A. Then, when the first sustain pulse is supplied to the scan electrodes Y, the sustain discharge may not occur because the voltage difference between the scan electrodes Y and the sustain electrodes Z is not large enough. In contrast, according to the driving method and apparatus of the PDP according to the embodiment of the present invention, when the address period ends, only the voltage of the scan electrodes Y is lowered to the ground voltage GND or 0V, and the sustain electrodes Y The voltage maintains the positive sustain voltage (Vs). The suction electrostatic force between the sustain electrodes Z and the negative wall charges is maintained high by the positive sustain voltage Vs applied to the sustain electrodes Z from the time point t0 to the time period t1. Negative wall charges on the fields Z are not lost. Therefore, the sustain discharge is stable because the voltage difference between the scan electrodes Y and the sustain electrodes Z becomes large enough during the period from the time t1 to the time t2 when the first sustain pulse is supplied to the scan electrodes Y. It happens very soon.

After the time t2 of the sustain period, the sustain pulses sus3 and sus3 having a normal pulse width are alternately supplied to the sustain electrodes Y and the scan electrodes Z alternately. The base voltage GND or 0V is continuously supplied to the address electrodes X. Each time the sustain pulse is supplied, sustain discharge occurs in the on cells selected in the write address period.

After the last sustain discharge, an erase ramp waveform ers gradually supplied to the sustain voltage Vs is supplied. The erase ramp waveform ers erases the discharge in the on-cell and erases the wall charges generated by the sustain discharge.

The driving waveform is not limited to the selective write subfield of the SWSE method but may be applied to the selective write method in which one frame period is time-divided by only the selective write subfields.

The drive waveform of the selective erase subfield (ESF) is substantially the same as that shown in FIG.

7 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 7, a driving device of a PDP according to an embodiment of the present invention includes a data processor including a gamma & gain adjusting unit 31, an error diffusion & dither processing unit 32, and a subfield mapping unit 33, and a PDP ( A data driver 34 for supplying data to the address electrodes X of the 39, a scan driver 35 for driving the scan electrodes Y of the PDP, and a sustain electrode Z of the PDP 39; ), A timing controller 37 for controlling the driving circuits by generating a timing control signal required for each driving circuit, and a driving voltage for generating a driving voltage required for the PDP 39. The generating part 38 is provided.

The gamma & gain adjusting unit 31 performs a gamma correction on the digital video data RGB from the input line and also corrects the gain.

The error diffusion & dither processing unit 32 diffuses the quantization error component of the digital video data RGB input from the gamma & gain adjustment unit 31 to adjacent pixel data using a Floyd-Steinberg error diffusion filter. Relax In addition, the error diffusion and dither processor 32 may dither the input data by thresholding the input data with a dither mask (or dither matrix) having a threshold set corresponding to each of the pixels. The error diffusion & dither processing section 32 expresses the gray scale of the halftone to enlarge the gray scale range that can be represented by the subfield pattern.

The subfield mapping unit 33 maps the data input from the error diffusion & dither processing unit 32 to the subfield pattern shown in FIG. 4.

The data driver 34 supplies the data input from the subfield mapping unit 33 to the address electrodes X under the control of the timing controller 37.

The scan driver 35 applies the rising ramp waveform Ruy and the falling ramp waveform Rdy to the scan electrodes Y during the reset period of the selective write subfield WSF under the control of the timing controller 37. It supplies continuously and write scan pulses scw are sequentially supplied to the scan electrodes Y during the address period of the selective write subfield WSF. During the sustain period of the selective write subfield WSF, the scan driver 35 continuously supplies the sustain pulses sus1 and sus3 as shown in FIG. 5 to the scan electrodes Y. During the erasing address period of the selective erasing subfield ESP, the scan driver 35 sequentially supplies the erasing scan pulse sce as shown in FIG. 3 to the scan electrodes Y under the control of the timing controller 37. The sustain pulse sus shown in FIG. 3 is continuously supplied during the sustain period of the erase subfield ESP.

The sustain driver 36 sustains the DC bias voltage DCz from the time of the falling ramp waveform Rdy of the reset period of the selective write subfield WSF to the time t1 under the control of the timing controller 37. The sustain pulse sus2 and the erase ramp waveform ers are continuously supplied to the sustain electrodes Z from the time t2 to the end of the sustain period. The sustain driver 36 supplies the base voltage GND or 0V to the sustain electrodes Z during the erase address period of the selective erase subfield ESF as shown in FIG. 3 under the control of the timing controller 37. The sustain pulse su is supplied to the sustain electrodes Z during the sustain period of the subfield ESF.

The timing controller 37 receives the vertical / horizontal synchronization signals V and H and the clock signal Clk and generates the timing control signals Cx, Cy, and Cz necessary for each of the driving units 34, 35, and 36. Each of the driving units 34, 35, 36 is controlled by supplying the timing control signals Cx, Cy, Cz to the corresponding driving units 34, 35, 36. The data control signal Cx includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal Cy includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 35. The sustain control signal Cz includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 36.

The driving voltage generator 38 includes the voltage Vsetup of the rising ramp waveform Ruy, the voltage Vsetdn of the falling ramp waveform Rdy, the scan voltage (-Vy), the sustain voltage (Vs), and the data voltage (Vd). Etc. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

As described above, the method and apparatus for driving a PDP according to the present invention allocate an SWSE-type selective write subfield to a low gradation subfield and assign other subfields as selective erasure subfields having a short address period. After the address period of the selective write subfield is finished, the voltage on the scan electrode is lowered, while the voltage on the sustain electrode is maintained at the positive voltage, and the first sustain pulse is being supplied to the scan electrodes (Y). By allowing the voltage difference between the scan electrodes Y and the sustain electrodes Z to become sufficiently large for a period from the time t1 to the time t2, the sustain discharge and the discharge of the selective erasure subfield subsequent to it can be stabilized.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing a subfield pattern of a frame period in the conventional method of driving a plasma display panel.

3 is a waveform diagram showing a driving waveform applied to a conventional SWSE method.

4 is a diagram illustrating a subfield pattern according to an embodiment of the present invention.

5 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 6A is a cross-sectional view illustrating wall charge distribution before and after address discharge when a driving waveform of the related art as shown in FIG. 3 is supplied to a plasma display panel.

6B is a cross-sectional view showing wall charge distribution before and after address discharge when the driving waveform of the present invention as shown in FIG. 5 is supplied to the plasma display panel.

7 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

31: Gamma & Gain Adjuster 32: Error Diffusion & Dither Processing

33: subfield mapping unit 34: data driver

35 scan driver 36 sustain driver

37: timing controller 38: drive voltage generator

Claims (8)

delete A method of driving a plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, and time-dividing one frame period into a reset period, an address period and a sustain period, A first step of supplying a scan voltage to the scan electrode and a data voltage to the address electrode to select a cell and supplying a DC bias voltage to the sustain electrode during the address period; A second step of lowering the voltage of the scan electrode to a base voltage and maintaining the voltage on the sustain electrode as the DC bias voltage until a time point t0 when the first sustain pulse is applied after the address period elapses; A third step of causing sustain discharge by alternately supplying sustain pulses to the scan electrode and the sustain electrode during the sustain period; In the third step, the first sustain pulse supplied to the scan electrode from the time t0 is maintained until the time t1 and t2, and the DC bias voltage supplied to the time t1 is lowered to the electromotive voltage from the time t1. And maintaining a low voltage until the time t2. The method of claim 2, The third step, Supplying a first sustain pulse to the scan electrode from the time t0 when the voltage of the scan electrode is lowered to the base voltage until the time t2 after a predetermined time; And supplying the sustain pulses alternately to the sustain electrode and the scan electrode from the time point t2 onwards. The method of claim 3, wherein The second step, And the voltage of the sustain electrode is maintained at the DC bias voltage from the time t0 to the time t1 between the time t2. delete An apparatus for driving a plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes and a plurality of address electrodes, and time-dividing one frame period into a reset period, an address period and a sustain period, A first driver supplying a scan voltage to the scan electrode and a data voltage to the address electrode to select a cell and supplying a DC bias voltage to the sustain electrode during the address period; A second driver configured to lower the voltage of the scan electrode to a base voltage and maintain the voltage on the sustain electrode as the DC bias voltage until a time point t0 when the first sustain pulse is applied after the address period elapses; A third driving unit configured to alternately supply sustain pulses to the scan electrodes and the sustain electrodes during the sustain period to cause sustain discharge; The driving unit maintains the first sustain pulse supplied to the scan electrode from the time t0 to the time t1 and the time t2, and lowers the DC bias voltage supplied from the time t1 to the electromotive voltage from the time t1 to the base voltage. The plasma display panel is driven until the time t2. The method of claim 6, The third drive unit, The first sustain pulse is supplied to the scan electrode from the time t0 when the voltage of the scan electrode is lowered to the base voltage until the time t2 after a predetermined time, And the sustain pulse is alternately supplied to the sustain electrode and the scan electrode after the point in time t2. The method of claim 7, wherein The second drive unit, And driving the voltage of the sustain electrode to the DC bias voltage from the time t0 to the time t1 between the time t2.