KR100710284B1 - Method And Aparatus for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving method and a driving apparatus of a plasma display panel.

A driving method of a plasma display panel according to an exemplary embodiment of the present invention includes a scan electrode and a sustain electrode to which a sustain voltage is alternately applied, a reset period for initializing a cell, an address period for selecting a cell, and a selected cell. A method of driving a plasma display panel that is time-divided into a sustain period for sustain discharge and a stabilization period for stabilizing a wall voltage of a selected cell, the method comprising: applying a first stabilization lamp voltage to the scan electrode during the stabilization period; And floating the sustain electrode in a part of the period during which the first stabilization lamp voltage is applied.

Description

Method and driving device for plasma display panel {Method And Aparatus for Driving Plasma Display Panel}             

1 is a perspective view showing a discharge cell of a conventional three-electrode AC surface discharge plasma display panel.

FIG. 2 is a cross-sectional view of the plasma display panel shown in FIG. 1.

3 is a diagram illustrating a frame structure of an 8-bit default code for implementing 256 gray levels.

4 is a driving waveform diagram of the plasma display panel shown in FIG. 1.

5A and 5B illustrate a form of wall charges accumulated in the upper dielectric layer by the waveform of FIG. 4.

6 illustrates a driving waveform for driving a plasma display panel according to a first embodiment of the present invention.

FIG. 7 is a view illustrating some modifications of a driving waveform for driving the plasma display panel according to the first embodiment of the present invention.

8 is a schematic diagram of driving waveforms of the plasma display panel according to the second and third exemplary embodiments of the present invention.

9 is a view showing in detail the sustain period and the next reset period of the driving waveforms of the plasma display panel according to the second embodiment of the present invention.

FIG. 10 is a view illustrating a driving waveform for driving the modified plasma display panel of FIG. 9.

FIG. 11 is a diagram illustrating in detail a sustain period and a next reset period among driving waveforms of a plasma display panel according to a third exemplary embodiment of the present invention.

FIG. 12 illustrates a driving waveform for driving the modified plasma display panel of FIG. 11.

FIG. 13 is a view schematically illustrating a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

Y: scan electrode Z: sustain electrode

55: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a driving apparatus for a plasma display panel, and more particularly, to a method and a driving apparatus for a plasma display panel capable of further stabilizing wall voltage control by applying a stable waveform.

Plasma Display Panels (hereinafter referred to as "PDPs") display images by emitting phosphors by ultraviolet rays generated during discharge of He + Xe, Ne + Xe, He + Ne + Xe gases. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

1 is a perspective view illustrating a discharge cell structure typically arranged in an alternating-type PDP in a matrix form, and FIG. 2 is a cross-sectional view of the discharge cell shown in FIG. 1.

1 and 2, the discharge cells of the three-electrode AC surface discharge type PDP are formed on the scan electrode Y and the sustain electrode Z formed on the upper substrate 10, and the lower substrate 18. The address electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrode 13Y is formed at one edge region of the transparent electrode. , 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and He + Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to the related art.

Referring to FIG. 4, the first subfield SF1 included in one frame of the PDP is divided into a reset period RPD, an address period APD, and a sustain period SPD.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage during set down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, a positive DC voltage is supplied to the sustain electrode Z when the reset pulse RP is set down. Since the reset pulse RP is supplied in a gradually decreasing form with respect to the positive DC voltage, the scan electrode Y becomes a negative polarity relative to the sustain electrode Z at the time of set down, that is, the polarity is reduced. This inversion reduces the wall charges generated during set-up.

In the address period APD, the scan pulse SP having the negative scan voltage Vy is supplied to the scan electrode Y and the data pulse DP is supplied to the address electrode X. Discharge will occur. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In the sustain period SPD, the triggering pulse TP is supplied to the scan electrode Y at the start so that the sustain discharge is started in the discharge cells in which the wall charge is sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y to maintain the sustain discharge during the sustain period SPD. At this time, when the last charge pulse (SUSPy) is supplied to the scan electrode (Y) in the form of the wall charge is accumulated, when the sustain pulse (S) in the scan electrode (Y) of FIG. SUSPy is applied and the ground potential GND is applied to the sustain electrode Z. Then, the positive polarity (+) voltage is supplied to the scan electrode Y by the sustain voltage difference Vs between the scan electrode Y and the sustain electrode Z. Negative wall charges are accumulated. In addition, since the voltage of the negative polarity (−) is supplied to the sustain electrode Z as compared with the scan electrode Y, the positive electrode wall charge is positively applied to the dielectric layer of the sustain electrode Z as shown in FIG. Will accumulate. In addition, since the ground potential GND is applied to the address electrode X, similar to the sustain electrode Z, the voltage of the negative polarity (−) is supplied to the address electrode X. Wall charges accumulate.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge. The erasing pulse EP has a lamp wave shape in which the light emission size is small, or a short pulse width of about 1 위해 for the discharge erasing. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge. That is, when the erase pulse EP having a voltage value gradually changing is applied to the sustain electrode Z, an erase discharge occurs between the scan electrode Y and the sustain electrode Z. In detail, since the voltage of the positive polarity (+) is gradually increased to the sustain electrode (Z), the wall charge of the negative polarity (-) is gradually increased to the dielectric layer of the sustain electrode (Z). Therefore, the positive wall charges accumulated in the dielectric layer of the sustain electrode Z at the time point of FIG. 4A are gradually reduced in combination with the gradually increasing negative wall charges. Similarly, when the erase pulse EP is applied to the sustain electrode Z, positive wall charges gradually accumulate in the dielectric layer of the scan electrode Y. Therefore, the negative (-) wall charge accumulated in the dielectric layer of the scan electrode (Y) at the time point of FIG. 4A is gradually reduced by coupling with the gradually increasing positive (+) wall charge.

Subsequently, the wall charges are accumulated at the time point (B) of FIG. 4 after the erasing pulse EP is supplied to the sustain electrode Z. As shown in FIG. The wall charges of the negative polarity (-) are weakly accumulated, and the wall charges of the positive polarity (+) are weakly accumulated in the sustain electrode Z as shown in FIG. Therefore, when the erasure discharge is completed in the previous subfield, the wall charges of the scan electrode Y and the sustain electrode Z disappear or all of the remaining charges are insignificant, so that the reset discharge is performed during the reset period RPD of the next subfield. In order to generate it, a high reset voltage must be supplied. Such a high reset voltage generates a light that should not occur during the reset period, which deteriorates the contrast performance. In detail, a large number of negative (−) wall charges are accumulated on the scan electrode (Y) by the sustain discharge at the time (A) of FIG. 4, and many positive (+) walls also exist on the sustain electrode (Z). Electric charges will accumulate. Subsequently, a slight amount of negative polarity (-) wall charges are left in the scan electrode (Y) by the erasing pulse (EP) during the erasure discharge, and a small amount of positive polarity (+) is also retained in the sustain electrode (Z). Wall charges remain. Only the weak amount of the wall charge thus erased does not affect the generation of the reset discharge during the reset period of the next subfield, and thus a high reset voltage must be supplied. Therefore, light that should not occur during the reset period is generated, which degrades the contrast performance.

Accordingly, an object of the present invention is to provide a method and a driving apparatus for a plasma display panel which can further stabilize wall voltage control and achieve high contrast ratio.

In order to achieve the above object, a driving method of a plasma display panel according to an exemplary embodiment of the present invention includes a scan electrode and a sustain electrode to which a sustain voltage is alternately applied, and a reset period for initializing the cell and selecting a cell. A method of driving a plasma display panel that is time-divided into an address period, a sustain period for sustaining discharge of a selected cell, and a stabilization period for stabilizing a wall voltage of a selected cell, wherein the first stabilization lamp voltage is applied to the scan electrode during the stabilization period. Applying; And floating the sustain electrode in a part of the period during which the first stabilization lamp voltage is applied.

Floating the sustain electrode in part of the period during which the first stabilization lamp voltage is applied; The sustain electrode is floated when the first stabilization lamp voltage is applied.

And applying a second stabilization lamp voltage to the sustain electrode within a period during which the first stabilization lamp voltage is applied after the sustain electrode is floated.

The sustain electrode is floated within a period of approximately 300 ns to 1.8 mW.

While the sustain electrode is floating, the voltage of the sustain electrode is formed to be about 1/2 or less of the sustain voltage.

The first stabilization lamp voltage rises to the sustain voltage for a first period and maintains the sustain voltage for a second period.

The second stabilization lamp voltage rises to the sustain voltage for a first period, maintains the sustain voltage for a second period, and falls to ground voltage for a third period.

Floating the sustain electrode in part of the period during which the first stabilization lamp voltage is applied; Grounding the sustain electrode for a predetermined period of time at a time point when the first stabilization lamp voltage is applied; The sustain electrode is floated for a second period after the first period within the period during which the first stabilization lamp voltage is applied.

And applying a second stabilization lamp waveform to the sustain electrode for a third period after the second period within the period during which the first stabilization lamp voltage is applied.

The sustain electrode is grounded to about 800 ns or less.

The sustain electrode is floated within a period of approximately 300 ns to 1 [mu] s.

While the sustain electrode is floating, the voltage of the sustain electrode is formed to be less than about 1/2 of the sustain voltage.

The first stabilization lamp voltage rises to the sustain voltage for a first period and maintains the sustain voltage for a second period.

The first period is included within a period in which the first stabilization lamp voltage rises.

An apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention includes a scan electrode and a sustain electrode to which a sustain voltage is alternately applied, and includes a reset period for initializing a cell, an address period for selecting a cell, and a selected cell. A driving apparatus of a plasma display panel which is time-divided and driven in a sustain period for sustain discharge and a stabilization period for stabilizing a wall voltage of a selected cell, comprising: a scan electrode driving circuit for supplying the sustain voltage and the first stabilization lamp voltage to the scan electrode; ; A sustain driving circuit for supplying the sustain voltage and the second stabilization lamp voltage to the sustain electrode; And a floating control circuit for floating the sustain electrode within the period during which the first stabilization lamp voltage is applied.

And a control unit for adjusting the scan driving circuit, the sustain driving circuit, and the floating control circuit.

The floating control circuit is formed as a switch disposed between the plasma display panel and the sustain driving circuit and controlled by the controller.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 13.

FIG. 6 is a diagram illustrating a driving waveform of a plasma display panel (hereinafter referred to as "PDP") according to the first embodiment of the present invention.

Referring to FIG. 6, in the setup period SU of the reset period, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a setup discharge with weak discharge between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD of the reset period, a falling ramp waveform Ramp-down, which starts to fall from approximately the sustain voltage Vs and drops to a base voltage GND or 0 [V], is applied to the scan electrodes Y. Supplied at the same time. While the falling ramp waveform Ramp-down is supplied to the scan electrodes Y, a positive sustain voltage Vs is supplied to the sustain electrode Z, and 0 [V] is supplied to the address electrode X. do. When the falling ramp waveform Ramp-down is supplied, a set-down discharge occurs with a weak discharge between the scan electrode Y and the sustain electrode Z and between the scan electrode Y and the address electrode X. At this time, excess wall charges unnecessary for the address discharge are erased among the wall charges formed during the setup discharge by the set-down discharge. Looking at the wall charge change during this reset period, there is almost no wall charge change on the address electrode (X), and negative (-) wall charges on the scan electrode (Y) formed during the setup discharge are partially reduced by the setdown discharge. . On the other hand, the positive wall charges are formed on the sustain electrode Z during the set-up discharge, but the negative wall charges are accumulated on the self as much as the decrease of the negative wall charges of the scan electrode Y during the set-down discharge.

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the on-cell to which the data pulse is supplied. In the on-cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. On-cells selected by the address discharge have a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is supplied as the wall voltage and the sustain pulse sus are added. Is generated.

After the sustain discharge is completed, the stabilization period continues. In the stabilization period, the first stabilization ramp waveform Ers1 is supplied to the scan electrode Y and the second stabilization ramp waveform Ers2 is supplied to the sustain electrode Z to stabilize the wall charge remaining in the cells of the full screen.

In the PDP driving waveform according to the first embodiment of the present invention, when the sustain period is completed, the stabilization ramp waveform Ers1 supplied and the setup waveform supplied in the reset period of the next subfield are set up in the first subfield. Since the size is smaller than the waveform, unnecessary discharge can be reduced, thereby achieving a high contrast ratio.

However, in the PDP driving waveform according to the first embodiment of the present invention, the second stabilization ramp waveform Ers2 supplied to the on-cell is applied after the first stabilization ramp waveform Ers1 is applied to the scan electrode Y. Voltage coupling occurs to cause the second stabilization ramp waveform Ers2 to become unstable as shown in FIG. 7. In addition, the second stabilization ramp waveform Ers2 is also severely changed depending on the load formed on the electrode. Accordingly, in the PDP driving waveform according to the first embodiment of the present invention, the wall charge becomes unstable.

8 is a diagram illustrating a PDP driving waveform according to a second embodiment of the present invention.

Referring to FIG. 8, in the PDP driving method according to the second embodiment of the present invention, the rising ramp waveform Ramp-up is supplied only to the first subfield SF1 of one frame. That is, in the driving method of the PDP according to the embodiment of the present invention, the contrast is improved by supplying the rising ramp waveform Ramp-up that causes the setup discharge to only the first subfield SF1 of one frame.

During the reset period of the first subfield in one frame, the rising ramp waveform Ramp-up, which is raised to the setup voltage Vsetup, is simultaneously applied to all the scan electrodes Y. This rising ramp waveform (Ramp-up) causes a small discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. After the rising ramp waveform Ramp-up is supplied, a falling ramp waveform Ramp-down falling from the sustain voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y. do. Ramp-down generates a slight microdischarge in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharge, and uniformly distributing the wall charges required for address discharge in the full screen cells. Will remain.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse is applied. A predetermined wall charge is generated in the cells selected by the address discharge.

On the other hand, the positive DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z from the time when the falling ramp waveform Ramp-down is supplied to the scan electrodes Y until the end of the address period.

In the sustain period, a sustain pulse su is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse (sus) is applied while the wall voltage and the sustain pulse (sus) in the cell are added. Discharge occurs. Here, the number of sustain pulses (sus) supplied during the sustain period is set corresponding to the luminance weight of each frame.

The first stabilization pulse Ers1 is supplied to the scan electrodes Y during the stabilization period after the sustain pulse sus is supplied. The first stabilization pulse Ers1 is supplied for a period T2 wider than the supply period T1 of the other sustain pulse su so that wall charges are sufficiently formed in the discharge cells. When the first stabilization pulse Ers1 is supplied to the scan electrodes Y, fine discharge is generated to uniform wall charges in the discharge cells. The first stabilization pulse Ers1 has a rising waveform that rises to the sustain pulse voltage level Vs for a predetermined period, and a voltage level that rises to the sustain pulse voltage level Vs until the stabilization period is completed after the rise is completed. It is made up of a sustained waveform. On the other hand, the second stabilizing pulse Ers2 is applied to the sustain electrode Z in the on-cell in which the sustain discharge occurs during the sustain period. The off-cells in which sustain discharge has not occurred in the first subfield maintain the wall charges formed in the reset period of the first subfield.

Hereinafter, the sustain period and the next reset period among the driving waveforms according to the second embodiment of the present invention will be described in detail with reference to FIGS. 9 to 12.

Subsequently, in the address period of the second subfield, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse is applied. A predetermined wall charge is generated in the cells selected by the address discharge.

As described above, the PDP driving waveform according to the second embodiment of the present invention expresses the gray level by repeating the reset period, the address period, the sustain period, and the stabilization period for each subfield.

9 is a diagram illustrating in detail a sustain period from a PDP driving waveform to a reset period of a next subfield according to the second embodiment of the present invention.

Referring to FIG. 9, in the PDP driving method according to the second embodiment of the present invention, a sustain pulse su corresponding to luminance as desired to be displayed on the scan electrode Y and the sustain electrode Z is applied during the sustain period. After the first stabilization pulse Ers1 having a long supply time is applied to the scan electrode Y, the sustain electrode Z is floated for a predetermined time and then the second stabilization pulse Ers2 is supplied. Specifically, in the period A, the second stabilization pulse Ers2 is sustained for a part of the period in which the second stabilization pulse Ers2 rises to the sustain voltage Vs immediately after the first stabilization pulse Ers1 supplied to the scan electrode Y is supplied. The electrode Z is grounded for a period of time without applying a waveform. At this time, the predetermined period during which the sustain electrode Z is grounded is preferably set to 800 ns or less. In the period B, the second stabilization pulse Ers2 of the sustain electrode Z is floated for a predetermined time after the first stabilization pulse Ers1 rises to a predetermined level before rising to the sustain voltage Vs, thereby rising to a constant voltage. do. Here, the predetermined time is about 300 ns to about 1 us, and the constant voltage is smaller than half of the sustain voltage level Vs. After the voltage of the second stabilization pulse Ers2 of the sustain electrode Z is raised to a constant voltage, a stabilization ramp waveform is further applied in the period C. Accordingly, in the PDP driving method according to the first embodiment of the present invention, it is possible to prevent distortion of the second stabilizing pulse Ers2 supplied to the sustain electrode Z, thereby stably controlling the wall voltage. Further, in the first subfield, the off-cells are applied with a ramp ramp waveform having a small slope in the next reset period to compensate for the reduced wall charge during the previous subfield period. Such a ramp ramp waveform with a small gradient can achieve high contrast ratio by keeping the wall charge in a state where discharge can be generated with almost no microdischarge. In addition, the PDP driving waveform according to the second embodiment of the present invention in the on-cell may be supplied with a waveform as shown in FIG. 10 in which the rising ramp waveform is not supplied in the second subfield reset period, thereby achieving a high contrast ratio. That is, in the PDP driving waveform according to the second embodiment of the present invention, a waveform that maintains the wall charges of the previous sustain period is applied during the second reset period, wherein the wall charges are supplied with the stabilization pulse Ers1 supplied during the stabilization period of the previous subfield. , Due to Ers2), it is possible to achieve a high contrast ratio by distributing in a form necessary for discharging without microdischarge.

11 illustrates a PDP driving waveform according to a third embodiment of the present invention.

The PDP driving waveform according to the third embodiment of the present invention is the same as the remaining period except for the sustain period as compared to the PDP driving waveform according to the second embodiment of the present invention, and thus the description except for the sustain period will be omitted.

Referring to FIG. 11, in the PDP driving method according to the third embodiment of the present invention, a sustain pulse su corresponding to luminance as desired to be displayed on the scan electrode Y and the sustain electrode Z is applied during the sustain period. After the first stabilization pulse Ers1 having a long supply time is applied to the scan electrode Y, the second stabilization pulse Ers2 of the sustain electrode Z is floated for a predetermined time and then stabilized ramp waveform. -ers) supply more. Specifically, in the period A, the first stabilization pulse Ers1 supplied to the scan electrode Y rises to the sustain voltage Vs and the second stabilization pulse of the sustain electrode Z is maintained for a predetermined time. Ers2 is floated from the ground level to a constant voltage. Here, the predetermined time is about 300 ns to about 1.8 us, and the constant voltage is a value (Vs / 2) corresponding to half of the sustain voltage Vs. In period B, the stabilization ramp waveform (ramp-ers) is further applied after the voltage of the second stabilization pulse Ers2 of the sustain electrode Z is raised to a constant voltage in period A. Accordingly, in the PDP driving method according to the third embodiment of the present invention, it is possible to prevent distortion of the second stabilizing pulse Ers2 supplied to the sustain electrode Z, thereby stably controlling the wall voltage. Here, the PDP driving method according to the third embodiment of the present invention is transferred to the setup (SU) section of the reset period of the second subfield as in the PDP driving method according to the second embodiment of the present invention as shown in FIG. 12. A waveform that maintains the voltage supplied to the sustain section of the subfield can be applied to achieve a high contrast ratio.

Herein, in the second and third embodiments of the present invention, the stabilization ramp waveforms (ramp-ers) additionally supplied to the second stabilization pulse Ers2 will be described. A rising ramp waveform rising to the sustain voltage level Vs during the second period, a sustain waveform holding the sustain voltage level Vs for the second period, and a falling ramp waveform falling to the ground level for the third period.

In addition, the driving apparatus of the PDP according to the first to third embodiments of the present invention may have a configuration as shown in FIG.

Referring to FIG. 13, a driving apparatus of a plasma display panel according to an exemplary embodiment of the present invention includes a scan driving circuit 50 for supplying scan pulses to a scan electrode Y of a plasma display panel, and a sustain to a sustain electrode Z. A controller for controlling the sustain driver circuit 60 for supplying a voltage, the switch 55 for floating the sustain electrode Z, the scan driver circuit 50, the sustain driver circuit 60, and the switch 55 ( 70).

The structure of the plasma display panel driving apparatus according to the embodiment of the present invention floats the sustain electrode Z under the control of the switch 55 provided between the plasma display panel PDP and the sustain driving circuit 60. In this way, the driving method of the plasma display panel according to the embodiment of the present invention can be achieved.

As described above, the PDP driving method and the driving apparatus according to the embodiment of the present invention can not only achieve a high contrast ratio through the application of a stable waveform, but also further stabilize the wall voltage control. In addition, the selective reset reliably occurs regardless of the change in the external environment, so that the wall voltage can be stably formed, thereby preventing the occurrence of erroneous discharge.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

A scan electrode and a sustain electrode to which the sustain voltage is alternately applied, the reset period for initializing the cell, the address period for selecting the cell, the sustain period for sustaining discharge of the selected cell, and the wall voltage of the selected cell are stabilized. In the driving method of the plasma display panel which is time-division driven in the stabilization period, Applying a first stabilization lamp voltage to the scan electrode during the stabilization period; Floating the sustain electrode in a part of a period during which the first stabilization lamp voltage is applied; And Applying a second stabilization lamp voltage to the sustain electrode within a period during which the first stabilization lamp voltage is applied after the sustain electrode is floated. Method of driving a plasma display panel comprising a. The method of claim 1, Floating the sustain electrode in part of the period during which the first stabilization lamp voltage is applied; And floating the sustain electrode at a time point when the first stabilization lamp voltage is applied to the plasma display panel. delete The method of claim 2, And the sustain electrode is floated within a period of approximately 300 ns to 1.8 mW. The method of claim 2, While the sustain electrode is floating, the voltage of the sustain electrode is And approximately one half voltage or less of the sustain voltage. The method of claim 2, The first stabilization lamp voltage is Rises to the sustain voltage for a first period; And the sustain voltage is maintained for a second period of time. The method of claim 1, The second stabilization lamp voltage is Rises to the sustain voltage for a first period; Maintain the sustain voltage for a second period of time, And a voltage drop to ground voltage for a third period. The method of claim 1, Floating the sustain electrode in part of the period during which the first stabilization lamp voltage is applied; Grounding the sustain electrode for a predetermined period of time at a time point when the first stabilization lamp voltage is applied; And floating the sustain electrode for a second period after the first period within the period during which the first stabilization lamp voltage is applied. The method of claim 8, And applying a second stabilization lamp waveform to the sustain electrode for a third period after the second period within the period during which the first stabilization lamp voltage is applied. The method of claim 8, And the sustain electrode is grounded to approximately 800 ns or less. The method of claim 8, And the sustain electrode is floated within a period of approximately 300 ns to 1 [mu] s. The method of claim 8, And the voltage of the sustain electrode is smaller than approximately half of the sustain voltage while the sustain electrode is floating. The method of claim 8, The first stabilization lamp voltage is Rises to the sustain voltage for a first period; And the sustain voltage is maintained for a second period of time. The method of claim 8, The first period is And a first stabilization lamp voltage within a period of time of rising. A scan electrode and a sustain electrode to which the sustain voltage is alternately applied, the reset period for initializing the cell, the address period for selecting the cell, the sustain period for sustaining discharge of the selected cell, and the wall voltage of the selected cell are stabilized. In the driving apparatus of the plasma display panel which is time-division driven by the stabilization period, A scan electrode driving circuit for supplying the sustain voltage and the first stabilization lamp voltage to the scan electrodes; A floating control circuit for floating the sustain electrode within a period during which the first stabilization lamp voltage is applied; And a sustain driving circuit for supplying the sustain voltage to the sustain electrode and supplying a second stabilization lamp voltage to the sustain electrode within a period during which the first stabilization lamp voltage is applied after the sustain electrode is floated. A driving device of the plasma display panel. The method of claim 15, And a control unit for adjusting the scan driving circuit, the sustain driving circuit, and the floating control circuit. The method of claim 15, The floating control circuit And a switch disposed between the plasma display panel and the sustain driving circuit and controlled by the controller.

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