KR20100008949A - Plasma display apparatus and method for driving of plasma display panel - Google Patents

Abstract

PURPOSE: A plasma display device and a drive method of a plasma display panel are provided to improve picture quality by preventing wrong discharging from being generated in a selective elimination sub field. CONSTITUTION: A plasma display panel(100) comprises a scan electrode, a sustain electrode and an address electrode crossing with the scan electrode and the sustain electrode. A driver(110) supplies the drive signals to the scan electrode, the sustain electrode, or the address electrode. The driver comprises a drive device implementing images on the screen of a plasma display panel.

Description

Plasma Display Apparatus and Method for Driving of Plasma Display Panel

The present invention relates to a plasma display device and a method of driving the plasma display panel.

In the plasma display panel, a phosphor layer is formed in a discharge cell divided by a partition, and a plurality of electrodes are formed.

When the drive signal is supplied to the electrode of the plasma display panel, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generate. The visible light displays an image on the screen of the plasma display panel.

The present invention provides a plasma display apparatus and a plasma display capable of preventing the occurrence of mis-discharge by adjusting the number of selective erase subfields to which a data signal is supplied to an address electrode in an address period among a plurality of selective erase subfields. Its purpose is to provide a method of driving a panel.

A plasma display apparatus according to the present invention includes a plasma display panel including a scan electrode and a sustain electrode, an address electrode intersecting the scan electrode and the sustain electrode, and a discharge cell formed at a point where the scan electrode and the sustain electrode cross the address electrode; Pixel data writing means for selectively erasing charges formed in the discharge cells in accordance with the pixel data corresponding to the gray level of the input image signal, and a sustain signal supplied to at least one of the scan electrode and the sustain electrode, which are not erased. And sustain means for sustaining the discharge in the discharge cell, wherein the data writing means performs a data writing operation by selective erasing in at least two subfields of the plurality of subfields according to the pixel data.

In addition, the data writing means is characterized in that for at least one subfield of the plurality of subfields, selective write discharge for selectively forming charges in the discharge cells is caused.

In addition, the data writing means is characterized by causing selective write discharge which selectively forms charge in the discharge cells in the first subfield among the plurality of subfields.

In addition, the data writing means is characterized in that the data writing operation is repeated in the successive subfields when the pixel data is low gradation.

In addition, the driving method of the plasma display panel according to the present invention supplies a data signal to an address electrode in an address period of at least two consecutive subfields among a plurality of selective erasing subfields in at least one frame among a plurality of frames, and The scan signal corresponding to the data signal may be supplied to the electrode.

In addition, the selective erasing subfield may be a subfield that turns off the discharge cells supplied with the data signal to the address electrodes in the address period in the sustain period after the address period.

The plurality of frames may include a first frame and a second frame having different gradation values, the gradation values of the first frame being smaller than the gradation values of the second frame, and in the first frame, the plurality of frames may be consecutive. The data signal is supplied to the address electrode in the address period of at least two subfields, the scan signal is supplied to the scan electrode, and the address electrode is supplied to the address electrode in the address period of one subfield of the plurality of selective erasing subfields in the second frame. The data signal may be supplied, and the scan signal may be supplied to the scan electrode.

In addition, the frame may include at least one optional write subfield.

In addition, the selective write subfield may be the first subfield among the plurality of subfields of the frame.

The selective write subfield may be a subfield that turns off the discharge cells supplied with the data signal to the address electrodes in the address period in the sustain period after the address period.

In addition, another plasma display panel according to the present invention is configured to supply a data signal to an address electrode in an address period of an N (N is a natural number) th selective erase subfield first of a plurality of selective erase subfields in a first frame (Frame1). And supplying a data signal to an address electrode in an address period of an M (M is a natural number greater than N) th selective erasing subfield for the first of the plurality of selective erasing subfields. The number of selective erasure subfields that supply data signals among the plurality of selective erasure subfields of one frame may be greater than the number of selective erasure subfields that supply data signals among the plurality of selective erasure subfields of the second frame.

In the first frame, the data signal can be supplied to the address electrode in the address period of the Nth subfield and the N + 1th subfield.

The third frame Frame3 further includes supplying a data signal to the address electrode in the address period of the P (P is a natural number greater than M) th selective erasure subfield first of the plurality of selective erasure subfields. The number of selective erasure subfields that supply data signals among the plurality of selective erasure subfields of two frames may be equal to the number of selective erasure subfields that supply data signals among the plurality of selective erasure subfields of the third frame.

In addition, the selective erasing subfield may be a subfield that turns off the discharge cells supplied with the data signal to the address electrodes in the address period in the sustain period after the address period.

The method may further include omitting a data signal in an address period of at least one selective erasing subfield among at least one selective erasing subfield disposed later in time than the N-th subfield.

Further, the number of selective erasure subfields supplying a data signal among the plurality of subfields of the first and second frames may be less than half of the total number of the plurality of selective erasure subfields included in the first and second frames.

In another method of driving a plasma display panel according to the present invention, a plurality of selective erasing subfields are disposed later in time than the selective writing subfields, and in the first frame (Frame1), a first of the plurality of selective erasing subfields is first performed. The process of supplying a data signal to the address electrode in the address period of the Nth selective erasing subfield and in the second frame (Frame2), M (M is a natural number greater than N) first of the plurality of selective erasing subfields. And supplying a data signal to the address electrode in the address period of the selective erasing subfield, wherein the number of the selective erasing subfields supplying the data signal among the plurality of selective erasing subfields of the first frame is determined by the plurality of selective erasing subfields. Of the selective erase subfields to supply data signals There can be more than.

Further, the selective erasing subfield is a subfield that turns off the discharge cells supplied with the data signal to the address electrode in the address period in the sustain period after the address period, and the selective write subfield is the data signal to the address electrode in the address period. May be a subfield that turns on the discharge cells supplied in the sustain period after the address period.

The driving method of the plasma display panel according to the present invention has the effect of improving the image quality of the image to be implemented by preventing the occurrence of mis-discharge in the selective erasure sub-field.

Hereinafter, a driving method of a plasma display apparatus and a plasma display panel according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram for explaining a configuration of a plasma display device.

Referring to FIG. 1, the plasma display apparatus includes a plasma display panel 100 and a driver 110.

The plasma display panel 100 may include scan electrodes Y1 to Yn and sustain electrodes Z1 to Zn that are parallel to each other, and may include address electrodes X1 to Xm that cross the scan electrode and the sustain electrode.

The driving unit 110 may include a driving device that supplies an driving signal to at least one of a scan electrode, a sustain electrode, and an address electrode of the plasma display panel 100 so that an image is displayed on the screen of the plasma display panel 100. .

Preferably, the driving unit 110 includes pixel data writing means for generating selective erasure discharge for selectively erasing charges formed in the discharge cells of the plasma display panel 100 according to the pixel data corresponding to the gray level of the input image signal ( And a sustain means (not shown) for supplying a sustain signal to at least one of the scan electrode and the sustain electrode of the plasma display panel 100 to sustain the discharge in the non-erased discharge cell.

Here, the data writing means may perform a data writing operation by selective erasing in at least two subfields of the plurality of subfields according to the pixel data.

The operation of the driving unit 110 will be described in more detail below.

Here, in FIG. 1, only the case in which the driving unit 110 is formed in one board form is illustrated, but in the present invention, the driving unit 110 is divided into a plurality of board forms according to electrodes formed on the plasma display panel 100. It is also possible to lose. For example, the driver 110 may include a first driver (not shown) for driving the scan electrode of the plasma display panel 100, a second driver for driving the sustain electrode, and a third driver (not shown) for driving the address electrode. Can be divided into

2 is a diagram for explaining the structure of a plasma display panel.

Referring to FIG. 2, the plasma display panel 100 includes a front substrate 201 in which scan electrodes 202 and Y and sustain electrodes 203 and Z are parallel to each other, and scan electrodes 202 and Y and a sustain electrode ( The back substrate 211 on which the address electrodes 213 and X intersect with 203 and Z may be formed.

The discharge currents of the scan electrodes 202 and Y and the sustain electrodes 203 and Z are limited on the scan electrodes 202 and Y and the sustain electrodes 203 and Z, and the scan electrodes 202 and Y and the sustain electrodes ( An upper dielectric layer 204 may be arranged to insulate between 203 and Z).

A protective layer 205 may be formed on top of the upper dielectric layer 204 to facilitate discharge conditions. The protective layer 205 may include a material having a high secondary electron emission coefficient, such as magnesium oxide (MgO) material.

Address electrodes 213 and X may be formed on the rear substrate 211, and a lower dielectric layer 215 may be formed on the address electrodes 213 and X to insulate the address electrodes 213 and X.

On top of the lower dielectric layer 215, a partition space 212, such as a stripe type, a well type, a delta type, a honeycomb type, etc., is formed on the discharge space, that is, to partition the discharge cells. Can be. Accordingly, the first discharge cell emitting red (R) light, the second discharge cell emitting blue (B) light, and the green (Green) light between the front substrate 201 and the rear substrate 211. : G) A third discharge cell or the like that emits light can be formed.

A predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, a first phosphor layer that generates red light, a second phosphor layer that generates blue light, and a third phosphor layer that generates green light may be formed.

FIG. 3 is a diagram for describing a structure of a frame for implementing gradation of an image.

Referring to FIG. 3, a frame for implementing gray levels of an image may include a plurality of selective erase subfields SF1 to SF8.

Although not shown, the plurality of selective erasing subfields divide the discharge cells into an address period for selecting a discharge cell in which discharge will not occur and a sustain period for implementing gradation according to the number of discharges. Can lose.

For example, when an image is to be displayed with 256 gray scales, for example, one image frame is divided into eight subfields SF1 to SF8 as shown in FIG. 3, and each of the eight subfields SF1 to SF8, respectively. May be divided into an address period and a sustain period.

Here, the selective erasing subfield may be configured to turn off a discharge cell supplied with a data signal Data corresponding to a scan signal to an address electrode of the plasma display panel in an address period in a sustain period after the address period. Field.

The gray scale weight of the corresponding subfield may be set by adjusting the number of the sustain signals supplied in the sustain period. That is, a predetermined gray scale weight can be given to each subfield using the sustain period. For example, the gray scale weight of each subfield is 2 ⁿ by setting the gray scale weight of the first subfield to 2 ⁰ and the gray scale weight of the second subfield to 2 ¹ (where n = 0, 1). , 2, 3, 4, 5, 6, and 7) to increase the gray scale weight of each subfield. As described above, gray levels of various images may be realized by adjusting the number of sustain signals supplied in the sustain period of each subfield according to the gray scale weight in each subfield.

In FIG. 3, only one image frame is composed of eight subfields. However, the number of subfields constituting one image frame may be variously changed. For example, one video frame may be configured with 12 subfields from the first subfield to the twelfth subfield, or one video frame may be configured with 10 subfields.

In addition, in FIG. 3, subfields are arranged in the order of increasing magnitude of gray scale weight in one image frame. Alternatively, subfields may be arranged in order of decreasing gray scale weight in one image frame. Alternatively, subfields may be arranged regardless of the gray scale weight.

In addition, although FIG. 3 illustrates only the case where all subfields included in the frame are selective erasing subfields, at least one of the plurality of subfields included in the frame may also be a selective write subfield. It is possible.

Here, the selective write subfield is a subfield that turns on a discharge cell supplied with a data signal corresponding to a scan signal to an address electrode in an address period in a sustain period after the address period.

4 is a diagram for explaining an example of driving waveforms in the selective write subfield and the selective erase subfield. The driving signals to be described below are supplied by the driving unit 110 of FIG. 1.

Referring to FIG. 4, the first reset signal RS1 may be supplied to the scan electrode Y in a reset period for initializing the selective write subfield SW.

Here, the first reset signal RS1 may include a first rising signal RU1 in which the voltage gradually rises and a first falling signal RD1 in which the voltage gradually falls. Here, the first rising signal gradually rises from the first voltage V1 higher than the voltage of the ground level GND to the second voltage V2, and the first falling signal is the maximum voltage V2 of the first rising signal. The third voltage V3 may be gradually lowered from the lower third voltage V3 to the fourth voltage V4 lower than the voltage of the ground level GND. The first voltage V1 may be substantially the same as the third voltage V3.

When the first rising signal is supplied to the scan electrode, weak dark discharge, that is, setup discharge, may occur in the discharge cell by the first rising signal. By this setup discharge, some wall charges can be accumulated in the discharge cells.

Thereafter, a first falling signal having a polarity opposite to that of the first rising signal may be supplied to the scan electrode after the first rising signal. Then, a weak erase discharge, that is, a set down discharge may occur in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated can be uniformly retained in the discharge cells.

In the address period after the reset period, the first scan bias signal Ybias1 having a voltage Vsc1 higher than the lowest voltage V4 of the first falling signal may be supplied to the scan electrode.

In addition, a scan signal Scan falling from the first scan bias signal Ybias 1 may be supplied to the scan electrode.

When the scan signal is supplied to the scan electrode, the data signal Data may be supplied to the address electrode X corresponding to the scan signal.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage caused by the wall charges generated in the reset period are added. After the address discharge occurs in the address period of the selective write subfield, a sufficient amount of wall charges can be formed in the discharge cell to generate the sustain discharge when the sustain signal is supplied. In this way, the address discharge generated in the address period of the selective write subfield is referred to as selective write discharge or write address discharge.

The first sustain bias signal Zbias 1 may be supplied to the sustain electrode in order to prevent the address discharge from becoming unstable due to the interference of the sustain electrode Z in the address period.

Subsequently, in the sustain period for displaying an image, the sustain signal SUS may be supplied to at least one of the scan electrode and the sustain electrode. For example, a sustain signal may be alternately supplied to the scan electrode and the sustain electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal, and a sustain discharge, i.e., display between the scan electrode and the sustain electrode when the sustain signal is supplied. Discharge may occur.

Meanwhile, in the at least one subfield, a plurality of sustain signals are supplied in the sustain period, and the pulse width of at least one sustain signal of the plurality of sustain signals may be different from the pulse widths of other sustain signals. For example, the pulse width of the sustain signal that is supplied first of the plurality of sustain signals may be larger than the pulse width of other sustain signals. Then, the sustain discharge can be more stabilized.

That is, the data writing means of the driving unit 110 of FIG. 1 generates selective write discharge that selectively forms charge in the discharge cells in at least one subfield among the plurality of subfields.

In addition, the selective write subfield may be the first subfield among the plurality of subfields of the frame. In this case, it is preferable that the data writing means of the driving unit 110 of FIG. 1 cause selective write discharge to selectively form charges in the discharge cells in the first subfield of the plurality of subfields.

In the selective erase subfield SE that is disposed later in time than the selective write subfield described above, the reset signal may not be supplied to the scan electrode in the reset period, or the reset period for initialization may be omitted.

In addition, in the address period, the second scan bias signal Ybias 2 may be supplied to the scan electrode, and the scan signal Scan that descends from the second scan bias signal may be supplied.

Also. The data signal Data corresponding to the scan signal may be supplied to the address electrode.

Then, the address discharge is generated by the voltage difference between the scan signal and the data signal in the address period of the selective erasure subfield, so that wall charges can be erased in the discharge cell. In this way, the address discharge occurring in the address period of the selective erasure subfield is referred to as selective erasure discharge or erase address discharge.

As such, when the data signal is supplied to the address electrode in the address period of the selective erasing subfield, the wall charges can be erased by the discharge generated by the data signal and the scan signal. Thus, the scan electrode and Even when the sustain signal is supplied to at least one of the sustain electrodes, sustain discharge may not occur.

Here, when comparing the address periods of the selective write subfield and the selective erase subfield, since the discharge cells turned on in the sustain period must be selected in the address period of the selective write subfield, sufficient wall charges must be formed during address discharge. . Therefore, it may be desirable that the pulse width of the scan signal supplied to the scan electrode in the address period of the selective write subfield is sufficiently wide or the voltage is sufficiently large.

On the other hand, in the address period of the selective erasing subfield, since the discharge cells to be turned off in the sustain period must be selected, a sufficient amount of wall charges must be erased during address discharge. Therefore, it may be preferable that the pulse width of the scan signal supplied to the scan electrode in the address period of the selective erasing subfield is sufficiently small or the voltage is sufficiently small.

Alternatively, the data signal supplied to the address electrode in the address period of the selective erase subfield has a sufficiently small pulse width or a sufficiently small magnitude of voltage compared to the data signal supplied to the address electrode in the address period of the selective write subfield. It may also be desirable.

On the other hand, in order to prevent the strong discharge between the scan electrode and the sustain electrode in the address period of the selective erasure subfield, and to erase the wall charge more uniformly, the magnitude of the voltage than the first sustain bias signal Zbias 1 on the sustain electrode. Can supply the second sustain bias signal Zbias 2 which is small.

The voltage Vzb1 of the first sustain bias signal Zbias 1 may be higher than the ground level GND and lower than the voltage Vs of the sustain signal SUS supplied to at least one of the scan electrode and the sustain electrode in the sustain period. . In addition, the voltage of the second sustain bias signal Zbias 2 may be lower than the voltage Vzb2 of the first sustain bias signal Zbias 1.

On the other hand, the first subfield disposed in time in any frame may be a selective write subfield, the remaining subfield may be a selective erase subfield.

5 to 7 are diagrams for describing a method of driving a plasma display panel. Here, a mark indicates that the data signal is supplied to the address electrode in the address period. In addition, the gradation level from 0 to 12 indicates the gradation level of the image to be implemented, and may not display the gradation value itself of the image to be implemented.

First, FIG. 5 illustrates a case in which one frame includes 12 subfields SF1 to SF12, and all 12 subfields are selective erasure subfields.

Referring to FIG. 5, when the zero gray level is implemented, the data signal may be supplied to the address electrode in the address period of the first subfield SF1 to the fourth subfield SF4.

When all the subfields included in one frame are selective erasing subfields, after all the discharge cells are turned on before the first subfield SF1 disposed first in time, the first subfield is turned on. The discharge cell to be turned off is selected from the subfield. Accordingly, in order to implement the zero gray level, the first gray level is first turned off.

In addition, when one gray level is implemented, the data signal may be supplied to the address electrode in the address period of the second subfield SF2 to the fourth subfield SF4. In this case, sustain discharge occurs in the first subfield, that is, the first subfield is turned on, and sustain discharge is not generated in the subsequent second subfield, i.e., turned off from the second subfield. The gray level of the image may be implemented by light generated in the sustain period. In FIG. 5 to FIG. 6, portions indicated as etch indicate subfields that are turned on.

In the case of implementing the two gray level levels, the data signal may be supplied to the address electrode in the address period of the third subfield SF3 to the fourth subfield SF4. In this case, sustain discharge occurs in the first and second subfields, and sustain discharge does not occur from the third subfield afterwards, so that light generated in the sustain periods of the first subfield and the second subfield is caused. The gray level of the image may be implemented.

In addition, in the case of implementing the three gradation levels, the data signal may be supplied to the address electrode in the address period of the fourth subfield SF4. In such a case, sustain discharge occurs in the first, second, and third subfields, and sustain discharge does not occur from the fourth subfield thereafter, so that light generated in the sustain periods of the first, second, and third subfields is generated. The gray level of the image can be implemented.

In the case of implementing the 12th gradation level, the data signal may not be supplied to the address electrode in the address period of all the subfields, that is, the first subfield SF1 to the twelfth subfield SF12. In this case, since sustain discharge occurs in the first to twelve subfields, the gray level of the image may be implemented by light generated in the sustain periods of the first to twelve subfields.

A total of 13 gray levels can be implemented using the method described above, and it is possible to implement various gray levels of the image by using the 13 gray levels.

That is, the data writing means of the driving unit 110 of FIG. 1 may cause a data writing operation by selective erasing, that is, selective erasing discharge in at least two subfields of the plurality of subfields according to the pixel data.

In addition, it may be preferable that the data writing means repeatedly performs the data writing operation in successive subfields when the pixel data is low gradation. That is, selective erasure discharge may be generated in at least two selective erasure subfields in a region where pixel data is low grayscale.

In addition, referring to FIG. 5, the number of selective erasing subfields to which a data signal is supplied to an address electrode in an address period among a plurality of selective erasing subfields when implementing one gray level and three gray levels is implemented. You can see that is different. That is, the number of selective erasure subfields to which the data signal is supplied to the address electrode in the address period among the plurality of selective erasure subfields of the frame implementing one gray level and the frame implementing three gray levels may be different.

In other words, when the sum of gradation weights of the selective erasing subfields that are turned on among the plurality of selective erasing subfields included in the first frame when the first frame and the second frame are compared is smaller than the second frame, Among the plurality of selective erase subfields of the first frame, the number of the selective erase subfields to which the data signal is supplied to the address electrode in the address period may be larger than that of the second frame. Here, the sum of gray level weights of the selective erasing subfield to be turned on may correspond to the total sum of the number of sustain signals supplied in the sustain period of the selective erasing subfield to be turned on.

Here, the sum of the gray scale weights of the selective erasing subfields that are turned on may be determined by the position of the selective erasing subfields that are first turned off among the plurality of selective erasing subfields, that is, the data signal is first supplied to the address electrodes in the address period.

As a result, the data signal is changed depending on the position of the selective erasing subfield that is first turned off among the plurality of selective erasing subfields, that is, the selective erasing subfield in which the data signal is first supplied to the address electrode in the address electrode period among the plurality of erasing subfields. It is possible to change the number of selective erasing subfields to supply.

Preferably, the faster the position of the first selective erase subfield among the plurality of selective erase subfields in time, the greater the number of selective erase subfields to which a data signal is supplied.

For example, when comparing a first frame with a second frame, a plurality of selective erasing subfields included in the second frame have positions of the first selective erasing subfields among the plurality of selective erasing subfields included in the first frame. When the time is faster than the position of the first selective erase subfield of the field, the number of the selective erase subfields to which the data signal is supplied in the address period is more than the second frame among the plurality of selective erase subfields of the first frame. There can be many.

As a result, in the first frame Frame1, the data signal is supplied to the address electrode in the address period of the N (N is a natural number) th selective erasure subfield first among the plurality of selective erasure subfields, and in the second frame Frame2, When the data signal is supplied to the address electrode in the address period of the M (M is a natural number greater than N) th selective erasure subfield first, the data signal of the plurality of selective erasure subfields of the first frame is returned. The number of selective erase subfields to supply is larger than the number of selective erase subfields to supply a data signal among the plurality of selective erase subfields of the second frame.

Meanwhile, as shown in FIG. 6, at least one of the plurality of subfields included in the frame may be an optional write subfield, and the remaining subfields may be an optional erase subfield.

For example, as shown in FIG. 6, one frame includes a total of 12 subfields from the first subfield SF1 to the twelfth subfield SF12, and among the 12 subfields, the first subfield disposed first in time. It is possible that one subfield SF1 is an optional write subfield and the remaining subfields are selective erase subfields.

As described above, when the frame includes at least one selective write subfield and an optional erase subfield, the selective write subfield is arranged to be temporally ahead of the selective erase subfield, and the discharge cells selected in the selective write subfield are disposed. The image may be implemented by selectively turning off the subsequent selective erasure subfield. Therefore, since it is possible to selectively turn off the discharge cells selectively turned on in the selective write subfield in the selective erase subfield without turning on all the discharge cells, it is possible to improve the contrast characteristic of the image to be implemented. .

In the case of FIG. 6, when the zero gray level is implemented, the data signal may not be supplied to the address electrode in the address period of all subfields, that is, the first subfield SF1 through the twelfth subfield SF12.

When the first subfield SF1 arranged in time among the plurality of subfields included in one frame is an optional write subfield, the data signal is not supplied to the address electrode in the address period of the first subfield. If no sustain discharge is generated, there is no need to turn off the plurality of selective erase subfields that are subsequently disposed. Therefore, in the case of implementing the zero gradation level, the data signal is not supplied to the address electrodes in the address periods of all the subfields.

In addition, when one gray level is implemented, the data signal may be supplied to the address electrode in the address period of the first subfield SF1 to the fourth subfield SF4. In such a case, sustain discharge occurs in the first subfield, which is an optional write subfield, and erase address discharge occurs in the second subfield after that by the data signal supplied to the address electrode in the address period, thereby being disposed later. From the two subfields, sustain discharge may not occur.

In the case of implementing the two-gradation level, the data signal may be supplied to the address electrode in the address period of the first subfield, the third subfield SF3, and the fourth subfield SF4. In this case, sustain discharge occurs in the first and second subfields, and sustain discharge does not occur from the third subfield afterwards, so that light generated in the sustain periods of the first subfield and the second subfield is caused. The gray level of the image can be implemented.

Referring to FIG. 6 described above, as shown in FIG. 5, an optional erase subfield that is first turned off among the plurality of selective erase subfields, that is, an address electrode in the address electrode period for the first time among the plurality of erase subfields. The number of selective erasure subfields supplying the data signal may be changed according to the position of the selective erasure subfields to which the data signal is supplied.

As described above, the reason for changing the number of selective erasing subfields for supplying a data signal to the address electrode in the address period in accordance with the position of the first selective erasing subfield among the plurality of selective erasing subfields is as follows. Looking at it as follows.

FIG. 7 illustrates an example in which the number of selective erasing subfields supplying a data signal to the address electrode in the address period is substantially constant regardless of the position of the selective erasing subfield first turned off among the plurality of selective erasing subfields. Is shown. Here, it is assumed that one frame includes at least one selective write subfield SF1 and a plurality of selective erase subfields SF2 to SF12 as in the case of FIG. 6.

For example, when one gray level is implemented, a data signal is supplied to the address electrode in the address period of the second subfield SF2 among the plurality of selective erase subfields, and when the two gray level is implemented, a plurality of optional When the data signal is supplied to the address electrode in the address period of the third subfield SF3 among the erase subfields, and the four gradation levels are implemented, the address period of the fourth subfield SF4 among the plurality of selective erase subfields. The data signal can be supplied to the address electrode at. That is, the erase address discharge is generated by supplying the data signal to the address electrode in the address period only in the first selective erase subfield that is turned off among the plurality of selective erase subfields.

In this case, the selective erase subfield to be turned off when the erase address discharge generated by the data signal supplied to the address electrode and the scan signal supplied to the scan electrode in the address period of the selective erase subfield first turned off becomes unstable. By turning on, there is a possibility that the image quality of the image to be implemented is deteriorated. This possibility may be higher as the position of the selective erasure subfield first turned off in time.

For example, assume that any frame implements one gradation level.

In this case, after turning on the first subfield by supplying a data signal to the address electrode in the address period of the first subfield SF1 which is the selective writing subfield, the second subfield SF2 which is the selective erasing subfield. The second subfield can be turned off by supplying a data signal to the address electrode in the address period of.

Meanwhile, in the first subfield arranged in time in one frame, the number of sustain signals supplied to at least one of the scan electrode and the sustain electrode in the sustain period may be relatively small. Then, the number of sustain discharges in the sustain period of the first subfield is also relatively small, so that the distribution of wall charges in the discharge cells becomes relatively unstable after the sustain period of the first subfield.

In addition, the erase address discharge generated in the second subfield may be greatly influenced by the distribution of wall charges after the sustain period of the first subfield, so that the erase address discharge in the second subfield may also become unstable. It is big.

As described above, when the erase address discharge of the second subfield becomes unstable, wall charges may not be sufficiently erased in the address period of the second subfield, and an excessively large amount of wall charge may remain in the discharge cell. Then, even when the sustain discharge occurs in the sustain period of the second subfield to be turned off, the image quality of the image to be implemented may be deteriorated.

On the other hand, when the data signal is supplied to the address electrodes in the address periods of the 3 and 4 subfields in addition to the second subfield as in the case of FIGS. Since another erase address discharge can be generated by supplying a data signal to the electrode to sufficiently erase the wall charges in the discharge cell, even if the erase address discharge in the second subfield becomes unstable, another selective erase after the second subfield is performed. It is possible to prevent the subfield from turning on. Accordingly, the image quality of the implemented image can be improved.

On the other hand, in the case of a frame implementing the ninth gray level, an erase address discharge may be generated by supplying a data signal to the address electrode in the address period of the tenth subfield SF10 among the plurality of selective erase subfields.

In this case, a sufficient number of sustain discharges may already occur in the first subfield SF1 to the ninth subfield SF9, so that the distribution of wall charges in the discharge cells after the sustain period of the ninth subfield is It can be relatively stable. Therefore, even if the data signal is supplied to the address electrode in the address period only in the tenth subfield to generate the erase address discharge, the subsequent selective erase subfield can be prevented from turning on.

As a result, in the first frame Frame1, the data signal is supplied to the address electrode in the address period of the N (N is a natural number) th selective erasure subfield first among the plurality of selective erasure subfields, and in the second frame Frame2, When the data signal is supplied to the address electrode in the address period of the M (M is a natural number greater than N) first selective erase subfield, the data signal is supplied among the plurality of selective erase subfields of the first frame. The number of selective erasure subfields is preferably greater than the number of selective erasure subfields for supplying a data signal among the plurality of selective erasure subfields of the second frame.

In addition, as described above, the possibility that the erase address discharge may become unstable may be relatively small when the gradation level is relatively large compared to when the gradation level is relatively small.

Therefore, when the gradation level is higher than or equal to the threshold level, it is also possible to generate the erase address discharge by supplying the data signal to the address electrode in the address period only in the first selective erase subfield among the at least one selective erase subfield that is turned off.

For example, as shown in FIGS. 5 to 6, it is possible to supply the data signal to the address electrode in the address period only from the selective erase subfield first turned off from the three to 12 gradation levels. That is, the number of selective erasure subfields that supply data signals among the plurality of selective erasure subfields may be substantially the same in a frame implementing three gray levels and a frame implementing twelve gray levels.

8 to 9 are diagrams for explaining an example of another method of adjusting the number of selective erase subfields for supplying a data signal among a plurality of selective erase subfields.

First, referring to FIG. 8, the number of selective erasing subfields supplying a data signal to an address electrode in an address period among the plurality of selective erasing subfields of a frame is less than half of the total number of the plurality of selective erasing subfields included in the frame. Can be.

For example, one frame is composed of a total of 12 subfields SF1 to SF12, and the first subfield SF1 disposed first in time is an optional write subfield, and the remaining 11 subfields are selective erase subs. In the case of a field, a data signal can be supplied to an address electrode in an address period of up to five selective erase subfields out of eleven selective erase subfields. This case may be the case of a frame implementing one gray level.

If, as in the case of FIG. 9, the data signal is supplied to the address electrodes in the address periods of all the selective erasing subfields to generate the erase address discharge, it is possible to sufficiently prevent the occurrence of the false discharge, but rather due to the supply of unnecessary data signals. Driving efficiency may be lowered.

For example, in the case of a frame implementing one gray level, if the data signal is supplied to the address electrode in the address period of the second, third, fourth, fifth, and sixth subfields, the wall charges can be sufficiently erased in the discharge cells. Since sustain discharge can be sufficiently prevented from occurring after the seventh subfield, unnecessary power waste can be caused if the data signal is supplied to the address electrode in the address period in the seventh to seventh subfields. will be.

As a result, the data signal is not supplied to the address electrode in the address period of all the selective erasing subfields that are turned off in any frame, and at least one of the selective erasing subfields of the plurality of selective erasure subfields that are turned off does not provide a data signal in the address period. Omitting may be more advantageous in terms of driving efficiency. For example, in an arbitrary frame, when the N (N is a natural number) subfield is first turned off, that is, a subfield in which a data signal is supplied to the address electrode in the address period for the first time, the N-th subfield is in time. In this case, the data signal can be omitted in the address period of at least one selective erasure subfield among the at least one selective erasure subfield.

However, in the case of implementing the 11th gradation level as shown in FIG. 8, since the selective erasing subfield that is turned off among the plurality of selective erasing subfields is the twelfth subfield SF12 disposed last in time, This is an exception because it is impossible to omit the data signal in the address period in at least one selective erase subfield of the plurality of selective erase subfields.

10 to 11 are diagrams for describing positions of selective erasing subfields for supplying a data signal among a plurality of selective erasing subfields.

Referring to FIG. 10, a plurality of selective erasing subfields to which a data signal is supplied to an address electrode in an address period among the plurality of selective erasing subfields may be adjacent to each other. Preferably, in any frame, assuming that the N (N is a natural number) th selective erase subfield is first turned off, data is transmitted to the address electrode in the address period of the N + 1 th selective erase subfield adjacent to the N th selective erase subfield. It can supply a signal.

For example, assuming that the first subfield SF1 is an optional write subfield and the remaining subfields are selective erase subfields, as in the case of FIG. 10, a frame that implements one gray level is an optional erase subfield. The data signal may be supplied to the address electrode in the address period of the second, third, and fourth subfields.

In the case where the selective erase subfields to which the data signal is supplied to the address electrode are discontinuously arranged in the address period, for example, in the case of a frame implementing one gray level as shown in FIG. 11, the third subfield as the selective erase subfield. When the data signal is supplied to the address electrode in the address periods of the second, fourth, and fifth subfields without supplying the data signal to the address electrode in the address period of SF3, it occurs in the address period of the second subfield. When the erase address discharge is unstable and an excessively large amount of wall charges are formed in the discharge cell, the sustain discharge occurs in the sustain period of the third subfield, which is continuous with the second subfield and is not supplied with the data signal, thereby improving the image quality of the image. Can get worse.

Therefore, when a data signal is supplied to the address electrode in the address period of the plurality of selective erasing subfields, it is preferable that the plurality of selective erasing subfields to which such data signals are supplied are arranged in succession.

In the above description, only the case where one selective write subfield is included in one frame may be different from the case where a plurality of selective write subfields are included in one frame.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 is a diagram for explaining the configuration of a plasma display device;

2 is a diagram for explaining the structure of a plasma display panel;

FIG. 3 is a diagram for explaining a structure of a frame for implementing gradation of an image. FIG.

4 is a diagram for explaining an example of drive waveforms in a selective write subfield and a selective erase subfield;

5 to 7 illustrate a method of driving a plasma display panel.

8 to 9 are diagrams for explaining an example of another method of adjusting the number of selective erasing subfields for supplying a data signal among a plurality of selective erasing subfields.

10 to 11 are diagrams for explaining positions of a selective erase subfield for supplying a data signal among a plurality of selective erase subfields.

Claims (18)

A plasma display panel including a scan electrode and a sustain electrode, an address electrode intersecting the scan electrode and the sustain electrode, and a discharge cell formed at a point where the scan electrode and the sustain electrode cross the address electrode; Pixel data writing means for causing selective erase discharge to selectively erase charges formed in said discharge cells in accordance with pixel data corresponding to the gray level of an input video signal; And Sustain means for supplying a sustain signal to at least one of the scan electrode and the sustain electrode to sustain discharge in an unerased discharge cell; Including, And the data writing means performs a data writing operation by the selective erasing in at least two subfields of a plurality of subfields according to the pixel data. The method of claim 1, And the data writing means generates a selective write discharge which selectively forms charge in the discharge cells in at least one of the plurality of subfields. The method of claim 2, And the data writing means generates a selective write discharge which selectively forms charge in the discharge cells in the first subfield of the plurality of subfields. The method of claim 1, And the data writing means repeatedly writes data in successive subfields when the pixel data is low gradation. A driving method of a plasma display panel including an scan electrode, a sustain electrode, and an address electrode, and implementing an image in a plurality of frames including a plurality of selective erase subfields. In at least one frame of the plurality of frames, a data signal is supplied to the address electrode in an address period of at least two consecutive subfields of the plurality of selective erasing subfields, and the scan electrode corresponds to a scan corresponding to the data signal. A method of driving a plasma display panel for supplying a signal. The method of claim 5, wherein And the selective erasing subfield is a subfield that turns off a discharge cell supplied with a data signal to the address electrode in the address period in a sustain period after the address period. The method of claim 5, wherein The plurality of frames includes a first frame and a second frame having different gray values, the gray value of the first frame is smaller than the gray value of the second frame, In the first frame, a data signal is supplied to the address electrode in an address period of at least two consecutive subfields among a plurality of selective erasing subfields, and the scan signal is supplied to the scan electrode. And a data signal is supplied to the address electrode in an address period of one subfield among a plurality of selective erasing subfields, and the scan signal is supplied to the scan electrode. The method of claim 5, wherein And the frame includes at least one selective write subfield. The method of claim 8, And the selective write subfield is a first subfield among a plurality of subfields of a frame. The method of claim 8, And wherein the selective write subfield is a subfield that turns off a discharge cell supplied with a data signal to the address electrode in the address period in a sustain period after the address period. A driving method of a plasma display panel including an scan electrode, a sustain electrode, and an address electrode, and implementing an image in a frame including a plurality of selective erase subfields. Supplying a data signal to an address electrode in an address period of an N (N is a natural number) th selective erasing subfield first of a plurality of selective erasing subfields in a first frame (Frame1); Supplying a data signal to the address electrode in an address period of an M (M is a natural number greater than N) first selective erase subfield of a plurality of selective erase subfields in a second frame (Frame2); Including, The number of selective erasing subfields for supplying the data signal among the plurality of selective erasing subfields of the first frame is the number of selective erasing subfields for supplying the data signal among the plurality of selective erasure subfields of the second frame. A method of driving a plasma display panel more than the number. The method of claim 11, And the data signal is supplied to the address electrode in an address period of the Nth subfield and the N + 1th subfield in the first frame. The method of claim 11, The third frame (Frame3) further comprises the step of supplying a data signal to the address electrode in the address period of the first P (P is a natural number greater than M) th selective erase subfield of the plurality of selective erase subfield, The number of selective erasing subfields for supplying the data signal among the plurality of selective erasing subfields of the second frame may include the number of selective erasing subfields for supplying the data signal among the plurality of selective erasure subfields of the third frame. A method of driving a plasma display panel equal to the number. The method of claim 11, And the selective erasing subfield is a subfield that turns off a discharge cell supplied with a data signal to the address electrode in the address period in a sustain period after the address period. The method of claim 11, And in the first frame, omitting the data signal in the address period of at least one selective erasure subfield among at least one selective erasure subfield disposed later in time than the Nth subfield. Driving method. The method of claim 11, The number of selective erasing subfields supplying the data signal among the plurality of subfields of the first and second frames is less than half of the total number of the plurality of selective erasing subfields included in the first and second frames. Driving method. A plasma display including an scan electrode, a sustain electrode, and an address electrode, and implementing an image in a frame including at least one selective write subfield and a plurality of selective erase subfields. In the driving method of the panel, Placing the plurality of selective erasing subfields later in time than the selective writing subfield; Supplying a data signal to an address electrode in an address period of an N (N is a natural number) th selective erasing subfield first of a plurality of selective erasing subfields in a first frame (Frame1); And Supplying a data signal to the address electrode in an address period of an M (M is a natural number greater than N) first selective erase subfield of a plurality of selective erase subfields in a second frame (Frame2); Including, The number of selective erasing subfields for supplying the data signal among the plurality of selective erasing subfields of the first frame is the number of selective erasing subfields for supplying the data signal among the plurality of selective erasure subfields of the second frame. A method of driving a plasma display panel more than the number. The method of claim 17, The selective erasing subfield is a subfield that turns off a discharge cell supplied with the data signal to the address electrode in the address period in a sustain period after the address period, And wherein the selective write subfield is a subfield that turns on a discharge cell supplied with the data signal to the address electrode in the address period in a sustain period after the address period.

Images