KR100804534B1 - Apparatus for driving discharge display panel wherein ram is effeciently used - Google Patents

Abstract

An apparatus for driving a discharge display panel using a RAM is provided to minimize time loss due to the stop of write operation by using the latest address used for a writing operation. A discharge display panel includes a RAM(Random Access Memory) for storing the sub-field data of at least two frames to execute reading and writing operations. The reading operation on a unit scan electrode line of the discharge display panel is separated into a read active time(t2-t3) and a read wait time(t3-t4). The writing operation(WR) on the unit scan electrode line is executed during the read wait time. An address used in the latest writing operation is stored at the start of the read active time. When a reading operation(RD) on the unit scan electrode line is terminated, a writing operation is started from the stored address.

Description

Apparatus for driving discharge display panel where RAM is effeciently used}

1 is an internal perspective view showing the structure of a plasma display panel of a three-electrode surface discharge method that is a driving target of the driving apparatus of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a unit display cell of the panel of FIG. 1.

3 is a timing diagram illustrating an address-display separation driving method for Y electrode-lines of the plasma display panel of FIG. 1.

4 is a block diagram illustrating an apparatus for driving a plasma display panel according to the present invention.

5 is a timing diagram illustrating driving signals applied to the panel of FIG. 1 in the unit sub-field of FIG. 3 by the driving apparatus of FIG. 4.

6 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t2 of FIG. 5.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t3 of FIG. 5.

8 is a block diagram illustrating an internal configuration of a logic controller in the driving device of FIG. 4.

FIG. 9 is a diagram schematically illustrating frame data input to a subfield matrix unit of FIG. 8.

FIG. 10 is a diagram schematically illustrating frame data output from the subfield matrix unit of FIG. 8.

FIG. 11 is a block diagram illustrating an internal configuration of a matrix buffer unit of FIG. 8.

FIG. 12 is a block diagram illustrating a storage structure of a RAM of FIG. 8.

FIG. 13 is a timing diagram illustrating a read operation and a write operation of the memory controller of FIG. 8.

FIG. 14 is a flowchart illustrating a control algorithm of the memory controller of FIG. 8 in a read period set for a unit scan electrode line.

FIG. 15 is a block diagram illustrating an internal configuration of an address driver in the driving apparatus of FIG. 4.

FIG. 16 is a block diagram illustrating signals input to the address driver of FIG. 14 from the controller of FIG. 4.

FIG. 17 is a timing diagram illustrating that address signals are input to the driving elements by the chip-enabled signals of FIG. 16.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., X _n ... X electrode-line, Y ₁ , ..., Y _n ... Y electrode-line,

A _R1 , ..., A _Bm ... address electrode-line, X _na , Y _na ... transparent electrode-line,

X _nb , Y _nb ... metal electrode-line,

SF1, ... SF8, SF ₁ , ... SF ₈ ... sub-field,

42 logic controller, 43 address drive,

44 ... X drive, 45 ... Y drive,

41 ... image processing unit, 89 ... RAM.

The present invention relates to a driving device of a discharge display panel, and more particularly, to a driving device of a discharge display panel having a random access memory (RAM) for storing data of at least two frames for read and write operations. It is about.

In a typical discharge display device, for example, the plasma display device of US Pat. No. 5,541,618, a unit frame is divided into a plurality of subfields for time division gray scale display, and each of the subfields is a reset period, an addressing period, and a sustain period. It includes. Each of the subfields has a unique gray scale weight value, and a maintenance period is set in proportion to the gray scale weight value.

In the above discharge display apparatus, a random access memory (RAM) for storing data of at least two frames is required for a read operation and a write operation. However, a single RAM cannot simultaneously perform read and write operations. Therefore, even if only two frames of data are stored to reduce the number of RAMs, two RAMs are required.

An object of the present invention is to provide a driving device of a discharge display panel which can reduce the number of RAM by using RAM efficiently.

The driving device of the discharge display panel of the present invention for achieving the above object is a driving device of the discharge display panel having a RAM (Random Access Memory) for storing the sub-field data of at least two frames for the read operation and the write operation.

The read period set for the unit scan electrode line of the discharge display panel is divided into a read operation time and a read standby time. Here, a write operation on the unit scan electrode line is performed at the read-wait time. At the start of the read-operation time, the most recently used address for the write operation is stored. When the read operation on the unit scan electrode line is completed, the write operation is performed from the stored address.

According to the driving device of the discharge display panel of the present invention, since the write operation is performed on the unit scan electrode line in the read-wait time, data of two frames may be stored in one RAM. . Accordingly, the number of RAMs required can be reduced efficiently. In addition, when the read-operation time reaches the start time, since the address used as the most recent write operation is stored and used, time loss due to disconnection of the write operation may be minimized.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

1 shows the structure of a plasma display panel 1 of a three-electrode surface discharge method that is a driving target of the driving apparatus of the present invention. FIG. 2 shows the configuration of a unit display-cell of panel 1 of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of the surface discharge plasma display panel 1, address electrode-lines A _R1 ,..., A _Bm , a dielectric layer ( 11, 15), Y electrode-lines Y ₁ , ..., Y _n as scan electrode-lines, X electrode-lines X ₁ , ..., X _n as sustain electrode-lines The phosphor 16, the partition 17, and the magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied over the entire surface in front of the address electrode lines A _R1 , ..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., A _Bm . These partitions 17 function to partition the discharge area of each cell and to prevent optical cross talk between each cell. The phosphor 16 is applied between the partition walls 17.

The X electrode-lines X ₁ , ..., X _n and the Y electrode-lines Y ₁ , ..., Y _n are address electrode-lines A _R1 , ..., A _Bm It is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to the. Each intersection sets a corresponding cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode-lines made of a transparent conductive material such as indium tin oxide (ITO). (X _na , Y _{na in} FIG. 2) and a metal electrode line (X _nb , Y _{nb in} FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the back of the X electrode lines X ₁ ,..., And X _n and the Y electrode lines Y ₁ ,..., And Y _n . . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

FIG. 3 illustrates an address-display separation driving method for Y electrode-lines of the plasma display panel of FIG. 1. Referring to FIG. 3, each of the unit frames is divided into eight subfields SF1,..., SF8 to realize time division gray scale display. In addition, each subfield SF1, ..., SF8 has reset periods I1, ..., I8, address periods A1, ..., A8, and sustain periods S1, ..., S8. Is divided into

The discharge conditions of all the display cells become uniform in each reset period I1, ..., I8.

Each of the address periods (A1, ..., A8) in the address electrode lines (Fig. 1 A _R1, ..., A _Bm) as soon applied to the display data signals at the same time, the Y electrode in-line (Y _1, ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by address discharge in the corresponding display cell, and wall charges are not formed in the other display cell.

In each sustain period S1, ..., S8, all Y electrode-lines Y ₁ , ..., Y _n and all X electrode-lines X ₁ , ..., X _n The holding pulses are alternately applied, causing display discharge in display cells in which wall charges are formed in corresponding address periods A1, ..., A8. Therefore, the luminance of the plasma display panel is proportional to the length of the sustain periods S1, ..., S8 occupied in the unit frame. The lengths of the sustain periods S1, ..., S8 occupy a unit frame are 255T (T is unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the sustain period S1 of the first subfield SF1 and the time 2T corresponding to 2 ¹ in the sustain period S2 of the second subfield SF2. Is a time 4T corresponding to 2 ² in the sustain period S3 of the third subfield SF3, and a time 8T corresponding to 2 ³ in the sustain period S4 of the fourth subfield SF4. Is a time 16T corresponding to 2 ⁴ in the sustain period S5 of the fifth subfield SF5, and a time 32T corresponding to 2 ⁵ in the sustain period S6 of the sixth subfield SF6. ) Is a time 64T corresponding to 2 ⁶ in the sustain period S7 of the seventh subfield SF7, and a time (2) corresponds to 2 ⁷ in the sustain period S8 of the eighth subfield SF8. 128T) are set respectively.

Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

Referring to FIG. 4, the driving apparatus of the plasma display panel 1 according to the present invention includes an image processor 41, a logic controller 42, an address driver 43, an X driver 44, and a Y driver 45. It includes.

The image processing unit 41 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals.

The logic controller 42 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 41.

The address driver 43 generates display data signals according to the address signals S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 42, and generates the generated display data signals. Are applied to address electrode-lines (A _R1 ,..., A _Bm in FIG. 1).

The X driver 44 has the X driving control signal from the driving control signal from the logic controller (42) (S _A, S _Y, S _X) maintained in accordance with the (S _X) electrode - of as line X electrode lines (X ₁ , ..., X _{n in} FIG. ₁ ) is driven.

The Y driver 45 is Y electrode-lines as scan electrode-lines according to the Y drive control signals S _Y among the drive control signals S _A , S _Y , and S _X from the logic controller 42. (Y ₁ , ..., Y _{n in} FIG. ₁ ) is driven.

FIG. 5 shows driving signals applied to the panel 1 of FIG. 1 in the unit sub-field SF by the driving device of FIG. 4. In FIG. 5, S _{AR1 .. ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 , ..., A _Gm , A _Bm of FIG. 1), and S _{X1 .. Xn} is X electrode driving signals applied to the lines (Fig. ₁ X 1, the ... X _{n), Y1} and s, ..., s are the Y electrodes _Yn-line (Figure ₁ Y 1, ... a Y _n ) indicates a drive signal applied to the device. FIG. 6 illustrates a wall charge distribution of one display cell at a time point t2 immediately after a gradual rising potential is applied to the Y electrode lines Y ₁ ,... Y _n in the reset period I of FIG. 5. Shows. FIG. 7 illustrates a wall charge distribution of one display cell at a time point t3, which is the end point of the reset period I of FIG. 5. 6 and 7 the same reference numerals as used in FIG. 2 indicate the object of the same function.

Referring to FIG. 5, in the rising period t1 to t2 in the reset period I of the unit sub-field SF, the potential applied to the Y electrode lines Y ₁ ,..., Y _n . is, for a second potential (V _S), for example, the third potential (V _SET) as the higher the first potential (V _SET + V _S) than the second electrical potential (V _S) from 155 volt (V) for example, Continuously rising to 355 volts (V). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 , ..., A _Bm . Accordingly, continuous discharge occurs between the Y electrode lines (Y ₁ , ..., Y _n ) and the X electrode lines (X ₁ , ..., X _n ), while the Y electrode lines ( Y ₁ ,..., Y _n ) and a continuous discharge also occur between the address electrode-lines A _R1 , ..., A _Bm . Accordingly, Y electrode lines _{(Y 1, ..., Y n} ) is surrounded portion is formed to the polarity of wall charges, X electrode lines _{(X 1, ..., X n} ) is surrounded by positive wall Charges are formed, and positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 6).

Next, in the falling period t2 to t3 in the reset period I, the potential applied to the X electrode-lines X ₁ ,..., X _n is lower than the second potential V _S. In the state held at 4 potential V _E , the potential applied to the Y electrode-lines Y ₁ ,..., Y _n is continuously maintained _from the second potential V _{S to the} ground potential V _G. Descends. Here, the ground potential V _G is applied to the address electrode lines A _R1 , ..., A _Bm . Accordingly, due to the gradual discharge between the X electrode-lines (X ₁ ,..., X _n ) and the Y electrode-lines (Y ₁ , ..., Y _n ), the Y electrode-lines (Y) Some of the negative wall charges around ₁ , ..., Y _{n move} around the X electrode-lines X ₁ , ..., X _n (see FIG. 7). Also, positive wall charges are maintained around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

Accordingly, in a subsequent addressing period A, the display data signal is applied to the address electrode lines A _R1 ,..., A _Bm , and the fifth potential V _SCAN lower than the second potential V _S. As a scan signal of the ground potential V _G is sequentially applied to the Y electrode-lines Y ₁ ,..., Y _n biased by), smooth addressing may be performed. The display data signal applied to each address electrode line A _R1 , ..., A _Bm has a positive address potential V _A when the display cell is selected, and a ground potential V _G when the display cell is not selected. Is approved. Accordingly, when the display data signal of the positive address potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges for sustain discharge are formed by the address discharge in the corresponding display cell. In the other display cells, wall charges for sustain discharge are not formed. Here, for a more accurate and efficient address discharge, the fourth potential V _E is applied to the X electrode lines X ₁ , ... X _n .

In the following sustaining period S, the maintenance of the second potential V _{S at} all the Y electrode-lines Y ₁ , ... Y _n and the X electrode-lines X ₁ , ... X _n . The pulses are alternately applied, causing sustain discharge in the display cells in which wall charges for sustain discharge were formed in the corresponding address period A. FIG.

Referring to FIG. 8, the logic controller 42 of the driving apparatus of FIG. 4 includes a clock buffer 85, a synchronization controller 826, a gamma correction unit 81, an error diffusion unit 812, and first-in-first-out (First-First). In First-Out Memory 811, Subfield Generator 821, Subfield Matrix 822, Matrix Buffer 823, Memory Control 824, Random Access Memory 89, Rearranger 825, average signal level detector 83a, power controller 83, E.P.ROM (EEPROM) 84a, I ² C serial communication interface 84b, timing-signal generator 84c, and An XY control unit 84 is included.

The clock buffer 85 converts the 26-megahertz (MHz) clock signal CLK26 from the image processor 41 of FIG. 5 into a 40-megahertz (MHz) clock signal CLK40 and outputs the converted signal. The synchronization adjustment unit 826 includes a clock signal CLK40 of 40 mega-hertz (MHz) from the clock buffer 85, an initialization signal RS from the outside, and a horizontal synchronization signal from the image processing unit (41 in FIG. 4). A call H _SYNC and a vertical sync signal V _SYNC are input. The synchronization adjusting unit 826 outputs the horizontal synchronization signals H _SYNC1 , H _SYNC2 , and H _SYNC3 to which the input horizontal synchronization signal H _SYNC is delayed by a predetermined number of clocks, respectively. V _SYNC ) outputs vertical synchronization signals V _SYNC2 and V _SYNC3 delayed by a predetermined number of clocks, respectively.

The image data R, G, and B input to the gamma correction unit 81 has a reverse nonlinear input / output characteristic in order to correct the nonlinear input / output characteristics of the cathode ray tube. Therefore, the gamma correction unit 81 processes the image data R, G, and B of the reverse nonlinear input and output characteristics to have a linear input and output characteristic. The error diffusion unit 812 uses the first-in, first-out memory 811 to move the position of the most significant bit, which is the boundary bit of the 12-bit format image data R, G, and B, and the image of the 8-bit format. Generate data (R, G, B).

The subfield generator 821 converts 8-bit image data R, G, and B into 8-bit image data R, G, and B, respectively, corresponding to the number of subfields. For example, when grayscale driving is performed with 14 subfields in a unit frame, after converting 8-bit image data R, G, and B into 14-bit image data R, G and B, respectively, In order to reduce a data transmission error, 16 bits of image data R, G, and B are output by adding invalid data '0' of a maximum value bit (MSB) and a minimum value bit (Least Significant Bit).

The subfield matrix unit 822 rearranges 16-bit video data R, G, and B into which data of different subfields is simultaneously input, so that data of the same subfield is simultaneously output. The matrix buffer unit 823 processes the 16-bit image data R, G, and B from the subfield matrix unit 822 and outputs the 32-bit image data (R, G, B).

The memory controller 824 stores subfield data of at least two frames in one RAM 89 for read and write operations. Accordingly, the number of RAMs required can be reduced efficiently. The read and write operations will be described in detail with reference to FIGS. 12 and 13.

In FIG. 8, the reference sign EN indicates an enable signal generated from the XY controller 64 and input to the memory controller 824 to inform the memory controller 824 of the write operation time. In addition, the reference numeral S _STB is generated from the XY control unit 84 to inform the memory control unit 824 of the read operation time and to control data input / output in the rearrangement unit 825, and the memory control unit 824 and the rearrangement unit. The address-strobe signal input to 825 is indicated. The rearrangement unit 825 rearranges and outputs 32-bit image data R, G, and B from the memory control unit 824 according to the input format (see FIG. 13) of the address driver 53 (FIG. 5).

Meanwhile, the average gray scale detector 83a detects the average gray scale ASL in units of frames from the 8-bit image data R, G, and B from the error diffusion unit 812, and inputs the average gray scale ASL to the power controller 83. . The power control unit 83 sets the number of sustain pulses in each of the sustain periods so as to be inversely proportional to the average gray level ASL of each frame while being proportional to the gray scale weight value assigned to each subfield.

E. P. ROM (EEPROM) 84a has X electrode lines (X _{1 in} FIG. 1). To X _n ) and the Y electrode lines (Y ₁ of FIG. 1). To Y _n ), the timing control data according to the drive sequence are stored.

The discharge count data N _S from the power control unit 83 and the timing control data from the E.P.ROM 64A are transmitted through the I ² C serial communication interface 64b to generate the timing-signal generator 84c. ) Is entered. The timing-signal generator 84c operates according to the input discharge count data N _S and the timing control data to generate the timing-signal. The XY control unit 84 operates in accordance with the timing-signal from the timing-signal generator 84c to output the X driving control signal S _X and the Y driving control signal S _Y.

9 briefly illustrates frame data input to the subfield matrix unit 822 of FIG. 8. Referring to FIG. 9, each of 16-bit image data R, G, and B input to the subfield matrix unit 822 has a structure in which data of different subfields is simultaneously input.

FIG. 10 briefly illustrates frame data output from the subfield matrix unit 822 of FIG. 8. Referring to FIG. 10, each of 16-bit image data R, G, and B output from the subfield matrix unit 822 has a structure in which data of the same subfield is simultaneously input.

FIG. 11 illustrates an internal configuration of the matrix buffer unit 823 of FIG. 8. Referring to FIG. 11, the matrix buffer part 823 includes a red delay element 11R, a green delay element 11G, and a blue delay element 11B. The red delay element 11R delays the 16-bit red image data R input from the subfield matrix unit 822 of FIG. 8 by the input period of the 16 clock pulses to the positions of the first to 16th bits. Output Meanwhile, the 16-bit red image data R input from the subfield matrix unit 822 is directly output to the positions of the 17th to 32nd bits. Accordingly, the 16-bit red image data R from the subfield matrix unit 822 is output as the 32-bit red image data R. FIG. The same applies to the green and blue image data G and B. Here, the same reset signal RS, clock signal CLK40, second vertical synchronization signal V _SYNC2 , and second horizontal synchronization signal H _SYNC2 are input to each of the delay elements 11R, 11G, and 11B. .

12 illustrates a storage structure of the RAM 89 of FIG. 8.

Referring to FIG. 12, the Synchronous Dynamic RAM 89 of FIG. 8 includes four banks BA1 to BA4. These banks BA1 to BA4 have the same double data rate (DDR) structure. The sum of the capacities of the four banks BA1 to BA4 is about 134 mega bits, and two frames of subfield data are stored in a capacity of 128 mega bits. That is, the subfield data of the N + 1th frame is written while the subfield data of the Nth frame is read.

When one frame is configured with eight subfields, the first bank BA1 includes data of the first and second subfields (SF1 and SF2 of FIG. 3) and the N + 1 th frame of the Nth frame. Data of the first and second subfields (SF1 and SF2 of FIG. 3) are stored. The second bank (not shown) includes data of the third and fourth subfields (SF3 and SF4 of FIG. 3) of the Nth frame and third and fourth subfields of the N + 1th frame of FIG. 3. Data of SF3, SF4) is stored. The third bank (not shown) includes data of fifth and sixth subfields (SF5 and SF6 of FIG. 3) of the Nth frame and fifth and sixth subfields of the N + 1th frame of FIG. 3. Data of SF5, SF6) is stored. In the fourth bank BA4, data of the seventh and eighth subfields (SF7 and SF8 of FIG. 3) of the Nth frame and the seventh and eighth subfields of the N + 1th frame (SF1 of FIG. 3) The data of SF2) is stored.

An efficient storage structure that allows a large amount of data to be stored as described above is described in detail.

As a double data rate (DDR) structure, 32 bits of subfield data are stored in an area corresponding to one row address and one column address of the SDRAM 89. I (i is a natural number from 1 to n, n is the number of Y electrode-lines as scan electrode-lines) of the plasma display panel (1 in FIG. 1). Subfields corresponding to respective display cells of the Y electrode-lines Data is stored in an area of three rows of SDRAM 89. Here, for each of pairs (Y ₁ Y ₂ ,..., Y _{n -1} Y _n ) of odd-numbered scan electrode-lines and even-numbered Y electrode-lines, one row of RAM Subfield data of each of the odd-numbered scan electrode-line and the even-numbered scan electrode-line in the area of (Row) are stored together.

For example, in an area of one row in which the subfield data of the last display cell of the odd-numbered Y electrode-line is stored, the subfield data of the first display cell of the even-numbered Y electrode-line is stored together.

Here, a column of an area in which the subfield data of the last display cell of the odd-numbered Y electrode-line is stored, and a column of an area in which the subfield data of the first display cell of the even-numbered Y electrode-line is stored ( As there is a blank area between columns, data identification between Y electrode-lines is facilitated.

In this embodiment, odd rows are allocated to each of the pairs of odd-numbered Y electrode-lines and even-numbered Y electrode-lines adjacent to each other, and among the odd-numbered rows, a middle row. Subfield data of each of the odd-numbered Y electrode-line and the even-numbered Y electrode-line are stored together in the region of.

According to the above-described storage structure, the subfield data of the even-numbered scan electrode-line is not limited to being stored only in the subfield data of the odd-numbered scan electrode-line in the region of one row of the SDRAM SDRAM. Field data is also stored. As a result, the number of rows required for the SDRAM 89 can be efficiently reduced, thereby reducing the number of RAMs required.

FIG. 13 illustrates a read operation and a write operation of the memory controller 824 of FIG. 8. In FIG. 13, the same reference numerals as used in FIGS. 3 and 8 indicate the objects of the same function. In FIG. 13, reference numeral M _D denotes an operation mode of the memory controller 824, RD denotes a read operation, and WR denotes a write operation. A read operation and a write operation of the memory controller 824 of FIG. 8 will be described with reference to FIGS. 3, 8, 12, and 13 as follows.

The unit frame is divided into eight subfields SF1 through SF8. In each of the subfields SF1 to SF8, the Y electrode lines as the scan electrode lines (Y _{1 in} FIG. 1). To Y _n ), a read operation RD and a write operation WR are performed.

As described above, the reference symbol S _STB is generated from the XY control unit 84 to inform the memory control unit 824 of the read operation time and to control data input / output in the rearrangement unit 825. And an address-strobe signal input to the rearrangement unit 825. The time when the address-strobe (S _STB ) signal is logic '1' is the read-operation time, and the time when logic '0' is the read-wait time. Thus, for example, the read period set for the unit Y electrode-line, T _L1 is separated into a read-operation time t2 to t3 and a read-standby time t3 to t4.

As described above, the reference sign EN indicates an enable signal generated from the XY control unit 64 and input to the memory control unit 824 to inform the memory control unit 824 of the write operation time. The time when the enable signal EN is logic '1' is the write-operation time and the time the logic '0' is the write-wait time. However, in order to prevent data collision between the memory controller 824 and the SDRAM 89, all of the time when the enable signal EN is a logic '1' should not be a write-operation time. . Therefore, the write operation is performed on the unit Y electrode line, for example, the first Y electrode line Y ₁ , only at the read-wait time t3 to t4.

Accordingly, since two frames of data may be stored in one RAM 89, the number of RAMs required may be efficiently reduced.

Referring to FIGS. 13 and 14, a control algorithm of the memory control unit 824 of FIG. 8 in a read period T _L1 set for a unit scan electrode line, for example, the first Y electrode line Y ₁ of FIG. 1. This is as follows.

First, the memory controller 824 determines whether the address-strobe signal S _STB is in a logic '1' state (step S1).

If the address-strobe signal S _STB is in a logic '1' state, the memory controller 824 reads the subfield data of the current frame of the unit scan electrode line, for example, the first Y electrode line Y ₁ . The operation is performed (step S2).

If the address-strobe signal S _STB is not in a logic '1' state, that is, in a state of logic '0', the memory controller 824 determines that the enable signal EN of the data is a logic '1'. It is determined whether or not the state is (S5).

When the enable signal EN of the data is in a logic '1' state, the memory controller 824 may determine the unit field of the sub-field data of the next frame of the unit scan electrode line, for example, the first Y electrode line Y ₁ . A write operation is performed (step S6).

When the address-strobe signal S _STB acting preferentially as an interrupt signal during the write operation of the subfield data (step S6) becomes a logic '1' (step S7), the memory controller 824 ) Stops the write operation and stores the write-interrupt address as the address which was most recently used in the write operation (step S9). For example, the write-stop address that was used most recently in the write operation is stored in either register in the memory controller 824. That is, when the start time of the read-operation time is reached, the most recently used address for the write operation is stored.

If all of the subfield data of the unit scan electrode-line, for example, the first Y electrode line Y ₁ has been read (step S3) by the reading step S2, the memory controller 824 enables the data. ) Signal EN is determined to be in a logic '1' state (step S4).

If the enable signal EN of the data is in a logic '1' state, the memory controller 824 calls the stored write-stop address (step S10), and then a unit scan electrode-line example. For example, it is determined whether all the subfield data of the next frame of the first Y electrode line Y ₁ has been written (step S8).

If all the subfield data of the next frame of the unit scan electrode line, for example, the first Y electrode line Y ₁ is not written by the writing step S6 (step S8), the memory control unit 824 The write operation is performed from the stored address (step S6). That is, when the read operation on the unit scan electrode line is completed, the write operation is performed from the stored address.

If all the subfield data of the next frame of the first Y electrode line Y ₁ have been written by the writing step S6 (step S8), the unit scanning electrode line of the unit scan electrode line, for example, The read and write operations of the memory controller 824 with respect to the first Y electrode line (Y _{1 in} FIG. 1) are terminated.

Therefore, according to the control algorithm of the memory control unit 824 as shown in Fig. 14, when the read-operation time reaches the start time, the address used as the most recent write operation is stored and used. Time loss can be minimized.

FIG. 15 illustrates an internal configuration of the address driver 43 in the driving device of FIG. 4. FIG. 16 illustrates signals input from the controller 42 of FIG. 4 to the address driver 43 of FIG. 14. FIG. 17 shows that the address signals are input to the driving elements by each of the chip-enabled signals CE _ODD and CE _{EVEN of} FIG. 16.

15 to 17, in the driving apparatus of FIG. 4, the address driver 43 includes buffer units BF1 to BF3 and driving elements TP1 to TP22.

The address signals D _A from the control unit 42 of FIG. 4 are directly input to the driving elements TP1 to TP22 together with the clock signal CLK. Here, the address signal D _A from the control unit 42 with respect to any of the odd-numbered driving elements (for example, TP1) and the next even-numbered driving element (for example, TP2) of the address driver 43. ) Lines are commonly connected.

The odd-numbered chip-enable signal CE _ODD from the controller 42 is input to the odd-numbered driving elements TP1, TP3,..., TP21 through the buffer units BF1 to BF3. The even-numbered chip enable signal CE _EVEN from the controller 42 is input to the even-numbered driving elements TP2, TP4,..., And TP22 through the buffer units BF1 to BF3.

Here, while the odd chip-enable signal CE _ODD is in a logic '1' state, the address signal D _{A is} connected to the odd-numbered driving elements TP1, TP3,..., TP21 through 6-bit common lines. ) Is entered. In addition, while the even-numbered chip-enable signal CE _EVEN is in a logic '1' state, the address signal D _A is even-numbered driving elements TP2, TP4,..., TP22 through 6-bit common lines. (See Fig. 15). Accordingly, the number of lines of the address signal D _A connected between the driving elements TP1 to TP22 from the controller 42 may be reduced by half.

As described above, according to the driving apparatus of the discharge display panel according to the present invention, since a write operation is performed on the unit scan electrode line in the read-standby time, data of two frames is stored in one RAM. Can be stored. Accordingly, the number of RAMs required can be reduced efficiently. In addition, when the read-operation time starts, the address used as the most recent write operation is stored and used, so that time loss due to disconnection of the write operation can be minimized.

In addition, not only the subfield data of the odd-numbered scan electrode-line is stored in the area of any row of the RAM, but also the subfield data of the even-numbered scan electrode-line is stored together. As a result, the number of rows required for the RAM can be efficiently reduced, so that the number of required RAMs can be reduced.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (11)

A driving apparatus of a discharge display panel having a random access memory (RAM) for storing subfield data of at least two frames for a read operation and a write operation, The read period set for the unit scan electrode line of the discharge display panel is divided into a read-operation time and a read-standby time, At the read-wait time, a write operation is performed on the unit scan electrode line. When the start time of the read-operation time comes, the most recently used address for the write operation is stored. And a write operation is performed from the stored address when the read operation on the unit scan electrode line is completed. The method of claim 1, And the start signal of the read-operation time preferentially acts as an interrupt signal. The method of claim 1, A plurality of bits of subfield data are stored in an area corresponding to one row address and one column address of the RAM. The i th (i is a natural number from 1 to n, n is the number of scan electrode lines) of the discharge display panel, and the subfield data corresponding to each display cell of the scan electrode line is arranged in a plurality of rows of the RAM. Stored in the area of Rows, For each of the pairs of odd-numbered scan electrode-line and even-numbered scan electrode-line adjacent to each other, the odd-numbered scan electrode-line and the even-numbered scan electrode- in the region of any row of the RAM An apparatus for driving a discharge display panel in which subfield data of each line is stored together. The method of claim 3, Discharge display in which subfield data of the first display cell of the even-numbered scan electrode-line is stored together in an area of the row in which the subfield data of the last display cell of the odd-numbered scan electrode-line is stored. The drive unit of the panel. The method of claim 4, wherein Column of an area in which subfield data of the last display cell of the odd-numbered scan electrode-line is stored, and Column of an area in which subfield data of the first display cell of the even-numbered scan electrode-line is stored. A drive device for a discharge display panel having a blank area therebetween. The method of claim 5, An odd number of rows is assigned to each of the pairs of odd-numbered scan electrode-lines and even-numbered scan electrode-lines adjacent to each other, and the odd number in the region of the middle row among the odd-numbered rows. And a subfield data of each of the first scan electrode line and the even scan line. The method of claim 6, And 32-bit subfield data is stored in an area corresponding to one row address and one column address of the RAM. The method of claim 1, And a RAM (Synchronous Dynamic RAM). The method of claim 1, wherein in the discharge display panel, Of the discharge display panel in which X electrode-lines and Y electrode-lines as the scan electrode-lines form XY electrode-line pairs, and address electrode-lines are arranged in a direction crossing the XY electrode-line pairs. drive. A controller configured to generate driving control signals according to an input image signal; An address driver which processes an address signal from the controller to generate a display data signal, and applies the generated display data signal to address electrode lines; An X driver which operates in accordance with an X drive control signal from the controller to drive X electrode lines as sustain electrode lines; And A driving apparatus of a discharge display panel including a driving unit operating in response to a Y driving control signal from the control unit to drive Y electrode lines as scan electrode lines. The control unit includes a random access memory (RAM) for storing subfield data of at least two frames for read and write operations, The read period set for the unit scan electrode line of the discharge display panel is divided into a read operation time and a read standby time. At the read-wait time, a write operation is performed on the unit scan electrode line. When the start time of the read-operation time comes, the most recently used address for the write operation is stored. And a write operation is performed from the stored address when the read operation on the unit scan electrode line is completed. The method of claim 10, The apparatus may further include an image processor configured to convert an external analog image signal into a digital signal to generate an internal image signal. And a control unit to generate driving control signals according to an internal image signal from the image processing unit.

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