KR100581881B1 - Control logic device for plasma display apparatus comprising frame memories - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic control apparatus for a plasma display panel having a frame memory, comprising: an address period in which wall charges are formed in cells to perform display discharge, and a sustain pulse alternately applied to all cells, thereby applying a wall in the address period. A logic controller for a plasma display panel in which a sustain-discharge period in which display discharge occurs in cells in which charges are formed forms a unit sub-field, and a combination of unit sub-fields form a unit frame, wherein a single red frame- A memory, a single green frame-memory, and a single blue frame-memory inside the logic controller, each of the single frame-memory being a write operation and a read operation on a frame. Characterized in that the operation is performed at the same time.

Description

TECHNICAL FIELD [0001] Control logic device for plasma display apparatus comprising frame memories}

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating a configuration of a unit cell of the panel of FIG. 1.

FIG. 3 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a typical Address-While-Display driving method for Y electrode lines of the plasma display panel of FIG. 1.

FIG. 5 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 6 is a block diagram illustrating an internal configuration of a conventional logic control device of the driving device of FIG. 5.

7 is a block diagram showing an internal configuration of a logic control device according to the present invention.

FIG. 8A illustrates frame data input to a subfield matrix unit in the logic controller of FIG. 7.

FIG. 8B is a diagram illustrating frame data output from a subfield matrix unit in the logic controller of FIG. 7.

9 is a block diagram illustrating an internal configuration of a matrix buffer unit in the logic controller of FIG. 7.

10 is a memory map of a frame memory included in the logic controller.

11 is a memory map of a single frame memory having a first compartment and a second compartment.

FIG. 12 is a diagram showing how recording and reading are alternately performed in a single frame memory having a first compartment and a second compartment.

FIG. 13 is a diagram showing how writing and reading are constantly performed in a single frame memory having a first compartment and a second compartment.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line,

SF1, ... SF8, SF ₁ , ... SF ₈ ... sub-field,

52 logic controller, 53 address drive,

54 ... X drive, 55 ... Y drive,

56 image processing unit, 61 gamma correction unit,

611 first-in, first-out memory, 612 error diffusion,

621 subfield generator, 622 subfield matrix,

133 buffer section, 140 memory control section,

150 ... rearrangement,

RFM1, RFM2, RFM3 ... red frame-memory,

GFM1, GFM2, GFM3 ... Green frame-memory,

BFM1, BFM2, BFM3 ... Blue frame-memory,

625, rearrangement, 626, synchronous adjustment,

63a ... average signal level detector, 63 ... power controller,

64a ... EEPROM, 64b ... I ² C serial communication interface,

64c ... timing-signal generator, 64 ... XY controller,

65 ... clock buffer,

The present invention relates to a logic control apparatus for a plasma display panel, and more particularly, to include a frame memory temporarily necessary in order to rearrange the address driving subfield data of the plasma display panel in the logic control apparatus, The present invention relates to a logic control device for a plasma display panel that can be unified to perform efficient memory management.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of a conventional surface discharge plasma display panel 1, address electrode lines A _R1 ,..., A _Bm , a dielectric layer. (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each cell and to prevent optical cross talk between each cell. The phosphor 16 is applied between the partition walls 17.

The X electrode lines X ₁ , ..., X _n and the Y electrode lines Y ₁ , ..., Y _n are orthogonal to the address electrode lines A _R1 , ..., A _Bm . It is formed in a predetermined pattern on the back of the front glass substrate 10. Each intersection sets a corresponding cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

FIG. 3 illustrates a conventional address-display separation driving method for the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 3, a unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Further, each subfield SF1, ..., SF8 is divided into address periods A1, ..., A8 and sustain-discharge periods S1, ..., S8.

In each address period A1, ..., A8, a display data signal is applied to the address electrode lines (A _R1 , ..., A _{Bm in} FIG. 1) and at the same time, each Y electrode line (Y ₁ ,... Scanning pulses corresponding to Y _n ) are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each sustain-discharge period S1, ..., S8, all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n The sustain-discharge pulses are alternately applied, causing display discharge in discharge cells in which wall charges are formed in corresponding address periods A1, ..., A6. Therefore, the luminance of the plasma display panel is proportional to the length of the sustain-discharge periods S1, ..., S8 occupied in the unit frame. The length of the sustain-discharge periods S1, ..., S8 occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the sustain-discharge period S1 of the first subfield SF1 corresponds to 2 ¹ in the sustain-discharge period S2 of the second subfield SF2. Time 2T corresponds to 2 ² in the sustain-discharge period S3 of the third subfield SF3, and ² in the sustain-discharge period S4 of the fourth subfield SF4. ^The time 8T corresponding to ³ corresponds to the time 16T corresponding to 2 ⁴ in the sustain-discharge period S5 of the fifth subfield SF5, and the sustain-discharge period of the sixth subfield SF6. S6) corresponds to the time 32T corresponding to 2 ⁵ , the sustain-discharge period S7 of the seventh subfield SF7 includes the time 64T corresponding to 2 ⁶ , and the eighth subfield SF8. In the sustain-discharge period S8, a time 128T corresponding to 2 ⁷ is set, respectively.

Accordingly, when the subfield to be displayed among the eight subfields is appropriately selected, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

According to the above-described address-display separation driving method, since the time domains of the subfields SF1, ..., SF8 are separated in the unit frame, the address period and the address period in each of the subfields SF1, ..., SF8 are separated. The time domains of the display periods are also separated from each other. Therefore, in the address period, after each XY electrode line pair has been addressed, it has to wait until all other XY electrode line pairs are addressed. As a result, the time period occupied by the address period for each subfield becomes longer and the display period becomes relatively short. Therefore, the luminance of light emitted from the plasma display panel is relatively low. In order to solve this problem, a known method is an address while display driving method as shown in FIG. 4.

FIG. 4 illustrates a typical Address-While-Display driving method for Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, a unit frame is divided into _eight sub-fields SF ₁ , SF ₈ for time division gray scale display. Here, each unit sub-field overlaps each other based on the driven Y electrode lines Y ₁ ,..., And Y _n to form a unit frame. Therefore, since all sub-fields SF ₁ ,..., SF ₈ are present at every time point, an address time slot is set between each display discharge pulse for performing each address step.

Reset, address and display discharge steps are performed in each sub-field, and the time allocated to each sub-field is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) is composed of 255 units of time, driving is performed according to the image data of the least significant bit. The first sub-field SF ₁ is 1 (2 ⁰ ) unit time, the second sub-field SF ₂ is 2 (2 ¹ ) unit time, and the third sub-field SF ₃ is 4 (2). ² ) unit time, the fourth sub-field SF ₄ is 8 (2 ³ ) unit time, the fifth sub-field SF ₅ is 16 (2 ⁴ ) unit time, and the sixth sub-field SF ₆ Is the 32 (2 ⁵ ) unit time, the seventh sub-field SF ₇ is the 64 (2 ⁶ ) unit time, and the eighth sub-field SF ₈ driven according to the image data of the most significant bit. ) Has 128 (2 ⁷ ) unit hours each. That is, since the sum of the unit times allocated to each sub-field is 255 unit times, 255 gray scales can be displayed, and if gray scales without display discharge in any sub-fields are included, 256 gray scales can be displayed.

FIG. 5 shows a typical driving device of the plasma display panel 1 of FIG. 1.

Referring to FIG. 5, a typical driving device of the plasma display panel 1 may include an image processor 56, a logic controller 100, an address driver 53, an X driver 54, and a Y driver 55. Include. The image processing unit 56 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 100 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 56. The address driver 53 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 100 to generate a display data signal, and generates the generated display data. The signal is applied to the address electrode lines. The X driver 54 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the logic controller 100 and applies the X driving control signal S _X to the X electrode lines. The Y driver 55 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 100, and applies the Y driving control signal S _Y to the Y electrode lines.

6 is a block diagram in which an external frame memory is connected to a conventional logic control device 100.

In FIG. 6, R, G, and B 8-bit image data input from the image processor 56 are R, G, and B 8-bit image data among clock, vertical, and horizontal synchronization signals. After the inverse gamma correction and error diffusion at 110, the subfield data generator 120 generates R, G, and B 16-bit subfield data, and the delayed and non-delayed data are stored in the buffer 130. Combined into R, G, and B 32-bit subfield data, the memory control unit 140 converts each of the R 32-bit subfield data, G 32-bit subfield data, and B 32-bit subfield data into frames for each frame. RFM 1, RFM 2, GFM 1, GFM 2, BFM 1, BFM 2).

At this time, for example, the memory controller 140 writes the subfield data of the Nth frame to the first external frame memory RFM 1, and writes the subfield data of the N−1th frame to the second external frame. Read from memory RFM2. Next, the memory controller 140 reads the subfield data of the Nth frame from the first external frame memory RFM 1, and reads the subfield data of the N + 1th frame into the second external frame memory ( Write to RFM 2). Subsequently, the memory controller 140 writes the subfield data of the N + 2th frame into the first external frame memory RFM 1, and writes the subfield data of the N + 1th frame into the second external frame memory ( Read from RFM 2).

As such, the memory controller 140 alternately performs writing and reading operations on the two external frame memories BFM 1 and BFM 2 per unit frame.

By the way, in the conventional logic controller 100, the frame memories RFM 1, RFM 2, GFM 1, GFM 2, BFM 1, and BFM 2 are externally connected and the red, green, and blue subfield data are connected. Each requires two external frame memories. That is, since the memory control unit 140 cannot simultaneously write and read one external frame memory, two memory frames are used as the external frame memory, respectively, in order to simultaneously perform writing and reading. Frame memory (RFM 1, RFM 2, GFM 1, GFM 2, BFM 1, BFM 2) had to be installed.

However, the use of two external frame memories for one subfield data as described above has a problem in that the cost increases due to redundant memory installation and obstructs the miniaturization of the circuit.

Accordingly, an object of the present invention is to reduce the manufacturing cost of the plasma display panel circuit by including the frame memory in the logic control apparatus in the logic control apparatus for plasma display panel.

Another object of the present invention is to reduce the size of the circuit board for the plasma display panel by including the frame memory in the logic control apparatus for the plasma display panel logic control apparatus.

In order to achieve the above object, the present invention provides an address period in which wall charges are formed in cells to perform display discharge, and sustain pulses alternately applied to all cells to maintain display discharge in cells in which wall charges are formed in the address period. A logic control apparatus for a plasma display panel in which a discharge period forms a unit sub-field, and a combination of unit sub-fields forms a unit frame, comprising: a single red frame-memory, a single green frame-memory, And a single blue frame-memory in the logic controller, wherein each of the single frame-memories simultaneously performs a write operation and a read operation on a frame. .

Here, the single frame-memory performs a write operation and a read operation on a single frame, or perform a write operation and a read operation on a plurality of frames.

For example, when a single frame-memory performs a write operation and a read operation on a plurality of frames, the single red frame-memory, a single green frame-memory, and a single blue frame-memory are respectively. A first compartment and a second compartment having the same data space, wherein the frame-memory performing a write operation and a read operation on a plurality of frames is performed in the first and second partitions on a plurality of frames. Perform the operation and the read operation alternately.

For example, when a single frame-memory performs a write operation and a read operation on a plurality of frames, the single red frame-memory, a single green frame-memory, and a single blue frame-memory are respectively. A first partition and a second partition having the same data space, wherein the first partition performs only a write operation, the second partition performs only a read operation, and the frame-memory is divided into a write operation on a plurality of frames. Performing the read operation shifts the image data of the first section in which the recording operation has been performed on the previous frame to the second section, and performs the read operation on the current frame with respect to the image data transferred to the second section. Perform.

Hereinafter, preferred embodiments according to the present invention will be described in detail. 1 to 5 are equally applicable to the present invention.

7 is a block diagram showing an embodiment of a logic control device according to the present invention. Referring to FIG. 7, the logic controller 100 includes a clock buffer 65, a synchronization controller 626, an inverse gamma correction unit 61, an error diffusion unit 612, and first-in first-out. Memory 611, Subfield Generator 621, Subfield Matrix 622, Buffer 130, Memory Controller 140, Frame-Memorys RFM1, ..., BFM3, Rearranger ( 150, average signal level detection unit 63a, power control unit 63, E.P.ROM (EEPROM, 64a), I ² C serial communication interface 64b, timing-signal generator 64c, XY control unit (64).

The clock buffer 75 converts the 26-megahertz (MHz) clock signal CLK26 from the image processing unit 56 of FIG. 5 into a 40-megahertz (MHz) clock signal CLK40. The synchronization adjustment unit 626 includes a 40-megahertz (MHz) clock signal CLK40 from the clock buffer 65, an initialization signal RS from the outside, a horizontal synchronization signal H _SYNC from the image processor, and a vertical line. The synchronization signal V _SYNC is input. The synchronization adjusting unit 626 outputs the horizontal synchronization signals H _SYNC1 , H _SYNC2 , and H _SYNC3 to which the input horizontal synchronization signal H _SYNC is delayed by a predetermined number of clocks, respectively. V _SYNC ) outputs vertical synchronization signals V _SYNC2 and V _SYNC3 delayed by a predetermined number of clocks, respectively.

The image data R, G, and B input to the inverse gamma correction unit 61 have a reverse nonlinear input / output characteristic in order to correct the nonlinear input / output characteristics of the cathode ray tube. Accordingly, the inverse gamma correction unit 61 processes the image data R, G, and B of the reverse nonlinear input and output characteristics to have a linear input and output characteristic. The error diffusion unit 612 reduces the data transmission error by using the first-in, first-out memory 611 to move the position of the maximum sign bit, which is the boundary bit of the image data R, G, and B. FIG.

The subfield generator 621 converts 8-bit image data R, G, and B into 8-bit image data R, G, and B, respectively. For example, when grayscale driving is performed with 14 subfields in a unit frame, after converting 8-bit image data R, G, and B into 14-bit image data R, G and B, respectively, In order to reduce a data transmission error, 16 bits of image data R, G, and B are output by adding invalid data '0' of a maximum value bit (MSB) and a minimum value bit (Least Significant Bit).

The subfield matrix unit 622 rearranges 16-bit video data R, G, and B into which data of different subfields is simultaneously input, so that data of the same subfield is simultaneously output. The buffer unit 130 processes 16-bit image data (R, G, B) from the subfield matrix unit 622 and outputs it as 32-bit image data (R, G, B).

The memory controller 140 may include a red memory controller for controlling two red (R) frame memories (RFM1, RFM2, and RFM3), two green (G) frame-memories (GFM1, GFM2, A green memory controller for controlling GFM3), and a blue memory controller for controlling two blue-frame B- memories BFM1, BFM2, and BFM3. The frame data from the memory controller 140 is continuously output in units of frames and input to the rearrangement unit 150. In FIG. 7, the reference sign EN indicates an enable signal generated from the XY control unit 64 and input to the memory control unit 140 to control the data output of the memory control unit 140. In addition, the reference numeral S _SYNC is generated from the XY control unit 64 to control data input / output in units of 32-bit slots in the memory control unit 140 and the rearrangement unit 150. The slot synchronization signal input to 150 is indicated. The rearrangement unit 150 rearranges and outputs 32-bit image data R, G, and B from the memory control unit 140 so as to conform to the input format of the address driver 53 (FIG. 5).

Meanwhile, the average signal level detector 63a detects an average signal-level ASL in units of frames from the 8-bit image data R, G, and B from the error spreader 612, respectively, and then the power controller 63. To enter. The power control unit 63 generates the discharge frequency control data APC corresponding to the average signal-level ASL input from the average signal level detection unit 63a, thereby making the power consumption constant in each frame constant. Perform the function of control. Here, the load rate means the average load rate of the load rates of each subfield of the frame. The load ratio of each subfield means a ratio of the number of cells to be displayed to the number of all cells of the plasma display panel 1. In the present embodiment, the power control unit 63 performs the automatic power control function when the load ratio of the frame exceeds 30 (%). The E.P.ROM (EEPROM) 64a has X electrode lines (X ₁ , ..., X _n in FIG. 1) and Y electrode lines (Y ₁ , ..., Y _{n in} FIG. 1). Timing control data according to the driving sequence of is stored. The number of discharge control data APC from the power control unit 63 and the timing control data from the E.P.ROM 64A are transmitted through the I ² C serial communication interface 64b to the timing-signal generator 74c. ) Is entered. The timing-signal generator 64c operates according to the input discharge count control data APC and the timing control data to generate a timing-signal.

The XY control unit 64 operates in accordance with the timing-signal from the timing-signal generator 64c to output the X drive control signal S _X and the Y drive control signal S _Y.

FIG. 8A illustrates frame data input to the subfield matrix unit 622 in the logic controller 100 of FIG. 7. Referring to FIG. 8A, each of 16-bit image data R, G, and B input to the subfield matrix unit 622 has a structure in which data of different subfields is simultaneously input. FIG. 8B is a diagram illustrating frame data output from the subfield matrix unit 622 in the logic control apparatus 100 of FIG. 7. Referring to FIG. 8B, each of 16-bit image data R, G, and B output from the subfield matrix unit 622 has a structure in which data of the same subfield is simultaneously input.

9 illustrates an internal configuration of the buffer unit 130 in the logic controller 100 of FIG. 7. Referring to FIG. 9, the buffer unit 130 includes a red delay element 11R, a green delay element 11G, and a blue delay element 11B. The red delay element 11R delays the 16-bit red image data R input from the subfield matrix unit 622 of FIG. 7 by the input time of the 16 clock pulses to the positions of the first to sixteenth bits. Output Meanwhile, the 16-bit red image data R input from the subfield matrix unit 622 is directly output to the positions of the 17th to 32nd bits. Accordingly, the 16-bit red image data R from the subfield matrix unit 622 is output as 32-bit red image data R. FIG. The same applies to the green and blue image data G and B. Here, the same reset signal RS, clock signal CLK40, second vertical synchronization signal V _SYNC2 , and second horizontal synchronization signal H _SYNC2 are input to each of the delay elements 11R, 11G, and 11B.

FIG. 10 illustrates a memory map in which 32-bit red image data R is recorded and read in a frame memory RFM included in the logic controller 100 according to the present invention in a single frame.

In one embodiment, when 16 subfield data are required for a unit frame, the frame memory performs a write operation and a read operation on a single frame. That is, in the Nth frame, the lines L0 to L15 of the frame memory RFM perform a write operation, and at the same time, the lines L0 to other frame memories GFM and BFM of the same structure not shown. The same write operation is performed in L15), and immediately after the write operation of each R, G, B frame memory (RFM, GFM, BFM) in the Nth frame is completed, the 32-bit red image data (R), 32-bit green image The data G and the 32-bit blue image data B are read and sent to the rearrangement unit 150 to be rearranged to match the data signal format required for the address driver 53.

In another embodiment, when 16 subfield data are required for a unit frame, the frame memory performs a write operation and a read operation on a plurality of frames. For example, a single red frame-memory, a single green frame-memory, and a single blue frame-memory each have a first partition (eg, as shown in FIG. 11) having the same data space. Lines L0 to L15) and a second section (e.g., lines L16 to L31), and a recording operation in the first section and the second section on a plurality of frames as shown in FIG. By alternately performing a read operation with each other, recording and reading can be performed for each frame. That is, for example, the subfield data of the Nth frame is written to the first partition, the subfield data of the N-1th frame is read from the second partition, and then, the Nth frame. The subfield data of &quot; Read &quot; from the first partition and the subfield data of the N + 1th frame are written to the second partition. Then, the subfield data of the N + 2th frame is written to the first partition, and the subfield data of the N + 1th frame is read from the second partition.

In another embodiment, when 16 subfield data are required for a unit frame, the frame memory performs a write operation and a read operation while shifting data on a plurality of frames as shown in FIG. For example, a single red frame-memory, a single green frame-memory, and a single blue frame-memory each have the same data space but perform only a write operation and a read operation only. And a second compartment. In the red frame-memory, subfield data are recorded in the first partition on the N-th frame. The same operation is simultaneously performed in the first sections of the green frame-memory and the blue frame-memory. At this time, the subfield data of the N-th frame, which is the previous frame, is read in the second partition. Subfields in which the write operation is performed in the N-1 &lt; th &gt; frame are then shifted to the second partition. Sub-field data of the N-th frame is recorded in the first partition, and the N- 1-th subfield data is read from the second partition and transferred to the rearrangement unit 150. That is, the lines L0 to L15 of the first section of the frame memory RFM in the N-1th frame perform a write operation, and at the same time, the first section of the first section of the other frame memories GFM and BFM. The same write operation is performed on the lines L0 to L15, and after the write operation of each of the R, G and B frame memories (RFM, GFM, BFM) in the N-1th frame is completed, the R, Each of the 32-bit red image data R, 32-bit green image data G, and 32-bit blue image data B, which are G and B subfield data, is shifted to the lines L16 to L31 of the second partition. It is read, sent to the rearrangement unit 150, and rearranged to match the data signal format required for the address driver 53. The rearrangement unit 150 rearranges and outputs 32-bit subfield data R, G, and B from the memory control unit 140 in accordance with the input format of the address driver.

So far, the present invention has been described with reference to the most preferred embodiments, but the above embodiments are only for better understanding of the present invention, and the contents of the present invention are not limited thereto. Additions, reductions, changes, modifications, etc. of some components of the composition of the present invention fall within the scope of the present invention as long as they belong to the technical idea of the present invention defined by the appended claims.

 As described above, according to the logic control apparatus for plasma display panel according to the present invention, since the frame memory is included in the logic control apparatus, the manufacturing cost of the circuit for the plasma display panel is reduced. In addition, according to the logic control apparatus for a plasma display panel according to the present invention, input / output pins and external memory for interfacing with an external memory are unnecessary, and power consumption is also reduced, which is advantageous in terms of design of a printed circuit board.

Claims (5)

The address period in which the wall charges are formed in the cells to perform the display discharge, and the sustain-discharge period in which the display discharge occurs in the cells in which the wall charges are formed in the cells in which the alternating sustain pulses are applied to all the cells, are divided into unit sub-fields. 10. A logic control apparatus for a plasma display panel which is formed, wherein a combination of unit sub-fields forms a unit frame. A single red frame-memory, a single green frame-memory, and a single blue frame-memory in the logic controller, And each of said single frame-memory performs a write operation and a read operation simultaneously on a frame. The method of claim 1, And said single frame-memory performs a write operation and a read operation on a single frame. The method of claim 1, And said single frame-memory performs a write operation and a read operation on a plurality of frames. The method of claim 3, The single red frame-memory, the single green frame-memory, and the single blue frame-memory each include a first compartment and a second compartment having the same data space, Wherein the frame-memories perform a write operation and a read operation on a plurality of frames, alternately performing a write operation and a read operation on the first and second sections on a plurality of frames. Panel logic controller. The method of claim 3, The single red frame-memory, the single green frame-memory, and the single blue frame-memory each include a first compartment and a second compartment having the same data space, The first compartment performs only a write operation, the second compartment performs only a read operation, The frame-memory performing a write operation and a read operation on a plurality of frames is performed by shifting the image data of the first section in which the write operation has been performed on the previous frame to the second section and moving to the second section. And a read operation is performed on the image data on a current frame.

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