KR100196832B1 - Memory in pdp tv - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a PDP TV, wherein a composite video signal transmitted from a broadcasting station is converted into digital video data through an A / D converter, and reconverted into video data having the same weight through a data processor. After arranging, the image data of the odd field is stored in the odd field memory, the image data of the even field is stored in the even field memory, and then stored in the odd field memory and the even field memory based on a control signal for selection from the memory control unit. Since the image data of each stored field is alternately provided to the PDP driving circuit, the image data is processed in the interlaced scanning method, thereby reducing the capacity of the memory provided for converting the progressive scanning method.

Description

PDTV memory device

1 is a schematic block diagram of a memory device of a PDP TV according to a preferred embodiment of the present invention.

2 is a schematic block diagram of a memory device of a conventional PDP TV.

* Explanation of symbols for main parts of the drawings

110: control signal generator 120: A / D conversion unit

130: data processing unit 140: memory control unit

150,160: frame memory 155: radix field memory

165: storm field memory 170: data selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PDPMA TELEVISION (hereinafter abbreviated as PDP TV), and more particularly, to a memory device of a PDP TV capable of storing image data in field units.

Among the various display devices that are applied to various fields, cathode ray tubes (CATHODE RAY TUBE: hereinafter referred to as CRT), which can display clearly, colorize, operate easily, and have low manufacturing cost, are used in many fields. Since the CRT itself has a structure of a Frasco type, it is large in size, requires a high operating voltage of approximately 10,000V, and has a big disadvantage of display distortion.

Therefore, the emergence of a display device capable of replacing the CRT is strongly demanded, and research on a so-called flat display device having a large display area and a small volume has been continuously conducted in many fields related thereto.

On the other hand, the flat display device as described above, active elements such as ELECTRO LUMINESCENCE, LIGHT EMITTING DIODE, PDP, LIQUID CRYSTAL DISPLAY, ELECTRO CHROMIC DISPLAY) and the like, and the present invention relates to a display device using a PDP which is substantially one of the active elements.

For reference, the advantages of the above-described PDP display device include a memory function that continues discharge when the input pulse is input once, and the display point is defined by the matrix structure, so that there is no distortion of the image and the emission frequency is 50-100 kHz. Because it is high, there is no flicker. In addition, since the PDP has a planar structure, it is advantageous for miniaturization, and since the material that reduces the extinguishing due to discharge is used on the surface of the dielectric layer in contact with the discharge, the life is long, and the panel structure mainly composed of the glass plate projects semi-fixed information as a slide It is possible to superimpose on a slide, which is advantageous for simplicity.

2 is a schematic block diagram of a memory device of a conventional PDP TV, which is abbreviated as a control signal generator 110 and an A / D converter (hereinafter, referred to as an A / D converter). 120, a data processor 130, a memory controller 140, a first frame memory 150, a second frame memory 160, and a data selector 170.

In FIG. 2, the control signal generator 110 controls a control signal and data for converting an analog composite video signal into digital video data based on a horizontal sync signal and a vertical sync signal included in the composite video signal. Generates a control signal for the control signal, a control signal for storage, a control signal for memory allocation and selection, and a control signal for data selection.

The A / D converter 120 converts the analog composite video signal into digital video data based on the control signal for conversion from the control signal generator 110, and the data processor 130 controls the control signal. Based on the control signal for data processing from the generator 110, the image data digitally converted by the A / D converter 120 is rearranged into image data having the same weight WEIGHT.

In addition, the memory controller 140 provides control signals corresponding to the control signals for memory allocation and selection from the control signal generator 110 to the first frame memory 150 or the second frame memory 160, respectively. .

In FIG. 2, the first frame memory 150 and the second frame memory 160 are configured to control signals for storage from the control signal generator 110 and control signals for allocation from the memory controller 140. The image data rearranged by the data processor 130 is stored on a frame basis, and the stored image data is provided to the data selector 170 based on a control signal for selection from the memory controller 140.

In addition, the data selector 170 selectively selects image data read and provided from the first frame memory 150 or the second frame memory 160 based on a control signal for selection from the control signal generator 110. Provided by PDP drive circuit.

An operation process of a memory device of a conventional PDP TV in the related art, which is constituted as described above, will be described in detail with reference to FIG.

First, since the composite video signal transmitted from a broadcasting station is an interlaced scan method, since the PDP TV displays the video data in a sequential scan method, it is necessary to store the video data in units of frames in the memory.

Next, the analog composite video signal transmitted from the broadcasting station is converted into digital video data through the A / D converter 120 based on the control signal for conversion from the control signal generator 110, and then Based on the control signal for the data processing from the control signal generator 110 is rearranged into the image data having the same weight as in the data processor 130.

The first frame memory 150 is selected based on a control signal for storage from the control signal generator 110 and a control signal for allocation from the memory controller 140, and is allocated from the memory controller 140. The rearranged image data in the data processor 130 is stored in the address.

Then, the data stored in the first frame memory 150 is read and provided to the data selector 170 based on the control signal for selection from the memory controller 140, and from the control signal generator 110. The image data protruding from the first frame memory 150 through the data selector 170 is provided to the PDP driving circuit based on a control signal for selection.

At this time, the composite video signal of the next frame transmitted from the broadcasting station is stored in the second frame memory 160 through the operation process as described above.

On the other hand, when the image data stored in the first frame memory 150 is read out and provided to the PDP driving circuit through the selector 170, the second frame memory based on a control signal for selection from the memory controller 140. The image data stored in the 160 is provided to the data selector 170, and the second frame memory (eg, the second frame memory) is provided through the data selector 170 based on a control signal for selection from the control signal generator 110. The image data read out from 160 is provided to the PDP driving circuit.

As described above, the conventional memory device of the conventional PDP TV alternately stores and reads data in two frame memories to provide image data to the PDP driving circuit for continuity of the image data.

On the other hand, if the resolution of the PDP TV is VGA class, the capacity of two frame memories required at this time requires about 16 MBIT.

However, since a conventional memory device of a conventional PDP TV uses two frame memories to convert the interlaced image denta transmitted from a broadcasting station into a sequential scan method, there is a problem of causing a waste of memory.

Accordingly, an object of the present invention is to provide a memory device of a PDP TV capable of displaying image data by interlaced scanning using two field memories. have.

In order to achieve the above object, the present invention provides a memory device for storing a composite video signal transmitted from a broadcasting station and then providing a PDP driving circuit, wherein the horizontal sync signal and the vertical sync signal included in the composite video signal are converted into analog signals. Control signals for converting composite video signals into digital video data, control signals for data processing, control signals for storage, control signals for memory allocation and selection, and control signals for generating control signals for data selection, respectively A / D conversion means for converting the analog composite video signal into digital video data based on a generation means, a control signal for conversion from the control signal generation means, and data processing from the control signal generation means. Zero converted digitally from the A / D conversion means based on a control signal for Data processing means for rearranging the data into video data having the same weight, and an address is simultaneously selected while selecting one of two field memories based on a control signal for memory allocation and selection from the control signal generating means; And two memory control means for storing rearranged image data through the data processing means at an address assigned by the memory control means based on a control signal for storage from the control signal generating means. The PDP driving circuit based on a field memory and a control signal for selection from the control signal generating means among the image data read out from the two field memories based on a control signal for selection from the memory control means; To provide optional Provided is a memory device of a PDP TV, comprising data selection means.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a memory device of a PDP TV according to a preferred embodiment of the present invention. The control signal generator 110, the A / D converter 120, the data processor 130, and the memory controller are shown in FIG. 140, the odd field memory 155, the even field memory 165, and the data selector 170.

Meanwhile, the control signal generator 110, the A / D converter 120, the data processor 130, the memory controller 140, and the data selector 170 in the constituent members of the memory device according to the present invention are described above. The control signal generator 110, the A / D converter 120, the data processor 130, the memory controller 140, and the data selector are among the components constituting the memory device of the conventional PDP TV. Since it performs substantially the same function as 170, the description of the function here will be omitted in order to avoid duplicate description.

Therefore, the memory device according to the present invention is different from the conventional memory device, as the radix field memory 155 and the even field memory 165, and the following description will focus on the operation of these components. .

In FIG. 1, the radix field memory 155 is configured by the data processor 130 based on a control signal for storage from the control signal generator 110 and a control signal for allocation from the memory controller 140. Image data of the radix field is stored among the rearranged image data, and the even field memory 165 stores a control signal for storage from the control signal generator 110 and a control signal for allocation from the memory controller 140. Based on the rearranged image data in the data processor 130 stores the image data of the even field.

An operation process of the memory device of the PDP TV according to the present invention made of the above-described constituent members will be described in more detail with reference to FIG. 1.

First, the composite video signal of the radix field transmitted from the broadcasting station is converted into digital image data through the A / D converter 120 based on the control signal for conversion from the control signal generator 110, and then controlled. The data processor 130 rearranges the image data having the same weight based on the control signal for data processing from the signal generator 110.

The radix field memory 155 is selected based on a control signal for storage from the control signal generator 110 and a control signal for allocation from the memory controller 140, and an address allocated from the memory controller 140. The video data of the radix field is stored in the video data rearranged by the data processor 130.

Then, the data stored in the radix field memory 155 is read and provided to the data selection unit 170 based on the control signal for selection from the memory control unit 140, and the selection from the control signal generation unit 110 is performed. The image data of the radix field read from the radix field memory 150 through the data selector 170 is provided to the PDP driving circuit based on the control signal for the control signal.

At this time, the composite video signal of the even field continuously transmitted from the broadcasting station is stored in the even field memory 165 through the above operation process.

On the other hand, when the image data of the radix field stored in the radix field memory 155 is read out and provided to the PDP driving circuit through the selector 170, the even field based on the control signal for selection from the memory controller 140. The image data of the even field stored in the memory 165 is provided to the data selector 170, and is excellent through the data selector 170 based on a control signal for selection from the control signal generator 110. Image data of even field read out from the field memory 160 is provided to the PDP driving circuit.

As described above, the composite video signal transmitted from the broadcasting station is converted into digital video data through the A / D converter 120, and rearranged into video data having the same weight through the data processor 130. The radix field image data is stored in the radix field memory 155, and the even field image data is stored in the even field memory 165, and then the radix field memory is based on a control signal for selection from the memory controller 140. The image data of each field stored in 155 and the even field memory 165 are alternately provided to the PDP driving circuit.

For example, if the resolution of the PDP TV is VGA, the capacity of the two field memories required at this time is about 8 MBIT, and half of the memory can be used to process the image data, compared to using the conventional two frame memories.

Therefore, using the present invention, since the image data is processed in the interlaced scanning method, there is an effect that can reduce the capacity of the memory provided to convert to the progressive scanning method.

Claims (1)

A memory device for storing a composite video signal transmitted from a broadcasting station and then providing the composite video signal to a PDP driving circuit, the analog video signal being analog based on a horizontal sync signal and a vertical sync signal included in the composite video signal. Control signal generating means (110) for generating a control signal for converting to a control signal, a control signal for data processing, a control signal for storage, a control signal for memory allocation and selection, and a control signal for data selection, respectively; A / D conversion means (120) for converting the analog composite video signal into digital video data based on the control signal for conversion from the control signal generating means (110); Data processing means for rearranging the image data digitally converted by the A / D conversion means 120 into image data having the same weight based on the control signal for data processing from the control signal generating means 110 130; Memory control means (140) for selecting any one of two field memories (155, 165) and allocating an address at the same time based on a control signal for memory allocation and selection from the control signal generating means (110); The two for storing the rearranged image data through the data processing means 130 at the address assigned by the memory control means 140 based on the control signal for storage from the control signal generating means 110 Field memories 155 and 165; On the basis of a control signal for selection from the control signal generating means 140 among the image data read out from the two field memories 155 and 165 based on a control signal for selection from the memory control means 140. And a data selecting means (170) for selectively providing the PDP driving circuit to the PDP driving circuit.