JPS61140992A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a display control method, and particularly to a display control method suitable for application to control of a display device such as a high-density liquid crystal display in which a display screen is divided into multiple parts. Regarding the method.

(Prior Art) Conventional control circuits for controlling high-density liquid crystal displays include, for example, Nikkei Electronics (1984, 7-30).
rProduct development of vibrant LCD controllers p,
145-In. this house,
Conventionally, a control circuit for controlling a high-density liquid crystal display in which the display screen is divided into multiple parts as shown in Figure 3 has been constructed using an independent refresh address generation circuit for each divided display screen, and a refresh control circuit for storing display data. Those with memory were common. According to such a control circuit, the addresses when drawing on the split screen are discontinuous at the vertical and horizontal boundaries of the split screen [13, [2], ..., [N] shown in FIG. becomes. In other words, if the drawing address for the first line of split screen [11] starts from O and ends at M, what is the continuous value of the first drawing address for the first line of split screen [2] such as M+1? Furthermore, the leading value of the drawing address on the first line of the first split screen [3] is not a continuous value such as 2M+1, and as shown in the lower split screen of Figure 3, the drawing address is not the same as the split screen. It becomes a continuous value internally. Therefore, when performing screen operations such as screen scrolling, character insertion, and graphic processing on the entire N split screens, the split screen [
Since the drawing addresses become discontinuous at the vertical boundaries of 11, [2], .

This was burdensome and required more processing time than when the circuit was constructed using dedicated hardware. Also, currently there are control circuits that take into consideration the continuity of drawing addresses for the top and bottom surfaces of a divided display screen, but there are no control circuits that take into account the continuity of drawing addresses for all of the divided screens. Ta. Therefore, even when the circuit of the above control method is used, when controlling a screen with a screen density greater than 2, screen operations such as character insertion processing and graphic processing are largely dependent on software.

Generally, when realizing screen scroll processing and character insertion processing using software, it is necessary to read out the entire display screen and rewrite the entire display screen, but in the case of a split screen, as shown in the flowchart in Figure 4. , (a) reading display data for the entire N-split screen, (b) address conversion calculation processing of data for each byte, and (C) processing for drawing data for each byte. The processes in (b) and <c> are repeated as many times as the display data on the screen, so if (b) and (C) are repeated once,
) is assumed to complete in about 100 microseconds, it is necessary to perform the calculation process 5,000 to 10,000 times to process the entire LCD screen, so Compare software on split screen
Scroll and software character insertion processing takes 0.5 seconds or more
An additional processing time of about 1.0 seconds is required.

(Problem that the invention attempts to solve) The conventional control method has the following problems.

(1) When graphic processing is performed on a screen where drawing addresses are discontinuous, address calculation becomes complicated and the burden on the software increases, resulting in an increase in processing time.

(2) When screen operations such as screen scroll processing and character insertion processing are performed due to discontinuous portions of drawing addresses caused by screen division, it is necessary to handle all operations using software processing. Therefore, compared to a method using dedicated hardware, processing time is required.

Therefore, the present invention has been made in order to eliminate the above-mentioned problems caused by discontinuity of drawing addresses on the split screen of a display device. To provide a display control method capable of improving the operability of software processing and shortening processing time by realizing screen operations such as screen scrolling and three-character insertion processing using dedicated hardware. With the goal.

(Means for solving the problem) The present invention has multiple display screens! l! This is a display control method that controls a display device such as a high-density liquid crystal display that is divided into two parts, and is equipped with a plurality of latches for holding screen display data and a correction address generation unit, and has one refresh memory read cycle. The refresh memory is read for the number of screen divisions to make the drawing addresses of the divided screens continuous. The latch is provided at the output stage of the refresh memory for storing screen display data, and holds the screen display data.The correction address generation unit generates a screen division correction address in order to serialize the drawing address of the divided screen.

(Function) According to the present invention, since the display control system is configured as described above, it functions as follows.

During the screen refresh period, the correction address generation unit first generates a refresh address value for the first divided screen, and the refresh memory is accessed based on this. Then, the data determined by the refresh address is held by the first screen display data holding latch.Similarly, the data for each split screen is fixed and held for the second, third, and so on. After this is done, the final data is provided to the display device. This refresh memory reading is performed by repeating 0 or more operations performed for the number of screen divisions in one refresh memory read cycle, thereby achieving continuous drawing addresses for the divided screens and solving the problems of the prior art described above. become.

(Example) First, the control system of the present invention will be explained based on FIGS. 1 and 2. FIG. 1 is a block diagram for explaining the control method of the present invention, and FIG. 2 is a time chart thereof.

In FIG. 1, l is an address counter for generating refresh addresses, 2 is a correction address generation unit that generates addresses for screen division correction, and 3 is an addition of the address data of address counter 1 and the address data of correction address generation unit 2. 4 is a multiplexer for switching between screen refresh operation and drawing operation; 5 is a timing generation unit for providing necessary timing to the entire control circuit; 6 is a refresh memory for storing display data; 7 is a line counter that counts the number of lines. 8-1 to 8-N are latches for holding display data, and are used for the number of screen divisions (N). 9-1
~9-N are shift registers for converting parallel display data to serial display data, and latch 8-N
Similar to 1 to 8-N, only the number of screen divisions (N) is used.

10 is a central processing unit; 11 is a drawing address bus that supplies drawing addresses from the central processing unit 10 to the multiplexer 4 during drawing operations; and 12 is a central processing unit l.
This is a data bus for data transfer between O and the refresh memory 6.

Signal names in Figure 1 (CHRCLK, REF-1,...,
LTS-1,...

DATA, . . . , LOAD, etc.) correspond to the signal names in the time chart of FIG. 2, respectively.

The address counter l is a counter for one line of one divided screen, and as shown in FIG. 3, its count value generates an address for one line from 0 in the upper left to M in the upper right.

This address counter 1 is composed of a modulo (M+1) base counter. The correction address generation unit 2 corrects the refresh start address value at the top left of the N divided screens.The correction address generation unit 2 generates a refresh start address value in advance at the leftmost part of each line of the N divided screens. It outputs the refresh start address value of each divided screen according to the signal input to the correction address generation unit 2. The adder 3 adds the address generated by the address counter l and the address generated by the correction address generation unit 2,
Its address output is applied to multiplexer 4. As you can see from the time chart in Figure 2, CHRCLK
The first half is a period for reading and writing data between the central processing unit 22) 1G and the control circuit, and the refresh operation for the N-divided screen is performed in the second half.

During screen refresh operation, strobes REF-1, REF-2 to REF- for refreshing address switching are used.
By N, each refresh address of N divided screens is switched and generated in order from divided screen [11] to divided screen [N]. Refresh addresses Al, A generated in order
Display data DAT on the split screen determined by 2-AH
A-1, DATA-2, ~DATA-N are display data latch strobes, LTS-1, LTS-2 ~LT
Due to SN, up to the trailing edge of CHRCLK is held in display data holding latch groups 8-1 to 8-H. Retained display data DATA-1, DATA-2, ~DAT
A-N is a load strobe L for the shift register groups 9-1 to 9-N that is generated at the trailing edge of CHRCLK, is taken into the shift register groups 9-1 to 9-N at the OA port, and finally each division Serial data SDI to screen.

SD2-SDN are generated and supplied to a display device (eg, a high density liquid crystal display).

As can be seen from the above description, the characteristics of the control method of the present invention are as follows.

(1) Perform refresh operations for the number of divided screens using the same fresh memory in one refresh memory read cycle.

(2) A correction address generation unit is provided to generate a refresh start address value for the leftmost line of each divided screen as a means for eliminating discontinuity of drawing addresses on divided screens.

It is in.

Next, an embodiment of the control method of the present invention will be described. FIG. 5 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the number of screen divisions N=4, and the liquid crystal display to be actually connected has 480 dots in the horizontal direction as shown in FIG. , a four-split screen with 128 lines in the vertical direction is assumed. Furthermore, since the control circuit is assumed to be a circuit that outputs 8-bit serial data in the refresh cycle, 480 dots in the horizontal direction become BO bytes in the horizontal force direction, and the drawing address becomes the address shown in FIG.

In FIG. 5, 21 is an address counter, 22 is a register, 23 is an adder, 24 is a correction address generation unit, 25 is an adder, 28 is a multiplexer, 27 is a timing generation unit, 28 is a refresh memory, 29-
1 to 28-4 are latches, 30-1 to 30-4 are shift registers, 31 is a central processing unit, 32 is a line counter, 33 is a drawing address bus, and 34 is a data bus. The signal names in FIG. 5 also correspond to the signal names in the time chart of FIG. 6, respectively.

The address counter 21 generates a refresh address, and in this example, the divided screen is 30 bytes per line, so the generated address is 0 in lO base.
~28. This address counter 21 can be constructed from a modulo-30 counter. Register 22 is a register for screen scroll processing, and the seventh
The refresh start point shown in the figure)' P s ,
That is, scroll processing is performed by resetting the value of the point at the drawing address O at the upper left of the screen. Since this register 22 usually has a circuit configuration having a refresh memory capacity of two screens or more, a register of 11 bits or more is used. The adder 23 adds the address of the address counter 21 and the address of the scroll processing register 22.
The values from the set value 15 to Rqv+29 are repeatedly output. The correction address generation unit 24 generates addresses for making the four-split screen a continuous address. This correction address generation unit 24 performs a process of consecutively addressing a 4-split screen of 30 bytes horizontally and B4 vertical lines, and its output value is based on the output value of the line counter 32 and the input strobe REF from the timing generation unit 27. -A, REF-B.

It is uniquely determined by REF-C and REF-D. FIGS. 8(a) and 8(b) show the input/output relationship of the correction address generation unit 24 of this embodiment. The line count signal (LINE) input to the correction address generation unit 24 is transmitted vertically on a 4-split screen. has an 84-line configuration, so 0 to 6
Up to 3. Adder 25 adds the output of adder 23 and the output of correction address generation unit 24, and outputs an address for refreshing refresh memory 28. The central processing unit 31 is connected to the control circuit of this embodiment, and the drawing process to the refresh memory 28 is performed via the drawing address bus 33 and the data bus 34. The multiplexer 2B is connected to the drawing operation from the central processing unit 31 and the screen. In the multiplexer 2B, which switches the address of the refresh operation, the first half of CHRCLK is allocated to the drawing operation of the central processing unit 31, and the second half is allocated to the four-split screen, as shown in the time chart of FIG. It is assigned to the refresh operation. A timing generation unit 27 generates timing necessary for the control circuit of this embodiment. REF-A, REF-B, REF-C, REF-D which are the outputs of the timing generation unit 27
is a strobe for switching addresses during a screen refresh operation for a 4-split screen, and is supplied to the correction address generation unit 24. These strobes REF
-A-REF-D correspond to screens A to D of the four-split screen in FIG. 6, respectively. LTS-A, LTS-B
, LTS-C:, LTS-D is the refresh memory 28
This is a strobe for holding data from the latches 29-1 and 29-2, respectively, for holding the data of the A screen, 8 screen, C screen, and 0 screen in FIG.
.

It corresponds to latch 29-3 and latch 23-4. Data DATA-A, DATA-B held by latches 29-1, 29-2, 29-3, 29-4
, DATA-C, and DATA-D are the shift register load clock LOA output in the latter half of GHRCLK.
D, shift registers 30-1 and 30-
2, 30-3, and 30-4, and finally converted into serial data SD^, SD, , SDe, 50 units, and supplied to the liquid crystal display.

The correction address generation unit 24 of this embodiment has a total of nine input signals, REF-A, REF-B, REF-G, REF-D, and five line count signals (LJNE), and output signals RAO to There are 13 RAs 12, and the signal input/output relationship is quite complicated as shown in FIGS. 8(a) and 8(b). Therefore, it is common to configure a unit by storing data in a read-only memory in advance.

Next, regarding the operation of this embodiment, the block diagram shown in FIG.
This will be explained based on the time chart in FIG. 6 and the drawing address explanatory diagram of the 4-split screen in FIG.

The clock SFT CLK in FIG. 6 is the shift register 30.
It is used as a shift clock of -1 to 30-4, but in the case of this embodiment, it is also used as a basic clock of the timing generation unit 27. Clock SFT CLK to 8
The clock CHRCLK obtained by frequency division is a signal for dividing the period during which the refresh memory 28 can be accessed from the central processing unit 22) 31 and the period during which the display screen is refreshed, and the screen refresh operation is performed using CHRCLK.
Clock CI
(When RCLK becomes high level and enters the screen refresh period, strobe REF-A first becomes I SFT CL
The level is high during the K period. Then, the correction address generation unit 24 generates a refresh address value corresponding to the divided screen A in FIG. 7 from the high level output of the strobe REF-A and the output (LINE) of the line count 32. The address to actually access the 7-ray memory 28 is:

Address counter 21 and scroll processing register 2
This is the sum of the address value output by 2 and the refresh address value. That is, the sum of the output value of the address counter 21, the output value of the scroll processing register 22, and the output value of the adder 25 becomes the address value for actually accessing the refresh memory 28. The time chart shown in Figure 6 is
Assuming that the state at the beginning of the first line of the divided screen shown in the figure is shown, the address Al determined by the strobe REF-A is O. The data determined in the refresh memory 28 by the refresh address AI, that is, 0, is sent to the display data latch strobe LTS-A for the split screen A.
is maintained by In the time chart in Figure 6, the DAT starts from the double circle mark on the trailing edge of the strobe LTS-A.
This shows that A-A is maintained.

Next, when strobe REF-A becomes low level and strobe REF-B becomes high level, address value Bl corresponding to split screen B, that is, address value 30, is generated, and this address value 30 causes refresh memory 28 to be stored. Accessed and confirmed display data DATA-8
is held by the latch strobe 1 and TS-H.

Similarly, when strobe REF-C becomes high level,
Fresh address (ficl) corresponding to split screen C
, that is, the refresh memory 28 is accessed by an address value of 3840. Confirmed display data DATA-
C is held by a latch strobe LTS-C.

Further, when the strobe REF-D becomes high level, the refresh memory 28 is accessed using the refresh address value DI corresponding to the divided screen, that is, the address value 3870. The determined display data DATA-D is held by the latch strobe LTS-0.

Then, during the period of the last I SFT CLK of aSICLK, the clock LOA becomes high level, and at this time, the data DATA-A, DATA-B, corresponding to each divided screen A, B, C, D, DATA-〇 and DATA-〇 are respectively shift registers 30-1,
30-2, 30-3, and 30-4, and finally serial data SD^, SD,.

It is converted to SDe, 50 units, and supplied to the liquid crystal display.

1 split screen A in the next refresh cycle.

A as the refresh address value corresponding to B, C, and D.
2 is 1. B2 is 31. C2 is 3841, D2 is 3
The value 871 is output and the screen is refreshed.

By repeating the above operations, split screens A, B,
Since the refresh addresses of C and D are made continuous for 4 screens, the addresses at the time of drawing can also be performed for 4 consecutive screens.

As explained above, in this embodiment, the display screen is divided into four parts as shown in FIG.
Split screens A' and B shown in the figure.

The refresh addresses corresponding to C and D are generated four times via the correction address generation unit 24, and the display data is determined four times in one screen refresh cycle, and the last part of the refresh cycle I SFT C
Display data holding latch 213-1゜28- is used to capture the four data determined during LK into shift registers 3G-1, 30-2, 30-3, and 30-4 at once.
2.29-3.29-4 is provided. Furthermore, in this embodiment, the refresh addresses generated by the address counter 21 and the correction address generation unit 24 can cover the entire drawing addresses of the four divided screens A, B, C, and D shown in FIG. Since it is necessary to perform hardware scrolling and hardware character insertion processing, a scroll processing register 22 is provided to determine the screen refresh start address value.

The major feature of the control system of the present invention is that it has an address counter 21 that generates an address for one line of a split screen and a correction address generation unit 24 that outputs the leftmost value of each line of the split screen. It is conjectured that by simply adding one scroll processing register 22, it is possible to perform l\-ware scrolling of the entire divided screen, hardware character insertion processing, and screen graphic processing. Furthermore, although the control method of the present invention employs a method of drawing data directly on the display screen, in order to display only characters or specific fonts, a control circuit equipped with a character buffer and a character generator may also be used. The control method of the present invention can be used. In that case, a latch for holding display data must be inserted between the character generator and the shift register to hold the data of the character generator until the latter half of one refresh cycle.

(Effects of the Invention) As explained above, according to the present invention, it becomes possible to serialize the drawing addresses of the split screen of a display device such as a high-density liquid crystal display with a relatively simple circuit configuration, and the following There are advantages.

(1) When performing graphic processing, unnecessary address calculations are no longer necessary, and the burden on the software is reduced. Therefore, the operability of the software will be considerably improved.

(2) When performing screen operations such as screen scroll processing and character insertion processing, the circuit configuration allows dedicated hardware to be easily added, so there is no need to perform all software processing. Therefore, it is possible to significantly shorten the operation processing time.

(3) By using a hydraulic control circuit, it is possible to realize a shared display memory circuit between a CRT display control circuit and a liquid crystal display control circuit. Therefore, C
It can be effectively used in control circuits of devices that use both an RT display and a liquid crystal display.

(A zero-hydraulic type control circuit can be realized with a medium-sized circuit, but by using a dedicated IC, it can be directly mounted inside small devices or liquid crystal display units, making it suitable for a wide range of applications.) It will be possible to use it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the display control method of the present invention, and FIG.
The figure is a time chart to explain the operation of the control method in Figure 1, Figure 3 is a diagram showing the high-density liquid crystal display display screen with N-split screen and its divided screens, and Figure 4 is the software scroll of the split screen. , a flowchart of character insertion processing, FIG. 5 is a block diagram of an embodiment of the present invention, FIG. 6 is a time chart for explaining the operation of the embodiment of FIG. 5, and FIG. 7 is a flowchart of the embodiment of FIG. Figures 8(a) and 8(b) are diagrams showing the drawing addresses of a liquid crystal display with 60 bytes horizontally, 128 lines vertically, and 4 screen divisions connected to the embodiment, and the correction address i generated in the embodiment of FIG. FIG. 3 is a diagram for explaining input/output relationships of units. 1.21...address counter, 2.24...correction address generation unit, 3.23,
25. ...Adder, 4.26...Multiplexer, 5.27...Timing generation unit. 6.28... Refresh memory, 7.23... Line counter, 8-1 to 8-N: 29-1 to 23-4... Latch, 9
-1 to 9-N; 30-1 to 30-4...Shift register, 10, 31...Central processing unit, 11.33
...Draw address bus. 12.34...Data bus.

Claims (1)

[Claims] In a display control method that controls a display device whose display screen is divided into multiple parts, a plurality of latches for holding screen display data provided at the output stage of a refresh memory for storing screen display data, and a continuous drawing address for the divided screen are used. and a correction address generation unit that generates addresses for screen division correction in order to perform screen division correction, and read the refresh memory for the number of screen divisions in one refresh memory read cycle to make the drawing addresses of the divided screens continuous. A display control method characterized by: