JPS58187989A - Display memory circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display memory circuit suitable for writing to a display memory in units of dots in a display device that displays high-definition graphics.

Display specifications such as higher definition and faster display processing are required in devices such as personal computers that read data written in display memory and display graphics on display screens such as polarized tubes. It was rice.

FIG. 1 shows a conventional display device that uses a display memory circuit and is capable of displaying high-definition graphics and character overlays. In FIG. 1, 1 is an arithmetic processing circuit (hereinafter referred to as MPU) that performs arithmetic processing of the display device, and 2 is a display control circuit (hereinafter referred to as C) whose display address outputs horizontal and vertical synchronizing signals.
5 is an address conversion circuit that converts the display address from the above CRTC 2 into addresses in the graphic pattern data storage range and character code data storage range % 4 is an address signal from the above MpU 1 and the CRTC
2 is a switching circuit for switching the address signal from 2; 5 is a display memory for storing graphic pattern data and character code data; 6 is a pattern generation circuit for converting the character code into a character/(turn); 7 and 8 are parallel patterns. 9 is a parallel/serial conversion circuit that converts data into serial data; 9 is a synthesis circuit that synthesizes serial graphic pattern data and serial character pattern data and outputs it to the display tube; 11 is a synthesis circuit that converts the display memory 5 in bit units; A control signal generation circuit that generates a signal 16 for controlling writing, 1
2 is a mask register which records which bits are writable; 10 is a selection circuit for selecting the display memory 5 from the CPU. The control signal generation circuit 11 and the mask register 12 constitute a write control circuit 15. FIG. 2 shows the write control circuit 16 in more detail, and the control signal generation circuit 11 is composed of an AND circuit 19. Further, the display memory 5 is made up of eight memory circuits 20.

A conventional display memory circuit will be explained with reference to FIGS. 1 to 4.

When a mixture of characters and graphics is displayed on the display screen as shown in FIG. 6, graphic pattern data is stored in the display memory 5 from the first half of the display memory 5, that is, from address 0, as shown in FIG.

Also, the second half, address 8000 in hexadecimal (hereinafter s o
Character code data is stored in the hexadecimal number with an H added (such as o oH).

The display address output from the CRTC 2 is converted by an address conversion circuit 6 into a graphic pattern data storage address and a character code data storage address, and inputted into the display memory 5 through the switching circuit 4. Display memory 5
Then, it receives these two addresses and outputs graphic pattern data and a character code during one character display period. The character code is input to a pattern generation circuit 6, converted into a one-character pattern, and input to a parallel-to-serial conversion circuit 7. On the other hand, the graphic pattern is directly input to the parallel-to-serial conversion circuit 8.

The data is converted into displayable serial pattern data by the two parallel-to-serial conversion circuits 7 and 8, synthesized by one synthesis circuit 9, and mixedly displayed with graphics and characters on one display tube or the like. The manner in which the data stored in the display memory 5 is displayed in this manner will now be explained in the case where new graphic data is written to the display memory 5. As shown in Figure 5.

Assume that pattern data is now stored in the graphic pattern data storage area. Suppose that new display data is written there. (Hereinafter, for convenience of explanation, the leftmost data bit will be referred to as D7, and the rightmost data bit will be referred to as Do.) Since the above new write data is only bits D6 to D4, the mask register 12 has the mask shown in FIG. Data alarm. By using this mask data and the AND circuit 19GC in FIG. 2, the write control signal 15 from MpUl is output only to D6 to D4, and not to the remaining D7 and D6 to DO. Therefore, select display memory 5 from MpUl,
When the selection circuit 10 selects the display memory 5 and outputs display data to the data bus 17, only bits D6 to D4 of the 8-bit data are sent to the display memory 17.
I am drawn to 5. As a result, as shown in FIG. 5, the current graphic pattern is further added to the previous stored graphic pattern.

In this way, the mask register 12 and the control signal generation circuit 11
This allows graphic pattern data to be written into the display memory 5 at high speed. but.

Display device K using the display memory circuit according to the prior art described above had the following drawbacks.

A case will be explained in which character code data is further written into the display memory 5 after writing the graphic pattern data.

As described above, mask data was written into the mask register 12 in order to write graphic pattern data. Next, if you leave the mask register 12 as it is and write a one-character code (the current character code is @A'', that is 41H), bits D6 to D4 of the above character code will be written to the previously stored data. As a result, as shown in FIG. 6, the code 41H of A is not stored in the 1-display memory 5, but the code 42H of B is stored, making it impossible to store regular character code data.For this reason, the 1-character code data In order to store , all bits must be written to the mask register 12 each time, and then the character code data must be written to the display memory 5. In other words, there is a drawback that the display processing becomes slow when outputting one character code data.

The object of the invention is to obviate the drawbacks of the prior art.

To provide a display memory circuit capable of writing graphic pattern data at high speed and also writing character code data at high speed.

In order to achieve the above object, an address detection circuit is provided to detect S for writing data into the character code data storage range of the display memory range, and when writing character code data, the write control circuit is controlled and the mask register is The configuration is such that all bits of character code data are written into the display memory regardless of the stored bits.

FIG. 7 shows a display device using the display memory circuit of the present invention. Components that are the same as in FIG. 1 are given the same numbers. 7th
In the figure, an address detection circuit 22 for detecting the character code data storage range is added to the conventional technology, and the output signal of the address detection circuit 22 controls the write control circuit 13, specifically the control signal generation circuit 21. It is configured to do this. FIG. 8 shows the write control circuit 15 more specifically. An OR circuit 25 and an AND circuit 24 constitute a control signal generation circuit 21. Further, the display memory 5 is composed of eight memory circuits 20.

The display memory circuit of the present invention will be explained using FIGS. 7 to 10. The graphic pattern data and character code data stored in the display memory 5 are similar to the prior art example.
It is read out by the address signal from the CRTC 2, passes through the pattern generation circuit 6, the parallel-to-serial conversion circuits 7 and 81, and the synthesis circuit 9, and is displayed on a display tube or the like.

Next, the case of newly writing graphic pattern data and character code data into the display memory 5 will be described. Writing of graphic pattern data is similar to the conventional technique. Namely.

New [? ! The mask data shown in FIG. 9 is written so that only the bits to be written can be written. Thereafter, display data and write control number 15 are output from MpUl. The write control signal 15 is controlled by the control signal generation circuit 21, and only bits D6 to D4 of the display memory 5KR are output.
Written only to D4 bit. As a result, as shown in FIG. 9, the current graphic pattern is additionally written to the previously stored graphic pattern.

Next, after writing the graphic pattern data, character code data "A" (41B) is further written into the display memory 5. This will be explained using FIG. 10. M.P.
U1 outputs the character code data storage address of the display memory 5 and a write control signal 15 in order to write the character code data. The address detection circuit 22 outputs a detection signal 25 of logic 1jl by detecting the character code data storage address. The detection signal 23 is input to the OR circuit 25 of the control signal generation circuit 21. The output of the OR circuit 25 is such that all bits output logic 11m regardless of the mask data stored in the mask register 2 for writing graphic pattern data last time. I wanted to”
'(The write control signal 15 from 1MpU1 is input to all bits of the display memory 5 without being controlled by the AND circuit 241C.

As a result, one character code data is written into the all-bit display memory 5. In other words, there is no need to change the contents of the mask register as in the prior art.

Further, the character code is written into the display memory 5 at high speed without being written with a change.

According to the present invention, by providing a character code data storage address detection circuit, graphic pattern data can be written into the display memory in bit units, and character code data can be written in all bits at high speed, enabling high-speed display processing. Display device can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a display device using a conventional display memory circuit, FIG. 2 is a more specific diagram of a write control circuit, FIG. 3 is a diagram showing a display screen, and FIG. Figure 5 shows the state of data stored in the display memory.
6 is a diagram showing the procedure for writing to the display memory, FIG. 7 is a block diagram showing an embodiment of the display memory circuit according to the present invention, FIG. 8 is a specific block diagram of the write control circuit, and FIG. 10 are diagrams showing the procedure for writing data into the display memory according to the present invention. . 1... Arithmetic processing circuit 5... Display memory 13...
・Write control circuit 22...Address detection circuit power 1 figure 2 figure 5 figure 4 figure 5 figure 7 screen data figure

Claims (1)

[Claims] In a display memory circuit in which each line of a plurality of data lines of the arithmetic processing circuit and the arithmetic processing circuit is connected in chip units and stores display information for a display screen to which addresses are assigned in units of the number of bits of the plurality of data lines, the above-mentioned display A display memory write control means for controlling whether or not to store display information in bits in the memory is provided, and an address detection means for detecting a specific range within the address allocation range of the display memory. When the range is detected,
A display memory circuit characterized in that it controls the display memory write control means.