JPS6152688A - Pattern data updating system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern data updating method, and particularly to a method for rapidly changing data in a VRAM that stores pattern data to be displayed on a CRT to desired pattern data.

[Conventional technology]

A CRT (cathode ray tube) display is equipped with a VRAM (video random access memory), and the dot pattern to be displayed is written in the lyRAM, read out, and displayed on the CRT.
Many use the method of displaying on the screen. In the case of color display, there are three types of VRAM for R (red), G (green), and B (blue), and since it is a digital system, seven color display is possible. There are also models that are equipped with a VRAM for brightness (I) and have a variety of display colors by adding brightness and darkness to the seven colors, and there are also models that use a method called tile paint that can produce a wider variety of intermediate colors.

In the case of color, one dot on the display screen consists of R, G, and 83 dots, but if it is treated as one dot, each dot is 0 in R.
．． 1. 0. 1.・・・・・・1゜0.1 in G
．． When O, ..., B = 0, each dot is alternately green, red, green, red, ..., and to the human eye, it appears as an intermediate color between green and red. appear. A similar display is possible with R and G, G and B, and this is evening.

This is a color display method called il-paint.

In principle, a memory chip constituting a VRAM or the like has one address and one memory cell, and one access writes and reads one bit to and from one memory cell. Multiple memory chips, for example 8, depending on the data bus width.
If used in parallel, multiple bits per address (8 in this example)
Bit access is possible, allowing quick writing and reading.

[Problem that the invention seeks to solve]

By the way, there is a request to change the display pattern by changing the data of the pattern to be displayed on the CRT in the VRAM that stores the data. For example, you may want to change a red straight line on the display screen to a green straight line, or change a solid line to a dotted line. In such cases, in the conventional method, the CPU (central processing unit)
Read the RAM, make desired changes to the read data,
A method is used in which the information is written to successive addresses in the VRAM and the process is repeated for each data bus width and for each R, C, B, but this takes time. V
The same goes when writing a new pattern to RAM;
However, since the software accesses the VRAM separately for R, G, and B and repeatedly writes new pattern data in data bus width units, it takes time.

However, the present invention attempts to enable rapid writing of VRAM by providing a writing circuit (hardware) suitable for partially modifying data and writing new ML (simply referred to as updating).

[Means for solving problems]

In a pattern data updating method for a video random access memory in which data of a pattern to be displayed on a cathode ray tube is written, the present invention writes data specifying bits to be changed and bits not to be changed to data read from the memory. an image data register into which the changed data of the bit to be changed is written;
An arithmetic circuit is provided which receives the read data of the memory and each output data of the pattern register and the image data register and corrects the read data with the data of the register, and sends the output of the arithmetic circuit to the address from which the data of the memory was read. The feature is that data is written and data 1 is corrected.
Explain the action.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and 10 is a VRAM? '
Rt< 7ri 12, G bank 14, B bank 16, I
It consists of 4 banks, 18 banks. Notes for each bank) and alpha capacity (2) are equal because of the dots in a CRT display, and multiple bits, in this example 8 bits, are written and read simultaneously. Reference numeral 20 denotes a latch circuit for VRAM puncture data, which consists of four circuits: 22 for R bank, 24 for G bank, 26 for B bank, and 28 for I bank.

30 is a pattern calculation (mask) circuit, which also has R pitch 1.
It consists of four bits: 32 for - bit, 34 for G bit, 36 for B bit, and 38 for ■ bit. 40 is a register for storing mask patterns; 42 for R, 44 for G, 4G for B, 4 for 1.
It consists of 4 rooms of 8. 60 is a register that stores image data that instructs whether to change data;
is the central processing unit (CPU), 52 is its data bus,
54 is an address bus. In this example, the bus width is 8. Therefore, data is handled in units of 8 bits, the launch circuit 20 has 8 bits each for R, G, B, and 1, the pattern register 40 has 8 bits each for R, G, B, and I, and the image data register 60 has 8 bits each for R, G, B, and I. is also 8 bits.

When updating the VRAM data, the CPU 50 sequentially writes a mask pattern to the register 40 and image data to the register 60 in 8-bit units.

VRAM10 has been initial reset and is in a state of all 0s, and the next data is stored in register 40.60.
- Suppose that evening is written.

BGR register 60 0 0 0 0 1 1 1'LDOD
i D2 D3 D4 D5 D6
D7 register 42 1 0 1 0 1 0 1
0 register 44 0 1 0 1 0 1 0 1 register 46 1 1 0 0 1 1 0 0 register 48 0 0 1 1 0 0 1 1 It goes without saying that the number in the image data register 60 is 1.
This means that bits B and I are set to 1. Also, the bit of the pattern register 40 is 1, which means that V RAM
It means that the relevant bit of the Rft output data is not changed, and 0 means that it is changed according to the image data.
means.

The arithmetic circuit 30 performs such processing. That is, the CPU 50 outputs the address of the VRAM to be updated, the VRAM is read at this address, and the 8-bit successive data is taken into the U-nochi circuit 20 by the clock CLK, and from this launch circuit is sent to the arithmetic circuit 30. It is input to one input terminal.

A pattern register 40 is connected to the other input terminal of the arithmetic circuit 30.
The above 8 human data and image data register 6 from
The RGB I bits starting from 0 are input and the calculation is performed in the manner described above. Therefore, in the above example, the output of the arithmetic circuit is as follows.

Arithmetic circuit 32 01010101 Arithmetic circuit 34 10101010 Arithmetic circuit 36 00110011 Arithmetic circuit 38 11001100 In other words, since the image data in the register 60 is RGB I is 1, these bits and nodes are instructed to be set to 1, and the pattern register 42 The data is 10101010, that is, bits DO, D2. of the 8-bit read data of the VRAM R node. D4゜D6 is not modified, so o o o o, bi-nod D1. D3, D5. D7
is modified to 1, so the total is 1111° and 010101
It becomes 01. The same applies to G, B, and I data. The output of the arithmetic circuit 30 is sent to the VRAM 12 and written to the read address of the VRAM. Therefore, the read data at the VRAM address is updated with the output of the arithmetic circuit 30, and this is done simultaneously for 8 x 4-32 bits, so high-speed processing is possible.

This VRAM writing by pattern register 40, image data 60, and arithmetic circuit 30 has various advantages. Initially, the CPU 50 has to write data into the registers 40 and 60, but after that, it can repeatedly write the data written to the register (more specifically, the data specified by this data) simply by generating an address. You can get into it. The pattern originally written in the VRAM is a red straight line, and if you want to change it to a green dotted line, set R of the image data to 0, G to 1, and the pattern register 42 is all 01, the pattern register 46 is 01010101. etc. (of course, 00110011 etc. are also acceptable), and the V in which the data of the above red straight line is stored.
It is sufficient to generate a RAM address and perform the above processing. In this case, the memory is erased for R, and the memory is written every other hit for G.

Since data 1 in the pattern register 40 indicates a hint that will not be changed, a part of a complex pattern can be changed to (1
It is convenient for processing such as correcting , or changing a part of a multi-gIU color (composite color) (therefore changing it to another composite color). Since there is no need to add data, data creation and modification processing is easy.

FIG. 2 mainly shows a specific example of the arithmetic circuit 30. As shown in FIG. 32a and 32b are address gates, 32c is an OR gate, and 32 sets of such gates are provided for each bit of RGB . In the figure, only one each of RGB I is shown. AND gate 32 a, 32 b,...
. . . are opened and closed by each bit of each pattern register 40. That is, if this bit is 1, the gates 32a, 34a,...
... is opened and the VRA is latched by the latch circuit 20.
The read data of Ml0 is sent to the gates 32a, 34a, .
...and or game) 32c, 34c, ...
, and then enters VRAMl0 again and is written. If the data in the pattern register 40 is 0, the AND gate 3
2b, 34b.

...... will open and the RGB I of image data 60 will be displayed.
The bits pass through the gates 1-32b, 34b, . . . and the OR gates 32C, 34C, .
It enters the VRAM 10 and is written. When displaying on a CRT, the VRAM10 is read out (in repeated vertical scanning cycles) and input to the CRT, and this system is shown in FIG. 2 by a Nant gate 62 and a CPU.

〔Effect of the invention〕

As explained above, according to the present invention, data writing to VRAM can be executed at high speed by hardware with less burden on the CPU, and the via 1 and the designated via 1 of continuous VRAM data can be rewritten as specified. Since this method is adopted, it is advantageous for partially modifying VRAM data, and of course new writing is also possible. According to this method, tile pane 1-, data mask, base eye creation, etc. can be easily and quickly processed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing some details thereof. In the drawing, 10 is VRAM, 40 is pattern register, 6
0 is an image data register, and 30 is an arithmetic circuit.

Claims (1)

[Scope of Claims] When updating pattern data of a video random access memory into which data of a pattern to be displayed is written, a pattern register into which data specifying bits to be changed or bits not to be changed is written to the data read from the memory. , an image data register into which changed data of the bit to be changed is written, and an operation in which the read data of the memory and each output data of the pattern register and the image data register are input and the read data is corrected with the data of the register. A pattern data updating method characterized in that a circuit is provided and the output of the arithmetic circuit is written to the address from which the data in the memory was read to correct the data.