JPH02201642A - Access system for memory for display - Google Patents

Abstract

PURPOSE:To simultaneously process all components of data on one picture element at high speed by means of a processor by providing a data converting part between the processor and a memory for a display and simultaneously executing an access to respective parts of the memory for the display. CONSTITUTION:Picture element data in corresponding positions are simultaneously read from blocks 141-143 of respective components of a memory 14 for display and inputted through individual memory data buses 131-133 with n-bit width to a data converting part 12. An interconverting means 121 of the data converting part 12 identifies the picture element data of respective components and generates code data with the data quantity of m-bit. In such a case, m<=n is satisfied, and the data quantity (m) is made into the data quantity which the processor can process once. The code data is supplied through a processor data bus 11 to a processor 10. By executing the memory access once by means of the processor in such a manner, the data of all components of Red, Green and Blue of one picture element can be simultaneously and integrally processed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a display memory access method in an image processing system in which a processor accesses a display memory having a data structure in which one pixel data is divided into blocks according to red, green, and blue components. , an object of the present invention is to provide a display memory access method that allows a processor to process one pixel of data when the display memory is accessed once,
A data conversion section is provided between the processor and the display memory,
A memory data bus is provided between the display memory and the data conversion section to transfer pixel data of each block simultaneously, and a bit-width processor data bus is provided between the processor and the data conversion section to transfer code data. Equipped with a mutual converter that mutually converts between 1 pixel code data handled by the processor and 1 pixel data that is the sum of all pixel data of each component handled by the display memory, and 1 pixel code data is The configuration is such that the amount of data does not exceed the amount of data of one pixel data of one component of the memory for use.

[Industrial Application Field] The present invention is 1ii! The present invention relates to an access method for a display memory in an image processing system in which a processor accesses a display memory having a data structure in which data of a ii element is divided into red, green, and blue components.

In recent years, techniques for digitally processing images have been used in a wide range of fields, and image processing has begun to be performed on color image data. However, as the capacity of display memory has become larger and the amount of data per pixel has increased, it has become difficult to process pixel data all at once at high speed by a processor. In other words, color image data is divided into red and green for each pixel.
This is because it is composed of three component pixel data: )+Blue(BIL+(RI)), and uses a large number of bits to represent a large number of gradations as the pixel data of each component.

Even if the amount of pixel data for each component increases in this way, it is desired that the memory that stores the pixel data be able to process all the components at once.

[Conventional technology] FIG. 7 is an explanatory diagram of a conventional example.

A in FIG. 7 shows the structure of pixel data for one pixel. One pixel (corresponding to one dot on the display screen) is composed of n-bit data for each of three color components, namely, a red component, a green component, and a blue component, and has a total data amount of 30 bits.

Such pixel data is prepared for each pixel on the display screen, data for Mars is stored in the display memory,
Reading is performed when displaying, and when image processing is performed, it is accessed by the processor and reading and writing are performed.

B in FIG. 7 is a memory map of a conventional display memory. As shown in the figure, the memory stores Red component data, G
The data of the reen component and the data of the blue component are stored separately in blocks for each component. Each component block stores data for the total number of pixels, with n bits per pixel.

C3 in FIG. 7 is an access configuration diagram of a conventional display memory.

In the figure, when accessing the display memory from the processor, the processor data bus width is in bits, and the memory data bus connected to each component block of the display memory is β bits) and width (Il is n shown in B, (or greater than n), in order to access each component's memory block simultaneously, k must be greater than 3x6, and each memory data bus must be connected to a different part of the processor data bus. It will not work properly if it is not connected. However, the width of the processor data bus is limited by the width of the data bus included in the processor.
It is difficult to use a large number of processors such as BIT processors and to connect the processor data bus and three memory data buses.

Therefore, in the past, it was generally necessary for the processor to access the display memory three times each time one pixel of data was processed.

[Problems to be Solved by the Invention] As mentioned above, in the conventional method, the processor needs to access the display memory multiple times to process one pixel data, so there is a problem that data processing takes time. there were.

An object of the present invention is to provide a display memory access method that allows a processor to process one pixel of data when accessing the display memory once.

[Means to solve the problem] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 10 represents a processor, 11 represents a processor data bus, 12 represents a data converter, 13 represents a memory data bus, and 14 represents a display memory.

The present invention provides a data conversion section between the processor and the display memory, and the data conversion section mutually converts code data from the processor and pixel data of each component of the display memory, thereby increasing the bit width of the processor data bus. One pixel data of all components is accessed simultaneously using a width similar to that of an individual memory data bus.

[Operation] The display memory 14 stores red (displayed in Red) component blocks 141. Green (displayed as Green) component block 14
2 and a blue (displayed in Blue) component block 143, and the L pixel data of each component is composed of n bits. Separate memory data buses 131 and 13 each having a width of n bits are connected between each block and the data converter 12.
2 133 are provided, forming a memory data bus 13 having a total width of (3Xn) bits.

When processing data for one desired pixel, the processor 10 accesses the display memory 14 for reading,
After processing, write access is performed. When performing read access, data of one specific pixel in the display memory is read out using an address bus (not shown). At this time,
Pixel data at corresponding positions are simultaneously read out from blocks 141 to 143 of each component, and sent to the data conversion unit 12 via individual memory data buses 131 to 133 having a width of n bits.
Enter. The mutual conversion means 121 of the data conversion unit 12 identifies the pixel data of each component and generates code data of m-bit data amount. In this case, m≦
The data amount m of the code data is the amount of data that the processor can process at one time.

Code data is supplied to processor 10 via processor data bus 11 .

The results processed by the processor 10 are input as m-bit code data from the processor data bus 11 to the data converter 12, and the mutual converter 121 of the data converter 12 converts the code data of one pixel into each component of the display memory. A total of 3n bits of pixel data is converted into n-bit pixel data, and a total of 3n bits of pixel data is stored in a separate memory data bus 1 corresponding to each component.
31-133, each component block 141-1
43 (supplied from an address bus not shown).

In this way, data for one pixel can be processed by the processor performing one read/write access to the display memory.

[Embodiment] Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an access area and code data, Fig. 4 is a configuration diagram of an embodiment of a data converter, and Fig. 5 is a configuration of code data. A diagram showing an example, FIG. 6, is a processing flow diagram.

In FIG. 2, 20 is a processor, 21 is an 8-bit wide processor data bus, 22 is a data converter (corresponding to the data converter in FIG. 1), 231 to 233 are 8-bit wide memory data buses, and 241 to 233 are 8-bit wide memory data buses, respectively. 243 is R
ed, Green.

Memory blocks for each component of Blue, 25 represents an address decoder, and 26 represents a memory controller.

The data converter can have either a configuration divided for each component or a configuration combined into one, but in this example, the data converters 221 to 223 are divided for each component of Red, Green, and Blue. It is configured to be prepared.

The display memory 24 includes memory blocks 241 to 241 for each component.
The access area of each component is shown in Fig. 3A.
Assigned as shown.

That is, as shown in the figure, the Red component is 10 from address O.
The green component is from address 10,000 to less than 20,000, and the blue component is from address 20,000 to less than 30,000. These access areas are access areas for accessing each component individually, and are not used when implementing the present invention.

The simultaneous access area for all components of the display memory according to the present invention uses addresses from 30,000 to less than 40,000. The access address of this area is determined by the processor 2 in Figure 2.
When 0 is specified, the address decoder 25 identifies which of each component it is, and at the same time identifies whether the memory blocks of all components are addressed, and corresponding to the identification result, selects BlueGreen, R, ed, Generates any output of ALL. When the ALL output is generated, the memory controller 26 manually inputs the addresses from 30000 to less than 40000 to the addresses of the three component blocks of Red, Green, and Blue, as shown in FIG. Convert each memory block 2
Output as address inputs from 41 to 243.

For example, the address of address 30001 is 1 and 10.
The three addresses 001 and 20001 are supplied from the memory address control lot 261 to each block.

In this way, all memory blocks 241 to 243 of the display memory 24 are accessed at the same time, and reading, writing, etc. are controlled by the memory controller 1-roller 26 receiving a signal output from the processor to the processor control lot 201. It is supplied to each memory block from the memory address control bus 261.

In this embodiment, the pixel data of one pixel stored in the memory block of each component of the display memory 24 is composed of 8 bits as shown in FIG. 3B, and the code data of one pixel handled by the processor is as follows. As shown in Figure 3B, Red
, Green, and Blue, and two additional bits are added to the total of six bits to make up 8 bits.

FIG. 4 shows the configuration of an embodiment of the data converter.

The data converter of FIG. 4 represents one of three similarly configured data converters provided on the component side within data converter 22 of FIG.

In FIG. 4, 21 is the 8-bit wide processor data bus shown in FIG. 2, 4o is a data converter,
1 is a code generator, 42 is a comparator, 43 is a register in which 8-bit data is set in advance, 44 is an 8-bit buffer in which data read from the display memory is stored,
4546 is a register in which preset 8-bit data is set, 47 is a converter that decodes input 2-bit data and selects one from a plurality of inputs, and 48 is a plurality of registers in display memory. An 8-bit memory data bus (231-23 in FIG. 2) connects to one of the memory blocks (241-243 in FIG. 2) of each component provided.
3).

The operation shown in FIG. 4 will be explained.

To explain when the processor reads data from the display memory, at this time, only the inner gate 48c of the gates with control terminals shown in Fig. 4 is opened by the address and read signals shown in Fig. 2, and the others are gate 48a
, 48f, and 48g are in a closed state.

8-bit data of corresponding components is input from the memory data bus 48 to the data converter 40.

At this time, 8-bit data appears on internal bus 401 through gate 48e, but gate 48. A inhibit input is supplied to the control terminal (marked with ○), and the pro sensor data bus 21
is not output to . The 8 bits of the internal hash 401 are stored in a buffer 44 for write control (described later), and are also input to a comparator 42 where they are compared with preset 8 bit data in a register 43. Comparator 42
In this example, a match or a mismatch is detected, and the code generator 41 outputs "'00" and "11" according to the results. The comparison operation in this memory read is shown in A of FIG. ing.

Here, the comparator 42 can also determine whether it is large or small.

The 2-bit output from the code generator 41 is passed from the 2-bit wide bus 211 to the 2-bit position assigned to this color component on the 8-bit wide bus 21 through the game (to which no inhibit input is supplied) 48c. Output. (The bit allocation for each component is shown in Figure 3B.) A 2-bit code is generated from the data conharc- tion corresponding to each component, making a total of 6 bits of code, and 8-bit code data (2 bits) is generated. A total of 8 bits (including the bit additional code) are input to the processor from the processor data bus 21.

Note that the comparator 42. Register 43. The configuration of the code generator 41 is to identify whether the content of pixel data read from the display memory is the same as the content (color gradation) of a certain pixel data, and to detect a pattern of the same color. It is possible to identify whether a certain color pattern is inside or outside.

Next, the operation of the data converter 40 when writing from the processor to the display memory will be described. In this case, the address and write signals (processor 20 in FIG.
48g is opened by the Write signal from 1-48a, 48c, 48 with other control terminals
For the code data input from the 8-bit wide processor data bus 21 with f inhibited, two bits of the corresponding component are input to the data converter 40. The two bits are input from a two-bit wide bus 211 to converter 47 via gate 48d.

The 2-bit code data supplied to the data converter for each component is shown in FIG. 5B in this embodiment.

The converter 47 decodes the 2-bit data, selects one of a plurality of 8-bit data, and outputs it from the game) 48g (not prohibited during writing). In other words, the code data is “o o”
, "11'°, 8-bit data of the buffer 44 is output. This buffer stores the data on the internal bus 401 at the time of reading. If the code data is "ol" or "10" In this case, 8-bit data from register 45 or 46 is output, respectively.

The 8-bit data output from the data converter of each component is written into the block memory of each component shown in FIG. 2, respectively.

It is clear that the contents of the registers 43, 45, and 46 in FIG. 4 can be set by various means, and for example, the processor side can set necessary data corresponding to the operation.

In the configuration shown in FIG. 4, unidirectional data buses 401 and 402 are provided as internal data buses, but when the data converter 40 does not perform any conversion, that is, the 8-bit data from the processor data bus is directly transferred to this component. When writing to the memory block, only the gate 48f of the gates with control terminals is opened. For transfer in the opposite direction, gate 4 with control terminal
This is achieved by opening only 8a.

FIG. 6 is a processing flow for simultaneous reading (read) and simultaneous writing (write) in the simultaneous access area by the processor.

The operations at each step in FIG. 6 are as already described for the configuration of the embodiment, and the outline of the contents will be explained below.

In the read processing flow, the address of the simultaneous access area and a read signal are generated (step 60), and the pixel data at that address is output from each component memory block to the memory data bus (step 61).

Next, in step 62, the comparison operation and code data generation/output described with reference to FIGS. 4 and 5 are performed, and in the next step 63, the code data is input to the processor and comparison processing etc. be exposed.

The processing flow of write processing is as follows: When the processor generates the address and write signal of the simultaneous access area, and outputs the code data to the processor data bus (
64), the code data is input 2 bits at a time to the data converter for each component, converted to 8-bit data by the conversion operation explained in FIGS. 4 and 5 above, and then transferred to the memory data bus. It is output (65).

The output data of each memory data bus is written to the corresponding address of each corresponding memory block.

Furthermore, by combining read and write operations, for components to be rewritten, the values of registers 45 and 46 are written to the memory block of the corresponding component in the display memory, and for components not to be rewritten, the values are written to the memory block of the corresponding component. By writing a value of 44, only one or more specific components can be rewritten. Therefore, if this function is not used, there is no need to provide a buffer.

As described above, when the processor performs one memory access, the Red, 0reen, and Blue of one pixel are
Data of all components of UE can be processed simultaneously.

[Effects of the Invention] According to the present invention, there is provided a data conversion unit that performs data conversion between the processor and the display memory, and by accessing each part of the display memory at the same time, the processor can process all the components of one stroke of data. At the same time, high-speed processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of access areas and code data, and FIG. 4 is a configuration diagram of an embodiment of a data converter. FIG. 5 is a diagram showing an example of the structure of code data, FIG. 6 is a processing flow diagram, and FIG. 7 is an explanatory diagram of a conventional example. In Figure 1, 10: Processor 11: Processor data bus 12: Data converter 13: Memory data bus 14: Display memory Patent applicant Kazu Hosaka Patent attorney at BFNY Co., Ltd.Processing flow for simultaneous writing Simultaneous reading Process flow diagram

Claims (1)

[Scope of Claims] An image processing system in which a processor (10) accesses a display memory (14) having a data structure in which data of one pixel is divided into blocks according to red, green, and blue components, comprising: Data converter (12) between memory
A memory data bus (13) for simultaneously transferring pixel data of each block is provided between the display memory (14) and the data conversion section (12).
12) A bit-width processor data bus (11) is provided between them to transfer code data, and the data conversion unit (12) converts one pixel of code data handled by the processor and each component pixel data handled by the display memory. It is equipped with a mutual converter (121) that mutually converts between all the combined one pixel data, and the one pixel code data has a data amount that does not exceed the data amount of one pixel data of one component of the display memory. A display memory access method comprising: