JPS62151982A - Information processor - Google Patents

Abstract

PURPOSE:To realize the detection of a collision between specific graphics at high speed by slightly adding a hardware and hardly using a program step by automatically detecting the colision by a display control unit and requiring no operation of a central processing unit. CONSTITUTION:Signals 400, 410, 420 and 430, 440, 340 for selecting the output of 8 bits of a collision designating register 60 by 8 way selection circuits 71, 72 are display signals to a display. Accordingly, since the respective bits of the collision designating register 60 correspond to the respective colors of eight colors in 1:1, all '1' may be stored in the bit of the collision designating register 60 by considering the color displaying graphics in orde to monitor the collision of the specific graphics between three picture. Thereby, when the graphics monitoring the collision are registered on the same pixel position, a collision detecting signal 700 goes to '1' at the time when the pixel is displayed, the interruption is generated in the central processing unit according to an interruption request signal 802 and an interruption processing by the collision is performed.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to display control for a diffuser attached to an information processing device, and in particular to a display control method when it is possible to display multiple color screens at the same time. It is related to.

(Conventional technology) A conventional device of this type was constructed as shown in FIG.

The conventional example shown in FIG. 1 is an example in which a display capable of displaying m pixels has two screens capable of expressing eight colors. In FIG. 1, this conventional example includes a main memory unit 1 that stores instructions and data, and a central processing unit 2 that executes data processing according to instructions in the main memory unit 1.
The central processing unit 2 is connected to the system bus 0, which exchanges information between the main memory unit 1, the central processing unit 2, and various peripheral control units, and the system bus OIC data port. A display storage unit 3 that allows write and read access and stores mXfi bits of data for display on a display, and a display control unit that sequentially reads data in the display storage unit 3 and generates display display signals from the read data. It consists of 4. The display memory units 3 each have a display memory 30.32 having a storage capacity of m bits.
It consists of 6fIi1 display memories of ゜33.34.35, m bits in each display memory correspond one-to-one with m pixels that are the display range of the display, and display memories 30.31
, 32 constitutes the first screen, display memory 33°34.35 constitutes the second screen, and 3W is applied to each screen for each pixel.
Each bit in display memory of A is 3 bits in total, 23 or 8
It allows for the expression of colors. The display control unit 4 receives a clock signal 500 which is a basic clock for display control.
a clock generation circuit 50 that generates
1° 32.33, 34.35, respectively, and read data 300, 310° . . .
350 (8 bits each) as input data and clock signal 5
Shift registers 40, 41, whose operating clock is 00
42, 43, 44, 45, a read timing signal 460 to the display storage unit 3 is generated every 8 cycles of the clock signal 500, and the read data is transferred to the shift register 4.
Generates a load timing signal 461 for setting 0 to 45, and further outputs a load timing signal 461 from the central processing unit 2 to the display storage unit 3.
a display storage control circuit 46 that generates a write or read timing signal 460 to the display storage unit 3 in response to a write or read access request 200; and outputs 400 and 430 of the shift registers 40 and 43;
and a display signal synthesis circuit 47 that synthesizes the signals using a predetermined method and outputs a display signal 470 for the display.
Similarly, 410 and 440 are combined to produce a display signal 48.
0, 420 and 450, and outputs a display signal 490, respectively.

In the case of the conventional example with the above configuration, in order to detect that a specific figure, that is, a display with a specific color is located at the same pixel position in two screens, the schematic flow shown in Figure 2 is used. It is necessary for the central processing unit 2 to execute the indicated operation, which has the drawback of requiring a large amount of execution time and a large number of program steps.

(Objective of the Invention) 5. In order to eliminate these drawbacks, the present invention enables software to automatically detect collisions between specific figures.

(Structure of the Invention) In order to achieve the above object, the present invention further provides 24 pixels on a display consisting of m pixels in addition to the structure shown in FIG.
The display of colors (7 = 3 or 8 colors in Figure 1) is changed to 11 (first
In the figure, in an information processing device that is capable of simultaneously displaying n = 2, that is, 2 (m) off-screen images, a 2l-bit collision designation register, JXn pieces of data in the display storage unit, and the content of the collision designation register are used. A collision detection circuit detects whether specific figures overlap between any two screens on the n side, and an interrupt request signal is sent to the central processing unit upon detection of a collision in the collision detection circuit. It consists of a collision interrupt generation circuit that generates a collision interrupt.

Next, the present invention will be explained in detail by giving examples.

FIG. 3 shows one embodiment of the present invention, in which, in addition to the conventional example shown in FIG. An 8-bit collision designation register 60 that can be accessed for writing from the unit 2, 8-bit output signals 600 to 607 of the collision designation register 60, and output signals 400, 410 of the shift registers 40 to 45,
420, 430, 440°450, it is detected whether the color specified by the collision designation register 60 is displayed on any of the two screens, and the collision detection signal 700 is set to ``1'' in the former case.
", in the latter case, the collision detection circuit 70 outputs "0".
Then, the collision detection signal 700, the 1-bit data signal 800 from the system O, the interrupt mask setting signal 801 from the central processing unit 2, and the interrupt acceptance signal 803 are input signals, and the interrupt request signal 802 is processed by the central processing unit. The collision interrupt generation circuit 80 outputs to the unit 2. Fourth
The figure is a detailed diagram of the collision detection circuit 70, in which one of the 8-bit output signals 600 to 607 of the collision designation register 60 is
An 8-bit selection circuit 71 selects bits according to FIG.
, 440 and 450, the 8-way selection circuit 72 that selects according to FIG. It is composed of an AND gate 73. 6th
The figure is a detailed diagram of the collision interrupt generation circuit 80, in which 1-bit data 800 at a predetermined bit position among the 8-bit data on the system bus O is input as data (D input in the figure) to the central processing unit. A latch that uses the interrupt mask setting signal 801 generated from 2 to enable input (E input in the figure...the latch 81 is in the data through state during the "1" level, and the data hold state during the "θ'' level). 81, an AND gate 82 which takes the AND of the negative output 804 of the latch 81, and the collision detection signal 700, and an output signal 805 of the AND gate 82, which is clocked manually (CL in the figure).
K input...Since the D input is always 1'', the 7 lip-flop 83 is set at the rising edge of the CLK input), and the interrupt acceptance signal 803 from the central processing unit 2 is used as the clear input (CLR input in the figure). A flip-flop 83 outputs an interrupt request signal 802 to the central processing unit 2.The latch 81 is in a set state to mask collision interrupts, and the signal 80 is output only when in a reset state.
4 becomes ``1'' and the collision detection signal 700 becomes 1'', an interrupt request signal 802 is output, and when the signal 802 is accepted by the central processing unit 2, the interrupt acceptance signal 803 becomes 1''. The 7-lip flop 83 is cleared, the interrupt request signal 802 becomes 'θ'', and from then on, interrupt processing due to collision is performed by the central processing unit. Here, signals 400, 410, 420 and 43 select the output of the 8th bit (y) of the collision designation register 60 by the 8th bit selection circuit 71, 72.
0°440.450 is also a display signal to the display, and its display color is determined as shown in Table 1. Therefore, each bit of the collision designation register 60 has a one-to-one correspondence with each of the eight colors as shown in Table 1, so in order to monitor collisions between specific figures between two screens, Thinking about which color those figures will be displayed in, the bits of the collision designation register 60 corresponding to those colors are all set to 11''.
All you have to do is store it. As a result, when the figures to be subjected to collision monitoring overlap at the same pixel position, the collision detection signal 700 becomes 1'' at the time when that pixel is displayed.
An interrupt is generated in the central processing unit 2 by the interrupt request signal 802, and an interrupt process due to a collision is performed.

Number of screens: 2 (n=2), number of displayable colors: 8 CI=3
), but if the value of ``+l'' is 3 or more and 4 or more, respectively, the collision detection register in this embodiment is 2l bits and has one, and the 8-way selection circuit ( 7
1, 72) as 2l ways, and in place of the AND gate 73, there is a circuit that detects that two or more bits out of the n bits output from the nl 8 way selection circuit are 1. Yes, it is possible.

(Effects of the Invention) As explained above, according to the present invention, collision detection is automatically performed by the display control unit 4, and there is no need for any operation in the central processing unit 2 as shown in FIG. Therefore, there is an advantage that by adding a small amount of software, collisions between specific figures can be detected at high speed and with almost no program steps.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a flowchart showing the operation of the central processing unit 2 in the conventional example, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 5 is a detailed diagram of the collision detection circuit 70 of FIG. 4, FIG. 5 is a diagram explaining the operation of the 8-way selection circuits 71 and 72 of FIG. . 1...Storage unit, 2...Central processing unit, 3...Display storage unit, 4...-
... Display control unit, 40-45 ... Shift register, 46 ... Display storage control circuit, 47
~49...Display signal synthesis circuit, 50...
・Clock generation circuit, 60...Collision detection register, 70...Collision detection circuit, 71, 72...-
80... 8-way selection circuit, 73...--AND gate, 80... Collision interrupt generation circuit, 81...
...Latch, 82...And gate, 83.
·····flip flop. Cow-S concave (kanii/it: 8 way 2 king ni' times swamp) 7/ no entry/exit Gui 3 j; 8 siei hawk (-tK8 straddle 72 people n signal

Claims (1)

[Scope of Claims] A main memory unit that stores instructions and data, a central processing unit that processes data according to the instructions in the main memory unit, and a display that can be accessed for writing and reading from the central processing unit. 1, which is a display unit of the display, includes a display storage unit that stores data for display on the display, and a display control unit that sequentially reads data in the display storage unit and generates a display display signal from the read data. The display storage unit has a storage capacity consisting of n areas each having m sets of m sets of l bits in the display storage unit corresponding to each pixel on a one-to-one basis;
In an information processing device capable of simultaneously displaying a 2^l color display for n screens on a display consisting of a total of m pixels, the display control unit includes 2 memory cells that can be accessed for writing by the central processing unit. Read out 1 bit out of 2^l bits of the collision designation register using the ^l-bit collision designation register and the 1-bit data constituting one pixel in the display storage unit for each n screen for each pixel. a collision detection circuit that detects that two bits of read data between two screens are both predetermined values; and an interrupt is sent to the central processing unit upon the detection by the collision detection circuit. An information processing device comprising: a collision interrupt generation circuit that generates a request signal.