JPH06215560A - Memory integrated circuit for video display - Google Patents

Abstract

PURPOSE:To speedingly process a rectangular region transfer of video data. CONSTITUTION:When the data, which are equivalent to one line stored in the transfer origin region of a memory cell array 1, are transferred to a transfer destination region, the data, which are equivalent to one line and are read from the transfer origin region, are selected by a transfer gate 6 in accordance with input output select signals 101 and are outputted to serial ports 7a to 7d or an arithmetic and logic circuit 9. The circuit 9 performs arithmetic operations instructed by arithmetic operation select signals 104 against the one line data from one of the serial ports 7a to 7d selected by a selector 8 and the one line data from one of the other serial ports 7a to 7d or the data which are equivalent to one line and inputted from the memory cell array 1 through the transfer gate 6. The results of the operations are outputted to the memory cell array 1 or the serial ports 7a to 7d through the transfer gate 6.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to memory integrated circuits for video display and more particularly to bit transfer operations in bitmap graphic displays.

[0002]

2. Description of the Related Art Conventionally, in this type of bit transfer operation, data read from a VRAM memory cell array is subjected to a bit transfer operation by a bit transfer operation circuit, and the operation result is written in the memory cell array. .

In this case, the data in the memory cell array is once read out through the input / output buffer, and the bit transfer operation circuit performs the bit transfer operation on the read data. Then, the operation result of the bit transfer operation circuit is written in the memory cell array via the input / output buffer.

As described above, since data is written in and read from the memory cell array via the input / output buffer, the transfer unit is about byte (8 bits) to longword (32 bits). Therefore, it takes a long time to perform the bit transfer calculation process on the data in the memory cell array.

[0005]

In the above-mentioned conventional bit transfer arithmetic circuit, data write / read occurs in the memory cell array of the VRAM every time one arithmetic operation is performed,
Moreover, since the amount of data that can be processed at one time is about 32 bits, there is a problem in that the bit transfer calculation process takes time, and even if an LSI dedicated to the bit transfer calculation is used, the process takes too long.

For example, in a bit map display, a rectangular area of video data must be transferred at high speed in order to support multi-window, but this rectangular area is transferred using the bit transfer arithmetic circuit. Therefore, the bit processing amount that can be handled at one time is about 32 bits.

Therefore, if an attempt is made to increase the amount of bit processing that can be handled at one time, the circuit becomes large in scale and the number of bits increases, so that a memory chip is required in excess of the memory capacity, and the cost increases. is there.

Therefore, it is an object of the present invention to provide a video display memory integrated circuit which can solve the above-mentioned drawbacks and can process a rectangular area transfer of video data at high speed.

[0009]

A video display memory integrated circuit according to the present invention includes a memory cell array, an input / output buffer for inputting / outputting data to / from the outside when writing to and reading from the memory cell array. A video display memory integrated circuit including a serial buffer for storing data of one line of the memory cell array when displaying data of the memory cell array, wherein the video display memory integrated circuit includes: A plurality of holding means for holding one line of data, a computing means for performing a computation on the one line of data held in the plurality of holding means in response to an external command, and a computation result of the computing means And means for controlling writing to the transfer destination of the memory cell array.

[0010]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, V according to an embodiment of the present invention
When writing data to the memory cell array 1 in the RAM, the addresses A0 to A9 input and held in the address input buffer 2 are decoded by the column decoder 3 and the row decoder 4 and supplied to the memory cell array 1. The data input via the input / output buffer 5 is written in the memory cell array 1.

When data is read from the memory cell array 1, the addresses A0 to A9 input and held in the address input buffer 2 are decoded by the column decoder 3 and the row decoder 4, respectively, and the memory cell array 1 is read.
Data is read out from the memory cell array 1 via the input / output buffer 5 and output in word units or byte units.

Further, when the display data is read from the memory cell array 1, the addresses A0 to A9 inputted and held in the address input buffer 2 are respectively decoded by the column decoder 3 and the row decoder 4 to be decoded.
Data of one line read from the memory cell array 1 is held in the serial port 11.

The data held in the serial port 11 is read by the address supplied from the address counter 10 and output as display data through the input / output buffer 12 and the data line 105. Here, the address counter 10 has addresses A0 to A9 held in the address input buffer 2 and a serial clock (SC) from the outside.
An address is generated from 103 and output to the serial port 11.

On the other hand, when the data stored in the transfer source area of the memory cell array 1 is transferred to the transfer destination area, the data for one line read from the transfer source area is transferred via the transfer gate 6 to the serial ports 7a to 7d. Alternatively, it is output to the arithmetic circuit 9. The transfer gate 6 serves as an output destination of data from the memory cell array 1 in accordance with an input / output select signal 101 from the outside, and serves as a serial port 7a to 7a.
One of d and the arithmetic circuit 9 is selected.

In addition, the transfer gate 6 serves as a data output destination of the memory cell array 1 and a serial port 7
When a to 7d are selected, which of the serial ports 7a to 7d holds the data is determined by a serial port select signal 102 from the outside.

The arithmetic circuit 9 receives data for one line from one of the serial ports 7a to 7d selected by the selector 8 and one line from another one of the serial ports 7a to 7d. Data or transfer gate 6
The calculation is performed with the data for one line from the memory cell array 1 input via the.

That is, the arithmetic circuit 9 performs an arithmetic operation on the above-mentioned data for one line instructed by the arithmetic select signal 104 from the outside, and the arithmetic result is transferred via the transfer gate 6 to the memory cell array 1 or the serial port 7a. Output to ~ 7d.

As a result, the data for one line read from the transfer source area of the memory cell array 1 is subjected to at least bit unit shift processing or bit unit mask processing in the arithmetic circuit 9 and written in the transfer destination area. Be done. In this case, the data used for the arithmetic operation of the arithmetic circuit 9 and its arithmetic contents are designated by the input / output select signal 101, the serial port select signal 102 and the arithmetic select signal 104.

FIG. 2 is a diagram showing the types of calculations in the calculation circuit 9 of FIG. In the figure, the operation select signal 10
4 shows the correspondence between the contents of 4 (hereinafter, referred to as operation select bit) and the operation processing in the operation circuit 9. Where S
1 and S2 indicate source numbers.

When the operation select bit is "0000", the operation circuit 9 performs the operation of item No. 0, and the operation circuit 9 outputs the inverted value of S1. When the operation select bit is "0001", the operation circuit 9 performs the operation processing of item No. 1, and the operation circuit 9 outputs the inverted value of the logical sum of S1 and S2.

When the operation select bit is "0010", the operation circuit 9 performs the operation of item 2, and the operation circuit 9 outputs the result of the logical product of the inverted value of S1 and S2. When the operation select bit is "0011", the operation circuit 9 performs the operation process of item No. 3, and the operation circuit 9 outputs "0".

When the operation select bit is "0100", the operation circuit 9 performs the operation of item No. 4, and the operation circuit 9 outputs the inverted value of the result of the logical product of S1 and S2. When the operation select bit is “0101”, the operation circuit 9 performs the operation process of item No. 5, and the operation circuit 9 sends the S
The inverted value of 2 is output.

When the operation select bit is "0110", the operation circuit 9 performs the operation of item No. 6, and the operation circuit 9 outputs the result of the exclusive OR of S1 and S2. When the operation select bit is "0111", the operation circuit 9 performs the operation process of item No. 7, and the operation circuit 9 sends the S
The result of the logical sum of 1 and the inverted value of S2 is output.

When the operation select bit is "1000", the operation circuit 9 performs the operation of item No. 8, and the operation circuit 9 outputs the result of the logical sum of the inverted value of S1 and S2. When the operation select bit is "1001", the operation circuit 9 performs the operation process of item No. 9, and the operation circuit 9 sends the S
The inverted value of the result of the exclusive OR of 1 and S2 is output.

When the operation select bit is "1010", the operation circuit 9 performs the operation of item No. 10, and the operation circuit 9 outputs S2. Operation select bit is "1"
In the case of 011 ", the arithmetic circuit 9 performs the arithmetic processing of item No. 11, and the arithmetic circuit 9 outputs the result of the logical product of S1 and S2.

When the operation select bit is "1100", the operation circuit 9 performs the operation of item No. 12, and the operation circuit 9 outputs "1". When the operation select bit is "1101", the operation circuit 9 performs the operation of item No. 13, and the operation circuit 9 outputs the result of the logical sum of the inverted values of S1 and S2.

When the operation select bit is "1110", the operation circuit 9 performs the operation of item No. 14, and the operation circuit 9 outputs the result of the logical sum of S1 and S2. If the operation select bit is "1111", the operation circuit 9
Then, the calculation process of item No. 15 is performed, and S1 is output from the calculation circuit 9.

Further, the arithmetic circuit 9 is provided with a barrel shift circuit (not shown) having a ring-shaped shift function,
The shift amount and shift direction in this barrel shift circuit can be specified from the outside.

FIG. 3 is a diagram showing an example of a system using the VRAM shown in FIG. In the figure, a CPU 21 is connected to a graphic display controller 22 and a bitmap controller 23 via an address bus 110 and a data bus 111. The graphic display controller 22 and the bitmap controller 23 are connected to the OP VRA via the image bus 112.
M20 is connected.

Operation control of the OP VRAM 20 is performed by the CPU 2
1 is not controlled directly, but by the bitmap controller 23. That is, when the CPU 21 commands the bitmap controller 23 to calculate and transfer a rectangular area, the bitmap controller 23 outputs C
The instruction from the PU 21 is converted into control for the OP VRAM 20, and the input / output select signal 1 is sent via the control line 114.
01, the serial port select signal 102, and the operation select signal 104 are output to the OP VRAM 20 for control.

The graphic display controller 22 executes the graphic drawing and the sending of the control signal to the CRT display 25, and the bitmap controller 23 and the OP VRAM 20 execute the transfer of the rectangular area.

Graphic display controller 2
2 from the control signal via the control line 114 OP VRA
When output to M20, this control signal causes OP V
The data read from the RAM 20 is converted into analog data by the serial / parallel converter 24 and displayed on the CRT display 25.

FIG. 4 is a diagram showing transfer of a rectangular area according to an embodiment of the present invention. The transfer processing of the rectangular area according to the embodiment of the present invention will be described with reference to FIGS. The case where the data in the transfer source areas S1 and S2 is OR-operated and written in the transfer destination area D1 will be described below.

First, the CPU 21 starts the start address (x1,
y1), width HL bits, vertical 3 bits of rectangular area S1 data and start address (x2, y2) horizontal width HL bits, vertical 3 bits of rectangular area S2 data are ORed to start address (x3, y3), width HL bit, height 3
When the bitmap controller 23 is instructed to write in the rectangular area D1 of bits, the bitmap controller 23 controls the OP VRAM 20 as follows.

The bit map controller 23 operates on one line of data including the start address (x1, y1).
The data is read from the memory cell array 1 of the VRAM 20. The bitmap controller 23 controls the transfer gate 6 and the serial ports 7a to 7d by the input / output select signal 101 and the serial port select signal 102,
The data read from the memory cell array 1 is transferred to the serial port 7a.

The bit map controller 23 controls the arithmetic circuit 9 to shift the data held in the serial port 7a by "x3 -x1" bit by bit. The bitmap controller 23 controls the transfer gate 6 and the serial ports 7a to 7d by the input / output select signal 101 and the serial port select signal 102,
The data shifted by "x3 -x1" is transferred to the serial port 7a.

Next, the bit map controller 23 reads the data for one line including the start address (x2, y2) from the memory cell array 1 of the OP VRAM 20.
Bitmap controller 23 uses input / output select signal 1
01 and the serial port select signal 102 control the transfer gate 6 and the serial ports 7a to 7d to transfer the data read from the memory cell array 1 to the serial port 7b.

The bit map controller 23 controls the arithmetic circuit 9 to shift the data held in the serial port 7b by "x3 -x2" bit by bit. The bitmap controller 23 controls the transfer gate 6 and the serial ports 7a to 7d by the input / output select signal 101 and the serial port select signal 102,
The data shifted by "x3 -x2" is transferred to the serial port 7b.

In this case, x3> x1 and x3 <x2
Therefore, the data transferred to the serial port 7b is shifted in the opposite direction to the data transferred to the serial port 7a.

When the bit-wise shift processing is completed, the bitmap controller 23 outputs "1110" as the operation select signal 104, and the operation circuit 9 holds the data held in the serial port 7a and the serial port 7b. OR operation with the data obtained.

The bit map controller 23 outputs the calculation result of the calculation circuit 9 to 0 to (x3 -1) and (x3 + HL).
~ CA is "0" and x3 ~ (x3 + HL-1) is "1"
Then, the data is masked with the mask data of and written in the rectangular area D1. At this time, one line of data including the start address (x3, y3) remains in the portion where the mask data is "0", and the result of the OR operation in the arithmetic circuit 9 in the portion where the mask data is "1". Is written.

The bitmap controller 23 repeatedly executes the above processing until the processing for the data of three lines is completed, and the result of the OR operation between the data of the rectangular area S1 and the data of the rectangular area S2 is obtained as the rectangular area D1. The process of writing to is completed.

As described above, when data is transferred between the transfer source and the transfer destination in the memory cell array 1, the data for one line read from the memory cell array 1 is held in the plurality of serial ports 7a to 7d, and the serial port The arithmetic circuit 9 performs a multi-bit operation instructed by the operation select signal 104 on the data held in 7 a to 7 d and the data for one line read from the memory cell array 1, and the operation result is stored in the memory cell array 1. By writing the data to the transfer destination, the operations for the data of one line can be processed at one time, and since they are processed in the same IC, they can be processed at high speed.

Therefore, rectangular area transfer of video data in a bit map display or the like using a multi-window system can be processed at high speed.
In this case, since the arithmetic circuit 9 is installed in the VRAM, the amount of hardware in the system will not be increased.

[0046]

As described above, according to the VRAM of the present invention, a plurality of holding means for holding one line of data read from the memory cell array during data transfer between the memory cell arrays and a plurality of holding means. A rectangular area of the video data is transferred by controlling the write operation result of this operation means to a transfer destination of the memory cell array. There is an effect that it can be processed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing types of calculations in the calculation circuit of FIG.

3 is a diagram showing an example of a system using the VRAM shown in FIG.

FIG. 4 is a diagram showing transfer of a rectangular area according to an embodiment of the present invention.

[Explanation of symbols]

 1 memory cell array 6 transfer gates 7a to 7d, 11 serial port 8 selector 9 arithmetic circuit 101 input / output select signal 102 serial port select signal 104 arithmetic select signal

Claims (3)

[Claims] 1. A memory cell array, an input / output buffer for inputting / outputting data to / from the external when writing and reading to / from the memory cell array, and a memory cell array for displaying data in the memory cell array. A video display memory integrated circuit including a serial buffer for storing data for one line, comprising: a plurality of holding means for holding data for one line of the memory cell array during data transfer in the memory cell array; Arithmetic means for performing an arithmetic operation on the data for one line held in the plurality of holding means in response to a command; and means for controlling the arithmetic result of the arithmetic means to be written to a transfer destination in the memory cell array. A video display memory integrated circuit having. 2. The operation means performs at least a bit-unit shift and a bit-unit mask on the data for one line held in the plurality of holding means according to a transfer destination in the memory cell array. The video display memory integrated circuit according to claim 1, wherein the video display memory integrated circuit is implemented. 3. The video display according to claim 1 or 2, wherein the plurality of holding means holds the transfer source data and the transfer destination data in the memory cell array, respectively. Memory integrated circuit.