JPH05225348A - Drawing processor - Google Patents

Abstract

PURPOSE:To improve the drawing speed by omitting the start of a reading cycle to a bit map when a certain bit on the bit map is rewritten by a drawing processor. CONSTITUTION:A drawing processor 101 outputs the write data and the mask data in a writing cycle start mode. The bit number of the mask data is equal to that of a data bus and outputted through a mask output terminal 108. An external circuit can perform the control to decide whether each bit of the write data should be written in a memory chip or not by means of a mask signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drawing processor which is used in a digital image processing apparatus having a bitmap memory and which reads and writes data in the bitmap memory.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings.

FIG. 5 shows a drawing processor 5 according to the prior art.
This is a configuration example of 01. The drawing processor has 8-bit data input / output signals D0-D7 502, RD * 503 indicating that the read cycle is being activated, and WR * signal 504 indicating that the write cycle is being activated. .. Here, * at the end of the terminal name indicates that the terminal signal has negative logic.

Further, an 8-bit drawing arithmetic unit 505 and an 8-bit drawing mask generator 506 are mounted inside.
The drawing calculator rewrites the data read via the data bus and outputs it again on the data bus. The drawing mask generator, when the drawing arithmetic unit rewrites the data,
A drawing mask for instructing the drawing operation unit of "bits that must be rewritten" and "bits that must not be rewritten" is generated and given to the drawing operation unit. Reference numeral 507 is an internal mask bus for giving a drawing mask.

FIG. 6 shows the operation of input / output signals when the drawing processor activates a bus cycle. Figure 6
6A shows a read cycle, and FIG. 6B shows a write cycle. The operation of FIG. 6 will be described with reference to FIG. FIG. 7 is an example of a graphics device configuration using the drawing processor of FIG.

The drawing processor and a memory chip, which is a component of the bitmap, are connected by an 8-bit data bus. The drawing processor supplies RD *, WR * to the memory chip. Memory chip is RD *
Use the signal as the data output enable signal OE *,
The WR * signal is used as the write enable signal WE *.

In the read cycle of FIG. 6A, after the data buses D0 to D7 are set to high impedance,
Activate RD *. The memory responds to this,
Definite data continues to be output on the data buses D0-D7 while the OE * signal is active. At the rising edge of RD *, the drawing processor
Latch the data.

On the other hand, in the write cycle of FIG. 6B, WR * is activated after the definite data is output on the data buses D0-D7. In response, the memory latches the write data on the falling edge of WE *.

Now, a procedure for drawing one dot using the graphics device of FIG. 7 will be described.

As an example, consider a 640 dot × 400 dot bitmap memory. Since the horizontal direction is 640 bits, it is 80 bytes when converted into bytes. The entire bitmap occupies a memory space of 32000 bytes (= 80 × 400). FIG. 8A is a schematic diagram in which this is assigned to the real address space. No. 0 MS
B corresponds to the upper left one dot of the bitmap. It is assumed that the contents of this bitmap memory are all X as shown in FIG. Where X is 0 or 1
It means to take either value of.

Now, consider the case where the MSB at address 81 on the bitmap memory is rewritten to 1. In other words, consider a case where the state of FIG. 8 (B) is changed to the state of FIG. 8 (C). This is 9 from the left on the bitmap memory
It can be considered to be drawing for the dot and the dot located at the second dot from the top. The important point is that the 7 bits other than the MSB in the address 81 cannot be rewritten.

Therefore, the conventional drawing processor takes the following steps. This will be described with reference to FIG.

First, an 8-bit drawing mask is generated.
This is data in which only the MSB is 0 and the remaining 7 bits are 1. "0" means that it is the target of the drawing calculation, and "1" means that it is not the target of the drawing calculation. Next, the bitmap data at address 81 is read. "Drawing mask generation" and "Read out address 81"
May be performed simultaneously or in reverse order.
When the drawing mask and the bitmap data are available, the drawing operation unit follows the drawing mask's instructions.
The data in which only the MSB in the data is rewritten to 1 is output as the operation result. Finally, the calculation result is written back to address 81.

In conclusion, when the conventional drawing processor draws one dot, it is necessary to activate two bus cycles (one read cycle and one write cycle).

[0015]

However, when the conventional drawing processor draws one dot, two bus cycles must be activated. The above example
Although it was drawn with one dot, the situation is the same when rewriting a plurality of dots existing in one byte. At least two bus cycles must be activated. When drawing 1 dot, only 1 bit in 1 byte is 0
However, when rewriting a plurality of dots, the drawing mask data in which at least 2 bits are 0 is generated, and the drawing operation is executed based on the drawing mask data. Only the drawing mask value is changed, and the number of times of indispensable bus cycle activation is not reduced.

In view of the above-mentioned drawbacks, the technical problem of the present invention is that when the drawing processor rewrites a certain bit on the bitmap, the read cycle activation for the bitmap is not required and the drawing speed is improved. It is to provide the drawing processor.

[0017]

A drawing processor of the present invention is a data having a width of N bits (N is an integer of 2 or more) for collectively reading and writing a plurality of bits on a bit map memory. -When a bus and N-bit data are collectively subjected to a drawing operation, a drawing mask generation is performed to generate N-bit drawing mask information for distinguishing between a target bit for drawing operation and a non-target bit. And a drawing operation unit for executing a drawing operation on the N-bit data according to the N-bit drawing mask information, and when writing the operation result of the drawing operation unit to the bitmap memory, The drawing mask generator outputs the N-bit drawing mask information to the outside.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a drawing processor 1 according to the prior art.
This is a configuration example of 01. The drawing processor has 8-bit data input / output signals D0-D7 102, RD * 103 indicating that the read cycle is being activated, and WR * signal 104 indicating that the write cycle is being activated. .. Here, * at the end of the terminal name indicates that the terminal signal has negative logic. Also, an 8-bit drawing calculator 10
A 5-, 8-bit drawing mask generator 106 is mounted inside. The drawing calculator rewrites the data read via the data bus and outputs it again on the data bus. The drawing mask generator is a "bit that must be rewritten" when rewriting the data read by the drawing calculator.
And a drawing mask for instructing the drawing arithmetic unit of "bits that should not be rewritten". 10
Reference numeral 7 is an internal mask bus for giving a drawing mask. This drawing mask is supplied to the drawing arithmetic unit and simultaneously output to the outside of the drawing processor via the mask output terminals M0 to M7 108.

The operation of the input / output signals when the drawing processor starts the bus cycle is shown in FIG. Figure 2
2A shows a read cycle, and FIG. 2B shows a write cycle. 2A and 2B both show the bus cycle of the drawing processor according to the conventional technique.
It is almost the same as (A) and (B). The difference is light
In the cycle, the mask data is output onto the mask buses M0 to M7. In the write cycle, definite data is output on the data buses D0-D7,
Also, after outputting the definite mask data on the mask buses M0 to M7, WR * is activated. An example of the configuration of a graphics device using this mask data is shown in FIG.
Shown in.

The configuration example of FIG. 3 is almost the same as the configuration example of FIG. The only differences are the following: In FIG. 7, the WR * signal output by the drawing processor is directly changed to W.
It is supplied to all memory chips as an En * signal (n = 0, 1, 2, 3, 4, 5, 6, 7).

On the other hand, in FIG. 3, a signal obtained by negatively ANDing the WR * signal and the Mn signal is supplied to each memory chip as the WEn * signal. Therefore, in the write cycle, the data bus D0-
The 8-bit write data output on D7 is
Whether or not each of the eight memory chips latches
It can be controlled by the drawing processor itself. In other words, the drawing processor itself can control whether or not to write the data Dn to the memory chip n.

Now, the procedure for drawing one dot using the graphics device of FIG. 3 will be described. In order to clarify the difference from the prior art, consider the case where the state of FIG. 8 (B) is changed to the state of FIG. 8 (C) as in the description of the prior art. That is, 640 dots x 400
FIG. 8A is a schematic diagram in which a dot bit map memory is considered and allocated to the real address space. Consider the case where the MSB at address 81 on the bitmap memory is rewritten to 1. 7 bits other than MSB in address 81 must not be rewritten. All these assumptions are exactly the same as the assumptions in the description of the prior art.

The drawing processor of the present embodiment rewrites the MSB at address 81 on the bitmap memory to 1 by the following procedure. First, an 8-bit drawing mask is generated.
This is data in which only the MSB is 0 and the remaining 7 bits are 1. "0" means that it is the target of the drawing calculation, and "1" means that it is not the target of the drawing calculation.

Next, this drawing mask is used as a mask bus M0.
-D that is the MSB of the data bus that outputs to M7
The write value 1 is output to 7. The D0-D6 output values are indefinite. If WR * is activated in this state, M0
-M6 output values are all 0, so WE0 * -WE6 * all remain inactive. Only WE7 * is active. The memory chip 7 latches the data D7 and the data from the memory chip 0 to the memory chip 6 is 7
Chips do not latch the data on D0-D6. That is, only the memory of the memory chip 7 is rewritten,
The memory contents from memory chip 0 to memory chip 6 do not change. The MSB of address 81 becomes 1, and bits other than the MSB of address 81 do not change.

As described above, the MSB at address 81 is set to 1
The bus cycle required to rewrite
Only cycles. It is not necessary to read address 81.

As a counterargument to this embodiment, the existence of the following prior art may be pointed out. That is,
It is a drawing processor that outputs mask data in an encoded format. This is to notify the outside of the drawing target dot position within one byte by outputting three address signals (hereinafter referred to as dot address signals). In light of this embodiment, 81
The MSB of the address should output "7" as the dot address value. If this dot address signal is externally decoded and supplied to the memory chip, as in this embodiment, only 1 in 1 byte can be written in a write cycle.
Bits can be rewritten.

However, the drawing target bit in one byte that can be designated by this dot address signal is only one bit. If the drawing target bit is 2 bits or more, the dot address signal cannot handle it. An example in which the drawing target bit is 2 bits or more will be described with reference to FIG. 4 (A), (B), (C), and (D) each schematically show the figure drawn on the bitmap memory.

The rectangular data of FIG. 4A is used as a source, and the rectangular data of FIG.
(B) will be called a destination. Figure 4
Consider the case where the source shown in FIG. 4A and the destination shown in FIG. 4B are stored in different locations on the memory, and the source is transferred to the position where the destination is stored in a bit block. At this time, if the destination is simply rewritten with the source, the drawing result as shown in FIG. 4D is obtained as the new destination. this is,
FIG. 4B shows a window, and it can be considered that the character “F” is drawn on the window. But,
The graphics application often does not want the drawing result as shown in FIG. Rather, FIG. 4 (C)
I want a drawing result like. That is, the source of FIG. 4A is a recognition that only the foreground representing the letter “F” has meaning and the background is “transparent”.
Only the bits belonging to the foreground of the source are rewritten at the source, and the bits belonging to the background remain as they are without being rewritten. Such processing will be referred to as transparent bit block transfer.

The drawing processor of the present invention is very effective in performing transparent bit block transfers.
This is because it is highly likely that multiple "bits that must be rewritten" and "bits that must not be rewritten" will exist within one byte. The drawing processor of the present invention can complete the processing per byte in a read cycle for the source and a write cycle for the destination, which is a total of 2 bus cycles.

On the other hand, in the case of execution by the conventional processor, the read cycle for the source and the read cycle for the destination are added to the processing per byte.
Cycle, write cycle for destination, total of 3 bus cycles are required.

[0032]

As described above, the present invention has the following effects on the graphics device. One is the improvement in processing speed, and the other is the economic efficiency when constructing a graphics device.

First, the improvement of the processing speed will be described.

Consider the one-dot drawing process. In the conventional drawing processor, it takes two bus cycles to draw one dot. On the other hand, if the drawing processor of the present invention is used, one dot can be drawn in one bus cycle. Since the number of bus cycle activations is halved, the processing speed is 2
Double. The one-dot drawing can be applied to all line drawing processing of a one-dot width such as a straight line and an arc.

Now consider transparent bit block transfers. It takes 3 to transfer 1 byte in the conventional drawing processor.
A bus cycle was needed. On the other hand, if the drawing processor of the present invention is used, one byte can be drawn in two bus cycles. Since the number of bus cycle activations is two-thirds, the processing speed is 1.5 times. As described above, the transparent bit block transfer greatly affects the performance of character drawing. The graphics cursor drawing that follows the movement of the mouse is also a transparent bit block transfer. Character drawing,
Graphics cursor drawing has a large weight in determining the processing speed of a graphics application.

Based on these facts, the performance improvement when the drawing processor of the present invention is used will be estimated. When the graphics application runs on the graphics device, it is assumed that the line drawing time, the transparent bit block transfer time, and the other processing time ratio in the total graphics processing time are 40%: 40%: 20%. Then, 40% × 2 + 40% × 1.5 + 20% × 1 = 80% + 60% + 20% = 160%. This means that the graphics application will run 1.6 times faster.

Next, economic efficiency will be described.

A comparison of FIG. 3, which is a graphics device using the drawing processor of the present invention, with FIG. 7, which is a graphics device using the drawing processor of the prior art,
The components of the graphics device are almost the same.
Therefore, the above-described performance improvement can be realized without increasing the cost of the graphics device. However, in the case of constructing the device as shown in FIG. 3, there is a concern that a capacity larger than the bitmap memory capacity originally required by the graphics device may have to be added. The details will be described.

In recent years, the number of data terminals included in a memory chip tends to increase as the degree of integration increases. This tendency is particularly remarkable in DRAM, and DRA having 8 or 16 data terminals
M has also been commercialized. In fact, the memory chip used as the bitmap memory is most often DRAM. Alternatively, a dual port DRAM (hereinafter referred to as V
(Also called RAM) has been used more often. Although the number of data terminals is increasing in these chips, there is only one WE * input terminal. An exception is a DRAM with 16 data terminals and 2 WE * input terminals.
Has been commercialized. Therefore, when the bit map memory capacity required as a graphics device is small, the same number of DRs as the bit width of the data bus is used.
The graphics device of FIG. 3, which requires an AM chip, can sometimes be uneconomical.

Such a situation can be solved by utilizing the "write per bit" function. "Write per bit" is a general name, and DRAMs and VRAMs having many data input / output terminals are often equipped with this function. This is a function that is conscious of its application to bitmaps. Mask data is time-divisionally input from the data input / output terminal of the memory chip, and whether or not the data is latched by the memory chip is determined for each data terminal. It can be controlled. By supplying the mask data output by the drawing processor of the present invention to the memory chip equipped with the write perbit function, a memory chip having 8 or 16 data terminals can be used. Therefore, it is possible to avoid a situation in which a capacity larger than the bitmap memory capacity originally required by the graphics device has to be added. It is also possible to construct an economical graphics device that is expected to improve performance.

[Brief description of drawings]

FIG. 1 is a configuration example of a drawing processor according to the present invention.

FIG. 2 is a timing diagram of a bus cycle activated by the drawing processor of FIG. 2A shows a read cycle, and FIG. 2B shows a write cycle.

3 is an example of a graphics device configuration constructed by connecting the drawing processor of FIG. 1 to a memory chip.

FIG. 4 is a schematic representation of a graphic drawn in a bitmap memory.

FIG. 5 is a configuration example of a drawing processor according to a conventional technique.

6 is a timing diagram of a bus cycle activated by the drawing processor of FIG. 6A shows a read cycle, and FIG. 6B shows a write cycle.

7 is an example of a graphics device configuration constructed by connecting the drawing processor of FIG. 5 to a memory chip.

FIG. 8 is a diagram showing a relationship between a bitmap of 640 dots in the horizontal direction and 400 dots in the vertical direction, addresses, and data. FIG. 8A shows the real address assigned to the bitmap. FIG. 8B shows data values stored on the same bitmap. FIG. 8C is the same as FIG. 8B.
For the data storage state of, at the MSB position of address 81,
Indicates the state where the value 1 is written.

FIG. 9 is a diagram for explaining the procedure of a conventional drawing processor.

[Explanation of symbols]

 101 drawing processor 102, 502 data input / output signal D0-D7 103 output signal RD * 104 indicating read cycle activation WR * 105 drawing arithmetic unit 106 drawing mask generator 107, 507 internal mask Bus 108 Mask output terminals M0-M7 501 Drawing processor 503 Output signal RD * 504 indicating read cycle activation WR * 505 Drawing arithmetic unit 506 Drawing mask generator

Claims (1)

[Claims] 1. A data bus having a width of N bits (N is an integer of 2 or more) for collectively reading and writing a plurality of bits on a bit map memory, and the N bits of data collectively. And a drawing mask generator for generating N-bit drawing mask information for identifying a target bit and a non-target bit in the drawing operation, and the N-bit data. A drawing arithmetic unit that executes a drawing operation according to the N-bit drawing mask information, and an N-bit drawing output by the drawing mask generator when the calculation result of the drawing arithmetic unit is written to the bitmap memory. A drawing processor having means for outputting mask information to the outside.