JPS61176972A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention 1] The present invention relates to an image display device having a bitmap memory.

[Technical Background of the Invention] In recent years, as the amount of data processed by computers has increased, there has been a growing demand for increased capacity of image display devices and for faster display and drawing.

Generally, image display devices that perform graphic processing and image processing are equipped with a bitmap memory in which each bit corresponds to one dot on the screen.

FIG. 3 is a block diagram showing the configuration of a general image display device equipped with a bitmap memory.

In the figure, a CPU 1 writes image data directly to the bitmap memory through an address bus 2 and a data bus 3, and a CPU 4 sends predetermined parameter signals to a CRT controller (described later) and a drawing element (described later). A bitmap memory in which each bit corresponds to one dot on the screen, and a so-called R/W clock specifies a drawing cycle and a display cycle to continuously draw and display image data; 5 is a bitmap memory 4 in which the display cycle is 6 is a bitmap memory 4 which outputs a display address signal to address bus 2 when
A drawing element such as a graphic controller outputs image data to be drawn and its address signal, and numeral 7 indicates a CRT having a dot matrix corresponding to each bit of the pit map memory 4.

FIG. 4 is a time chart that does not show the operation cycle of each part of the image display device configured as shown in FIG.
) shows the clock of the drawing element 6, (b) shows the input/output data of the drawing element 6, and (C) shows the operation cycle of the bitmap memory 4. In (b), X is the drawing address signal, Y is the image data read from the bitmap memory 4, 2 is the modify data obtained by modifying the read image data, and W is the data input to the bitmap memory 4. Indicates writing.

In (C), the operation cycle of the bitmap memory 4 is divided into a display cycle P in which written image data is output to the CRT 7, and a drawing cycle Q in which the image data is modified and written.

By the way, when the drawing element 6 draws image data on the bitmap memory 4, it performs four steps: outputting a drawing address signal, reading already written image data, modifying the image data, and writing it. Action (b
1. : # Kel X -e Y -) Z -W), but conventional devices do
Since the display cycle P and the drawing cycle Q of the bitmap memory 4 are required twice for each time, there is a problem that the data processing speed is low.

[Object of the Invention] The present invention was made in view of the above-mentioned circumstances, and an object of the present invention is to provide a high-speed processing image display device that enables drawing of image data to a bitmap memory in each drawing cycle.

Summary of the Invention] In other words, the image display device of the present invention includes a bitmap memory in which a drawing cycle and a display cycle are specified by a predetermined instruction signal and image data is drawn and read, and an output signal to the bitmap memory. a drawing element that generates a drawing address signal to be drawn and also modifies image data in the bitmap memory; a read control element that outputs successive address signals to the bitmap memory; and a drawing cycle of the bitmap memory. while,
It has a logic element that outputs a drawing address signal output from the drawing element to an address bus of the bitmap memory, and a control element that controls each part, and the drawing address signal is output to the bitmap memory. The image forming apparatus is characterized in that the drawing element is configured to modify the image data in the bitmap memory in between.

[Embodiments of the Invention] Hereinafter, details of embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and parts common to those in FIG. 3 described above are given the same reference numerals.

In the figure, 1 is a CPU that directly writes data into the bitmap memory through an address bus 2 and a data bus 3, while also sending predetermined parameter signals to the CRT controller and drawing elements. 1
A bitmap memory corresponds to a dot and a drawing cycle and a display cycle are specified by a so-called R/W clock, and image data is continuously drawn and displayed. 5 is an address when the bitmap memory 4 enters a display cycle. A CRT controller outputs a display address signal to the bus 2; 6 is a drawing element such as a graphic controller 0-1 that outputs image data to be drawn to the bitmap memory 4 and its address signal; 7 is a drawing element such as a bitmap memory 4;
CR having a dot matrix corresponding to each bit of
It shows T.

8 is a gate that outputs the drawing address signal output from the drawing element 6 to the bitmap memory 4 when the bitmap memory 4 enters a drawing cycle; 9 is a CPU
3 shows a bus arbiter that switches and connects the address bus 2 and data bus 3 connected to the address bus 2 and the data bus 3 of the bitmap memory 4.

Next, the operation of the circuit shown in FIG. 1 will be explained based on the time chart shown in FIG.

In FIG. 2, (a) shows the clocks t1 and t of the drawing element 6.
2,..., (b) is the display address output from the CRT controller 5, (C) is the drawing address output from the drawing element 6, (d) is the address output from the gate 7, (e
) shows the input/output data of the drawing element 6, and (f) shows the operation cycle of the bitmap memory 4.

In (b), A is the display address, in (C), B is the drawing address, in (e), Y is the image data read from the bitmap memory 4, and 2 is the modified image data read out. The obtained modify data W indicates writing of data to the bitmap memory 4.

As shown in (f), the operation cycle of the bitmap memory 4 transfers the written image data to the CRT 7.
The display cycle P is divided into a display cycle P in which the image data is output, and a drawing cycle Q in which the image data is modified and written, and the drawing cycle Q is longer than the display cycle P.

The operation of the apparatus of this embodiment will be explained below.

First, when the operation cycle of the bitmap memory 4 reaches the display cycle P (FIG. 2f), the display address A is output from the CRT controller 5 onto the address bus 2 (FIG. 2b), and the display address A is output onto the CRT 7. Image data is displayed.

On the other hand, the drawing element 6 is activated at the same time as the display cycle P of the bitmap memory 4 starts, and outputs the drawing address B (FIG. 2C). This drawing address B is input to the gate 8, and when the display cycle P of the bitmap memory 4 ends and the drawing cycle Q starts, the address B
' on the address bus of the bitmap memory (FIG. 2d).

During the drawing cycle Q, the drawing element 6 transfers the image data at the address B' of the bitmap memory 4 to the clock t2.
It is read out at the timing of , modified at the timing of clock t3, and re-entered at the timing of clock t4 (corresponding to Y-4Z-4W in e).

However, in the device of this embodiment, graphic processing and image processing are performed by repeating the display cycle P1 and the drawing cycle Q in the bitmap memory 4, but the image data output from the drawing element is Since the data is written to the bitmap memory in cycles, it is possible to increase the speed of image processing. .

[Effects of the Invention] As explained above, the image display device of the present invention includes a bitmap memory in which a drawing cycle and a display cycle are designated by a predetermined instruction signal and image data is drawn and successively outputted, and this bitmap memory. a drawing element that generates a drawing address signal to be output to the memory and modifies image data in the bitmap memory; a read control element that outputs a read address signal to the bitmap memory;
While the bitmap memory is in a drawing cycle, it has a logical element that outputs the drawing address signal output from the drawing element to the address bus of the bitmap memory, and a control element that controls each part, and outputs the drawing address signal output from the drawing element to the address bus of the bitmap memory. Since the drawing element is configured to modify the image data in the bitmap memory while the image data is being output to the bitmap memory, image data can be written to the bitmap memory in one drawing cycle. , high-speed data processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart showing the operation cycle of each part in FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional image water surface device. , FIG. 4 is a time chart showing the operation cycle of each part of FIG. 3. 1... CPU 2... Address bus 3... Data bus 4... Bit map memory 5... CRT controller 6... ...Drawing element 7...CRT 8...Gate 9...Bus arbiter t...(Drawing element) clock A...
Display address B...Drawing address B'...Gate output data Y...Continuation data (of bitmap memory) Z...Modify data P... ...Display cycle Q...Drawing cycle Representative Patent Attorney Sasu Suyama - Figure 1 Figure 2

Claims (2)

[Claims] (1) A bitmap memory in which a drawing cycle and a display cycle are specified by a predetermined instruction signal to draw and read image data, and a bitmap memory that generates a drawing address signal to be output to this bitmap memory and the bitmap memory. A drawing element that modifies image data in a memory, a read control element that outputs a read address signal to the bitmap memory, and a drawing address signal that is output from the drawing element while the bitmap memory is in a drawing cycle. a logic element that outputs a signal to an address bus of the bitmap memory, and a control element that controls each part, and while the drawing address signal is being output to the bitmap memory, the drawing element controls the bitmap memory. An image display device configured to modify image data of. (2) The image display device according to claim 1, wherein the drawing cycle of the bitmap memory is longer than the display cycle.