JPH0927042A - Graphic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphic processor which can prevent the throughput of a host processor from decreasing while suppressing the complexity of the constitution. SOLUTION: This graphic processor is provided with an arithmetic circuit 32 which performs image processing operation according to image processing command information inputted from a data bus, and the arithmetic circuit 32 is enabled to read and write a texture buffer memory 5 which stores texture information for constituting part of a display image. Then the graphic processor is provided with a memory control circuit 33 which writes information on the data bus in the texture buffer memory 5 while discriminating the texture information from the command information and also sends the information written in the texture buffer 5 to the arithmetic circuit 32 while discriminating the texture information from the command information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is provided with an arithmetic circuit for performing an image processing operation based on image processing command information fetched from a data bus, and the arithmetic circuit constitutes a part of a display image. The present invention relates to a graphic processor configured to be readable and writable with respect to a texture buffer memory that stores texture information.

[0002]

2. Description of the Related Art Generally, such a graphic processor executes image processing commands such as drawing commands for various figures in place of the host processor when executing a series of image processing in cooperation with a so-called host processor. is there. Conventionally, as a form in which a graphic processor receives an image processing command, an auxiliary memory for storing the image processing command is provided for the graphic processor, or an auxiliary memory for storing the image processing command is provided in the main memory managed by the host processor. DM stored image processing commands in its auxiliary memory
A transfer is considered.

By the way, as one of the processes by the above-mentioned image processing command, for example, a pattern on the surface of an object is previously created as a two-dimensional image and stored as texture information, and the pattern is formed on the surface of the image of the three-dimensional object. There is a so-called texture mapping process in which a two-dimensional image is pasted. For such processing, a texture buffer memory for storing the above texture information has been conventionally provided, and the arithmetic circuit of the graphic processor is configured to be readable and writable with respect to this texture buffer memory. However, the exchange of information between the graphic processor and the texture buffer memory has nothing to do with the exchange of image processing commands described above.

[0004]

As in the above-mentioned conventional structure,
When the graphics processor receives an image processing command from the host processor, the host processor
Since the new image processing command is sent while monitoring the execution of the image processing command by the graphic processor, the host processor cannot execute other processing during that time, thus lowering the processing efficiency of the host processor. On the other hand, in the case of providing an auxiliary memory for storing the image processing command for the graphic processor and DMA-transferring the image processing command stored in the main memory managed by the host processor to the auxiliary memory, Since the image processing command can be sent regardless of the execution status of the image processing command of the graphic processor, it is possible to prevent the deterioration of the processing efficiency of the host processor as described above, but the configuration is complicated due to the provision of auxiliary memory. Turned into
There is an inconvenience that causes an increase in manufacturing cost. The present invention has been made in view of the above circumstances, and an object thereof is to prevent the processing efficiency of the host processor from decreasing while suppressing the complexity of the configuration.

[0005]

The graphic processor of the present invention is provided with an arithmetic circuit for performing an image processing operation on the basis of image processing command information fetched from a data bus, and the arithmetic circuit is a part of a display image. Is configured to be readable and writable with respect to a texture buffer memory that stores texture information for configuring
The characteristic configuration is such that information on the data bus is distinguished from the texture information and the command information,
Information written in the texture buffer memory and written in the texture buffer memory,
A point is that a memory control circuit for sending to the arithmetic circuit in a state where the texture information and the command information are distinguished is provided.

[0006]

According to the characterizing feature of the present invention, the image processing command executed by the graphic processor is temporarily stored in the texture buffer memory by the memory control circuit. By the memory control circuit, the command information and the texture information can be written in the texture buffer memory in a state where they are distinguished from each other, so that the command information and the texture information can be mixed in the texture buffer memory. Further, when the graphic processor executes the image processing command, the command information can be appropriately fetched from the texture buffer memory via the memory control circuit. That is, it is possible to send the image processing command regardless of the execution status of the image processing command by the graphic processor while using the texture buffer memory originally provided.

[0007]

According to the above characteristic structure, while utilizing the texture buffer memory originally provided,
Since the image processing command can be sent regardless of the execution status of the image processing command by the graphics processor, it is possible to prevent the processing efficiency of the host processor from decreasing while suppressing the complication of the configuration.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a three-dimensional graphics device to which a graphics processor of the present invention is applied will be described below with reference to the drawings. The three-dimensional graphics device TD is shown in FIG.
As shown in FIG. 3, a host processor 1 that controls the entire apparatus, a main memory that stores an operation program of a three-dimensional graphics apparatus TD including image processing command information (hereinafter, may be simply referred to as “command information”) 2. The graphic processor 3 that executes image processing command information of various commands stored in the main memory 2, the host processor 1 or the main memory 2 and the graphic processor 3 via the data bus DB and the address bus AB. Interface circuit 4 for connecting, texture buffer memory 5 for storing texture information which is information such as a two-dimensional image to be attached to the surface of an image of a three-dimensional object, frame buffer memory 6 for storing an image for display, hidden surface erasure Z buffer memory 7 for processing, graphic processor 3 D / A converter 8, D / A converter 8 for converting the digital image data generated into an analog signal is configured provided with a monitor 9 for displaying the image data converted into an analog signal.

The three-dimensional graphics device TD is provided with various input / output devices, storage devices, etc. in addition to the above, but they are not shown. As shown in FIG. 2, the graphic processor 3 includes a command switching circuit 30 that switches the input path of command information, a command input port 31 that temporarily holds the command information sent from the command switching circuit 30 in a FIFO format, and a command. An arithmetic circuit 32 that performs various image processing operations based on command information sent from the input port 31 and a memory control circuit that manages the flow of data when reading and writing command information and texture information from the texture buffer memory 5. D for transferring the command information sent from the memory control circuit 33 and the memory control circuit 33 to the command switching circuit 30 by DMA.
The MA controller 34 is provided and configured.

Next, the operation of the three-dimensional graphics device TD having the above structure will be briefly described. As a method of sending command information from the host processor 1 to the graphic processor 3, the host processor 1 directly writes the command information to the texture buffer memory 5, and the host processor 1 directly sends the command information to the command input port 31. There is a writing method, and it can be arbitrarily specified in consideration of the usage status of the texture buffer memory 5 and the like. A case in which the host processor 1 directly writes the command information in the texture buffer memory 5 will be described. First, the command information for drawing a desired three-dimensional graphic in the main memory 2 and the three-dimensional graphic Command information for processing such as shading and texture mapping is stored for
It is assumed that the texture information is already stored in the texture buffer memory 5. These command information can be input from various input means. From this state, the host processor 1 outputs the above command information stored in the main memory 2 to the data bus DB by designating the address of the texture buffer memory 5.
This command information is input to the memory control circuit 33 via the interface circuit 4.

The memory control circuit 33 writes the command information sent to the designated address. Then, the start address where the command information is written and the command length of the command information are stored in a register provided in the memory control circuit 33. Therefore, although the command information and the texture information are mixed in the texture buffer memory 5, they are written and read by the memory control circuit 33 in a state where they are distinguished. The command information stored in the texture buffer memory 5 is DMA-transferred to the command input port 31 via the command switching circuit 30 by the DMA controller 34 based on the record information in the register of the memory control circuit 33.

The command input port 31 has an arithmetic circuit 32.
Each time one arithmetic processing is completed, the command information is sequentially sent from the previously input command information to the arithmetic circuit 32.
The arithmetic circuit 32 sequentially arithmetically processes the command information received from the command input port 31, and reads the texture information of the texture buffer memory 5 as necessary. In this case, it is necessary to switch between sending information to the command input port 31 or sending information to the arithmetic circuit 32, and this processing is executed by the memory control circuit 33. When the method in which the host processor 1 directly writes the command information to the command input port 31 is adopted, the host processor 1 specifies the address of the command input port 31 to send the command information to the data bus D.
Output to B. The operation after the command input port 31 receives the command information is the same as when the host processor 1 directly writes the command information in the texture buffer memory 5.

[Other Embodiments] Other embodiments will be listed below. In the above embodiment, the command information is transferred from the main memory 2 to the texture buffer memory 5 by the host processor 1 reading the command information of the main memory 2 and outputting the read command information to the data bus DB. A configuration may be adopted in which DMA transfer is performed without going through the host processor 1. In the above-described embodiment, the memory control circuit 33 is provided with a register for distinguishing between the command information and the texture information mixed in the texture buffer memory 5, but it may be provided independently of the memory control circuit 33.

In the claims, reference numerals are provided for convenience of comparison with the drawings, but the present invention is not limited to the structure shown in the attached drawings.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram according to an embodiment to which a graphic processor of the present invention is applied.

FIG. 2 is a configuration diagram of a main part according to an embodiment of the present invention.

[Explanation of symbols]

 5 Texture buffer memory 32 Arithmetic circuit 33 Memory control circuit DB data bus

Claims (1)

[Claims] 1. An arithmetic circuit (32) for performing an image processing operation based on image processing command information fetched from a data bus (DB), the arithmetic circuit (32) constituting a part of a display image. A texture processor for storing texture information for storing the texture information, the graphics processor being readable and writable with respect to the information on the data bus (DB), and distinguishing the texture information from the command information. In this state, the information written in the texture buffer memory (5) and the information written in the texture buffer memory (5) are distinguished from the texture information and the command information, and the arithmetic circuit (32) A graphics processor provided with a memory control circuit (33) for sending to.