JP2001092778A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute processing by a processor during data input/output. SOLUTION: A processor 111 fetches the data from an input buffer memory 112, performs an arithmetic processing by a specified program and outputs the resultant data to an output buffer memory 113. Both of the input buffer memory 112 and the output buffer memory 113 have a double-buffer structure, each of them has areas A, B and holds input/output data for the processor 111. Reading, writing of the input buffer memory 112 and output buffer memory 113 are controlled by a DMA 114 according to the processing state of the processor 111 and the data input/output is performed even during the arithmetic processing of the processor 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital signal processing device for performing high-speed processing of a digital signal.

[0002]

2. Description of the Related Art Conventionally, a DSP (Digital Signal Processor) has been used for high-speed processing of digital signals. The DSP is a one-chip dedicated to digital signal processing.
The microprocessor has a circuit that performs high-speed processing of a predetermined calculation repetition.

However, since the conventional DSP has only one buffer memory, it cannot execute processing during data input or data output, and as shown in FIG. Data input, processing, and data output are performed sequentially. For this reason, it is desired that the processing can be executed even during data input and data output so as to shorten one processing unit time.

[0004]

As described above, in a conventional digital signal processing apparatus using a DSP, data input, processing, and data output are sequentially performed in one processing unit, and data input / output is performed during data input / output. So that processing can be performed,
It is desired to reduce the processing unit time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a digital signal processing apparatus in which a processor can execute processing during data input / output, thereby shortening one processing unit time. The purpose is to do.

[0006]

In order to achieve the above object, a digital signal processing apparatus according to the present invention has an input buffer memory having first and second areas each of which can alternately switch between reading and writing, and an output buffer memory. A buffer memory, a processor that reads data from a read-side area of the input buffer memory, performs arithmetic processing, and writes a result of the processing to a write-side area of the output buffer memory, and the input buffer memory according to a processing state of the processor. And a memory control circuit that controls reading and writing of the output buffer memory for each area, and writes input data to a writing side area of the input buffer memory during arithmetic processing of the processor. Reading and outputting data from an area

[0007] The processor, the input buffer memory, the output buffer memory, and the memory control circuit are formed on one chip.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 and 2,
An embodiment of the present invention will be described in detail.

FIG. 1 is a block diagram showing the configuration of a digital signal processing device using a DSP according to the present invention. In FIG. 1, reference numeral 11 denotes a DSP, which comprises a processor 111, an input buffer memory 112, an output buffer memory 113, and a DMA (Dynamic Memory Access) circuit 114. The processor 111 takes in data from the input buffer memory 112, performs arithmetic processing with a predetermined program, and outputs it to the output buffer memory 113. Each of the input buffer memory 112 and the output buffer memory 113 has a double buffer configuration, has areas A and B, respectively, and holds input / output data for the processor 111. The DMA 114 reads the input buffer memory 112 and the output buffer memory 113,
The writing is controlled in accordance with the processing status of the processor 111.

In the above configuration, a processing operation which is a feature of the present invention will be described below with reference to a processing time chart of each unit shown in FIG.

First, in the initial state, the processor 11
When a data processing request is issued to the processor 111, the processor 111
Issues a data input request to the DMA 114. At this time, the DMA 114 is stored in the area A of the input buffer memory 112.
Is written. As a result, the data D0 sent from the outside is written in the area A of the input buffer memory 112. DMA 114 is the input buffer memory 1
At the time when the data D0 is written to the area A of No. 12, the processor 111 notifies the processor 111 of the completion of the input data capture, and sets the area A of the input buffer memory 112 to the read state, the area B to the write state, and the output buffer memory 113.
Area A is in a write state.

When the processor 111 receives the input data fetch completion notification from the DMA 114, the processor 111 reads the data D0 from the area A of the input buffer memory 112, performs a predetermined arithmetic operation, and outputs the processing result to the area A of the output buffer memory 113. Write to. At this time, data D1 to be subjected to next arithmetic processing is written to the area B of the input buffer memory 112.

When the processing of the data D0 written in the area A of the input buffer memory 112 is completed, the processor 111 sends a data processing completion notification to the DMA 114. Upon receiving the data processing completion notification, the DMA 114 switches the area B of the input buffer memory 112 to the read state and the area A to the write state, and switches the area A of the output buffer memory 113 to the read state and the area B to the write state. Then, the completion of the area switching is notified to the processor 111.

When the processor 111 receives the area switching completion notification from the DMA 114, the processor 111
The data D1 is read out from the area B, a predetermined arithmetic processing is performed, and the processing result is written to the area B of the output buffer memory 113. During this time, the input buffer memory 11
Then, data D2 to be subjected to the next arithmetic processing is written in the area A of No. 2 and the processed data is read out and output from the area A of the output buffer memory 113. Thereafter, the same processing is repeatedly performed, and the processor 111 continuously executes the arithmetic processing without waiting for input / output of data.

Therefore, in the digital signal processing device having the above configuration, the input buffer memory 112 and the output buffer memory 113 using a double buffer are controlled by the DMA 114 in accordance with the processing of the processor 111. Input and output become possible, whereby the processor 111 can continuously execute arithmetic processing, and the unit time of one processing can be reduced.

[0016]

As described above, according to the present invention, it is possible to provide a digital signal processing apparatus in which a processor can execute processing while data is being input / output, thereby shortening one processing unit time. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device using a DSP according to an embodiment of the present invention.

FIG. 2 is a time chart showing a processing period of each unit in the embodiment.

FIG. 3 is a time chart showing a processing period of each unit of a digital signal processing device using a conventional DSP.

[Explanation of symbols]

 11 DSP 111 Processor 112 Input buffer memory 113 Output buffer memory 114 DMA

Claims (2)

[Claims] 1. An input buffer memory and an output buffer memory having first and second areas each of which can alternately switch between reading and writing, reading data from a reading side area of the input buffer memory, and performing arithmetic processing; A processor that writes the processing result to a write-side area of the output buffer memory; and a memory control circuit that controls reading and writing of the input buffer memory and the output buffer memory for each area according to the processing status of the processor. A digital signal processing device for writing input data to a write-side area of the input buffer memory during arithmetic processing of the processor, and reading and outputting data from a read-side area of the output buffer memory. 2. The digital signal processing device according to claim 1, wherein said processor, input buffer memory, output buffer memory, and memory control circuit are formed on one chip.