JP2000148574A - Device and method for register control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to store data outputted by external equipment in the internal memory of a signal processing circuit (DSP) and to input and output data to be processed at a high speed with simple constitution by storing the data outputted by the external equipment and outputting the data to the DSP. SOLUTION: When the DSP 200 writes data to a RAM 210, a DPS write address decoder 313 of the register control unit 310 writes the same data to a register 314 as well. When the data is written to a host CPU LSI, the write address decoder 311 writes a data signal 151a to a selected register 312 with a register write request signal 321. When the address of an address signal 201 indicates the data stored in the register 312 when the DSP 200 executes a program, the DSP 200 uses data that a DSP readout selecting circuit 340 outputs to a RAM data output selecting circuit 220.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a register control device and a register control method, and more particularly to a DSP (Dig).
It relates to a register control device and a register control method suitable for use in an italian signal processor.

[0002]

2. Description of the Related Art Conventionally, as a register control device of this kind, a device as shown in FIG. 5 has been known. In FIG. 5, a host CPU 910 controls the entire processing performed by using the DSP 940, such as image processing and creation of reverberation sound in audio. The LSI 950 includes a logic circuit 930 and a DSP 940, and the logic circuit 930 further includes a host I / F 9
The DSP 940 includes a RAM 941, and the RAM 941 can hold data in units of 1 bit.

The host CPU 910 is provided with a host I / F 9
20 and an address signal 912, a register read request signal 913, a register write request signal 9
14 is output to the host I / F 920. Further, the host CPU 910 is connected to the host bus 96
0 is connected to the host I / F 920, and data signals 924 and the like are exchanged.

The host I / F 920 is connected to the DSP 940, so that the interrupt request signal 921 and the write data 922 are output from the host I / F 920 to the DSP 940, and the read data 923 is output from the DSP 940 to the host I / F 920. Has become. Also,
The DSP 940 includes a RAM 941.

In the above configuration, for example, RA
An operation of acquiring data to be written to the M941 from outside the LSI 950 will be described. FIG.
1 shows a DSP clock when writing data to the CPU 1, processing contents performed by the DSP, a register write request signal 914, an interrupt request signal 921, and a timing chart of writing to the RAM. In the figure, the DSP clock emits a pulse at a predetermined clock frequency.
The SP normally performs the processing of the main routine.

At the time of writing, the host CPU 910 outputs an address signal 912, a data signal 924, and a register write request signal 914 to the host I / F 920. That is, a pulse is generated in the register write request signal 914 at a certain time as shown in FIG. Host I / F92
When 0 acquires this signal, an interrupt request signal 921 is output to the DSP 940.

When the DSP 940 detects the interrupt request signal 921, the processing of the DSP 940 shifts from the main routine to the interrupt routine. In this interrupt routine, the address signal 9 is sent to the RAM 941.
The data indicated by the data signal 924 is written to the address specified by 12. After this, the DSP 940 returns to the main routine.

In general, a DSP is used for performing a high-speed operation by digitally processing an analog signal. Therefore, it is important that the processing speed is high. Therefore, in the technology disclosed in Japanese Patent Application Laid-Open No. 62-168255, in order to speed up data transfer between a plurality of connected DSPs, a port that can be used for both input and output is provided. And the port is internally generated pulse,
It is configured to be operable with any external input pulse.

[0009]

The conventional register control device and register control method described above have the following problems. Several to several tens of clocks elapse between the time when the host CPU 910 issues a write request and the time when the writing to the RAM of the DSP is actually performed.
Therefore, when controlling the DSP 940 from the host CPU 910, it is necessary to wait a predetermined time. Accordingly, the control of the DSP 940 from the host CPU 910 is delayed from the logic circuit 930 other than the DSP 940 by the predetermined time.

Further, the period from when the interrupt routine of the DSP 940 is accepted depends on the state of the program processing, so that the period from the write request of the host CPU 910 to the actual writing is not constant. Therefore, the timing relationship between the DSP 940 included in the LSI 950 and the register of the logic circuit 930 is not kept constant, and control from the host CPU 910 is extremely difficult.

In the technique disclosed in Japanese Patent Application Laid-Open No. 62-168255, although the data transfer speed is increased, the period from the write request to the actual write is not constant. Did not.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has a register capable of inputting / outputting data to be processed with a simple configuration at a high speed and easily controlling a signal processing circuit such as a DSP. A control device and a register control method are provided.

[0013]

In order to achieve the above object, according to the first aspect of the present invention, a signal processing circuit having a built-in memory is interposed between an external device accessing the signal processing circuit. A register control device, wherein a first data storage means for acquiring a write request signal, data, and an address thereof from the external device and storing the acquired data as data of the address; A second data storage means for acquiring a write request signal, data and its address issued when writing data, and storing the same data as the content to be written in the internal memory, and using the read request signal from the external device When the address of the data to be obtained is obtained and the address indicates data from the external device, the data of the address is stored in the first data storage unit. A first data output means for selecting the data of the address from the second data storage means and outputting the selected data to the external device when the acquired address indicates data in the internal memory of the signal processing circuit; Obtains the address of the data to be used, and when the address is that of the data output by the external device, selects the data of the address stored in the first storage means, and selects the signal processing circuit. Output for use by the second data output means for enabling the data output from the external device to be used in the signal processing circuit without storing the data output from the external device in the internal memory. Is provided.

That is, when the first data storage means obtains a write request signal, data, and its address from an external device, the first data storage means stores the data in association with the address. Further, the second data storage means obtains a write request signal, data and its address, which are issued when the signal processing circuit writes data to the built-in memory,
This data is stored while being associated with this address.

The first data output means acquires a read request signal from an external device and an address of data to be used, and when the address indicates data from the external device, the data of the address is read from the first data storage means. Select and output to an external device. On the other hand, when the acquired address indicates data in the internal memory of the signal processing circuit, the data at that address is selected from the second data storage means and output to the external device.

The second data output means obtains an address of data used by the signal processing circuit, and when the address is that of data output by the external device,
The data at the address stored in the first storage means is selected and output so as to be used by the signal processing circuit.
That is, since the data from the external device is not stored in the memory of the signal processing circuit, when the signal processing circuit uses the data from the external device, the data is obtained from the first storage unit and used. On the other hand, when the data to be used is not from the external device but is stored in the memory of the signal processing circuit, the signal processing circuit directly accesses the memory and uses the data.

Here, the signal processing circuit having a built-in memory only needs to be able to perform signal processing for a predetermined purpose, and is constituted by, for example, a DSP which is a digital signal processing circuit. An external device that accesses the signal processing circuit is a device that outputs a signal to the signal processing circuit and receives an output from the signal processing circuit in the entire system configured using the register control device. That is, for example, it may be a CPU that controls a signal processing circuit or a device that is connected via a bus.

The write request signal from external equipment, data and its address are data necessary for performing image conversion processing in a system using this signal processing circuit. Therefore, the write request signal and the data address may be obtained from the host CPU, and the data may be obtained from the bus.

A write request signal, data and its address, which are issued when the signal processing circuit writes data to the built-in memory, are used by the signal processing circuit during image conversion processing in a system using this signal processing circuit. This is the data to be written to the memory in the processing circuit. Therefore, the write request signal, the data, and the address of the write request signal issued to the memory by the signal processing circuit are also acquired in the second data storage means.

As described above, the first storage means stores data from the external device, and the second storage means also stores data to be written to the memory by the signal processing circuit. It is stored in one storage means or the second storage means. That is,
Since the data from the external device is stored in the first storage means without writing to the memory of the signal processing circuit, there is no need to stop the main routine of the signal processing circuit and enter the interrupt routine.

Also, data necessary for reading is stored in the first storage means or the second storage means, and is output by the first data output means. Therefore, it is necessary to enter an interrupt routine of the memory of the signal processing circuit. Absent. Further, since the data required in the signal processing circuit is also stored in the first storage means or the memory of the signal processing circuit, the data required by the signal processing circuit is output from the memory or the data output by the second data output means. To get.

The storage means may be any one capable of writing and reading data. As a specific example, the invention according to claim 2 is the register control device according to claim 1, wherein the first storage means The configuration includes a plurality of flip-flop circuits as registers for storing data. That is, since a flip-flop circuit that is used very often is configured as a register for storing data, it is easy to incorporate a storable circuit into a logic circuit.

According to a third aspect of the present invention, as a specific example of a preferred configuration in which a flip-flop circuit is used as the storage means, the first storage means includes a write request signal. When receiving the data and the address of the storage data, these signals are decoded into a write enable signal, and the write enable signal is output to the flip-flop circuit corresponding to the designated address.

That is, in general, the flip-flop circuit controls the input / output of data contents to the flip-flop circuit by the write enable signal. Therefore, the write request signal and the address of the storage data are decoded, and the write enable signal is supplied to the flip-flop circuit uniquely determined from the designated data address.

Similarly, as a specific example of the configuration of the second storage means, the invention according to claim 4 is the register control device according to any one of claims 1 to 3, wherein the second storage means stores Is provided with a plurality of flip-flop circuits as registers for storing. That is, since the flip-flop circuit is also configured as a register for storing data in the second storage means, it is easy to incorporate a storable circuit into the logic circuit.

Further, as a specific example of a preferable configuration when a flip-flop circuit is used also in the second storage means, the invention according to claim 5 is the register control device according to claim 4, wherein Is configured to receive a write request signal and an address of storage data, decode these signals into a write enable signal, and output the write enable signal to a flip-flop circuit corresponding to the specified address. That is, also in the second storage means, the write request signal and the address of the storage data are decoded, and the write enable signal is given to the flip-flop circuit uniquely determined from the designated data address.

As described above, when writing data input from an external device or when outputting the storage contents of the memory of the signal processing circuit to the external device, the main routine of the signal processing circuit is interrupted to perform the storage processing on the memory. It is not necessary that the method of eliminating the above is necessarily limited to the device as described above. As an example, the invention according to claim 6
A register control method for controlling input / output of data between a signal processing circuit having a built-in memory and an external device accessing the signal processing circuit, wherein a write request signal, data, and an address thereof are transmitted from the external device. Obtain and obtain a write request signal, data and its address, which are issued when the signal processing circuit writes data to the built-in memory, and store the necessary data as data of each address to obtain the necessary data. The data is held in a memory other than the built-in memory of the processing circuit, and a read request signal and an address of data to be used are obtained from an external device. When the acquired address indicates data in the internal memory of the signal processing circuit, the second data storage means Select the data at that address and output it to the external device, and also obtain the address of the data used by the signal processing circuit, and if this address is that of the data output by the external device, Selecting the data of the address stored in the first storage means,
A configuration in which the signal output from the external device can be used in the signal processing circuit without storing the data output from the external device in the internal memory by outputting the signal for use by the signal processing circuit. There is. That is, the present invention is not necessarily limited to the form of the apparatus, and is effective as a method.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing a system using a register control device according to an embodiment of the present invention. In the figure, the host CPU 11
Numeral 0 is for controlling the entire processing performed using the DSP 200, such as image processing and creation of reverberation sound in audio. The LSI 100 includes a logic circuit 300 and a DSP 200. The logic circuit 300 further includes a register control device 310,
200 has a RAM 210.

The host CPU 110 is connected to a register controller 310, and outputs an address signal 111, a register read request signal 112, and a register write request signal 113 to the register controller 310. Further, the host CPU 110 is connected to the register control device 310 via the host bus 150, and exchanges data signals 151 and the like.

The register control device 310 is connected to the DSP 200, and the write control signal 203 from the DSP 200 to the RAM 210, the data signal 202 of the data to be stored, and the address signal 201 are transmitted to the register control device 3.
10, and the read data 204 is output from the register control device 310 to the DSP 200.

FIG. 2 is a block diagram of the register control device 310 according to one embodiment of the present invention, and a block diagram showing a part of the DSP 200. In the figure, the data signal 151 in FIG. 1 is input to the register control device 310 by the input data signal 151a, the register control device 3
The output from 10 is an output data signal 151b.

The register control device 310 is an LSI 100
A write address decoder 311 and a plurality of registers 312 are provided for storing external data. A register write request signal 113 and an address signal 111 are input to the write address decoder 311, an output destination is uniquely determined from the plurality of registers 312 by the address signal 111, and a register write enable signal 321 is output.

Each of the plurality of registers 312 is constituted by a flip-flop circuit, and receives the register write enable signal 321 and the input data signal 151a. Then, the input data is stored in the register to which the register write enable signal 321 has been input. In this sense, the write address decoder 311 and the register 312 constitute the first data storage means.

In this embodiment, a part of the storage capacity of the RAM 210 is used as a register area as shown in FIG. When the DSP 200 writes data in the register area of the RAM 210, the data is stored in the register control device 310.
An SP write address decoder 313 and a plurality of registers 314 are provided. The RAM write request signal 203 and the address signal 201 are input to the DSP write address decoder 313, the output destination is uniquely determined from the plurality of registers 314 by the address signal 201, and the register write enable signal 322 is output. .

Each of the plurality of registers 314 is constituted by a flip-flop circuit, and receives the register write enable signal 322 and the RAM data signal 202. Then, the RAM data is stored in the register 314 to which the register write enable signal 322 has been input. In this sense, the DSP write address decoder 313 and the register 314 constitute the second data storage means.

Further, the register control means 310 includes a host read select circuit 330 and a DSP read select circuit 340 for outputting the stored data. The register read request signal 112 is input to the host read selection circuit 330, and the register 312 and the register 314 are connected. A register corresponding to the register read request signal 112 is selected from these registers, and the register is selected. The contents are output to an external device as output data 151b. In this sense,
The host read selection circuit 330 constitutes the first data output means.

An address signal 201 is input to the DSP read selection circuit 340, and a register 312 is connected to the DSP read selection circuit 340. When the address specified by the address signal 201 is that of the data stored in the register 312, the register is selected and the data content is stored in the RAM 312.
The data is output to the data output selection circuit 220 as read data 204. The RAM data output selection circuit 220 receives data 211, read data 204, and an address signal 201 from the RAM, and outputs necessary data as a data out signal. In this sense, the DSP read selection circuit 340 constitutes the second data output means.

In the above configuration, the DSP 200
When writing data to the register area of the RAM 210, the DSP write address decoder 313
200, the write request signal 203 and the address signal 20
1 is obtained. Then, the same data is written into the register 314 inside the register control device 310 in parallel with the data being stored in the RAM 210. Host CPU
When the 110 writes to the LSI 100,
A desired address and data are output as the address signal 111 and the data signal 151a, and a register write request signal 113 is output.

The write address decoder 311 outputs the address signal 111 and the register write request signal 11
And 3 are obtained. Then, one of the registers 312 is selected according to the contents of the address signal 111, and the data signal 151a is written to the selected register by the register write request signal 321. FIG. 4 shows a timing chart of the DSP clock, the processing performed by the DSP, the register write request signal 113, and the writing to the RAM 210 at the time of this writing.

In the figure, the DSP 200 generates a continuous clock at a predetermined cycle, and performs a main routine process. Here, even if the register write request signal 113 is issued at a certain time, the main routine of the DSP is not interrupted and the interrupt routine is started as in the above-described conventional example. Is actually written to the register 312. By the above operation, all the contents written to the registers from the DSP 200 and the host CPU 110 are stored in the register 312 or the register 314 in the register control device 310.

The host CPU 110 operates in the register controller 3
When reading data stored in the ten registers, a desired address is output as the address signal 111 and a register read request signal 112 is output. The host read selection circuit 330 stores the requested address in the register 3
12 or the register 314, and one of them is selected and output to the host CPU 110.

When the DSP 200 uses the data written in the register of the register control device 310 when executing the program, the DSP 200 refers to the data in the register 312 or the register area of the RAM 210. The selection of the register is performed according to the contents of the address signal 201. That is,
If the address is that of the data stored in the register 312, the DSP 200
40 uses the data output to the RAM data output selection circuit 220. On the other hand, if the address of the address signal 201 is that of the data stored in the RAM 210, DS
P200 indicates that the RAM 210 is the RAM data output selection circuit 2
20 is used.

As described above, according to the register control device and the register control method, the write request signal, the data to be stored and the address thereof are received from the external device such as the CPU, and the write request signal to the RAM of the DSP and the data to be stored are received. And that address, and hold the data at the specified address when a write request is made. When receiving the read request signal from the external device and the address of the data to be output, it selects the data to be output from the data held according to the read signal and outputs it to the external device.

When the address of the data used by the DSP is received, if the address is that of data written from an external device, the data is selected and the DS is selected.
Output to P. Therefore, the data from the external device
Since there is no need to write data in the RAM inside the DSP, the main routine of the DSP is not interrupted, and data to be processed can be input / output at a high speed with a simple configuration. Further, since the time until the actual writing is constant, a register control device and a register control method capable of easily controlling a signal processing circuit such as a DSP can be provided.

[0045]

As described above, according to the present invention, there is no need to write data from an external device to the RAM in the DSP, so that the main routine of the DSP is not interrupted.
Data to be processed can be input and output at a high speed with a simple configuration. Further, since the time until the actual writing is constant, a register control device capable of easily controlling a signal processing circuit such as a DSP can be provided. According to the second aspect of the present invention, a storage circuit can be easily configured. Further, according to the third aspect of the present invention, the storage circuit can be controlled with a simple configuration. Further, according to the invention according to claim 4, a storage circuit can be easily configured. further,
According to the invention according to claim 5, the storage circuit can be controlled with a simple configuration. Further, according to the present invention, there is provided a register control method capable of inputting / outputting data to be processed with a simple configuration at a high speed and easily controlling a signal processing circuit such as a DSP. can do.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a system using a register control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a register control device and a part of a DSP according to an embodiment of the present invention.

FIG. 3 is a diagram showing a storage area of a RAM included in a DSP using the register control device according to the embodiment of the present invention.

FIG. 4 is a timing chart of a system using the register control device according to one embodiment of the present invention.

FIG. 5 is a schematic block diagram of a system using a register control device according to the related art.

FIG. 6 is a timing chart of a system using a register control device according to the related art.

[Explanation of symbols]

 100 LSI 110 Host CPU 150 Host bus 151 Data signal 200 DSP 210 RAM 220 RAM data output selection circuit 300 Logic circuit 310 Register controller 311 Write address decoder 312 Register 313 DSP Write address decoder 314 Register 330 Read selection circuit 340 DSP read selection circuit

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[Procedure amendment]

[Submission date] January 13, 1999 (1999.1.1)
3)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

Claims (6)

[Claims] 1. A register control device interposed between a signal processing circuit having a built-in memory and an external device accessing the signal processing circuit, comprising: a write request signal, data, and an address thereof from the external device. And the first data storage means for storing the data as the data of this address, and the signal processing circuit obtains a write request signal, data and its address which are issued when writing data to the built-in memory, A second data storage unit for storing the same data as the content to be written to the internal memory; a read request signal from the external device; and an address of data to be used, and the address indicates data from the external device. Sometimes, the data at that address is selected from the first data storage means, and the obtained address is stored in the data in the internal memory of the signal processing circuit. When indicating the data, the first data output means for selecting the data of the address from the second data storage means and outputting the selected data to the external device, and the address of the data used by the signal processing circuit are obtained. When the data is output from an external device, the data at the address stored in the first storage unit is selected and output so that the signal processing circuit uses the data. A register control device comprising: a second data output unit that enables the data output from the external device to be used in the signal processing circuit without storing the data output from the external device. 2. The register control device according to claim 1, wherein said first storage means includes a plurality of flip-flop circuits as registers for storing data. 3. The register control device according to claim 2, wherein the first storage means, upon receiving the write request signal and the address of the storage data, decodes these signals into a write enable signal and is designated. A register control device for outputting a write enable signal to a flip-flop circuit corresponding to an address. 4. The register control device according to claim 1, wherein said second storage means includes a plurality of flip-flop circuits as registers for storing data. Register control device. 5. The register control device according to claim 4, wherein the second storage means, upon receiving the write request signal and the address of the storage data, decodes these signals into a write enable signal and is designated. A register control device for outputting a write enable signal to a flip-flop circuit corresponding to an address. 6. A register control method for controlling input / output of data between a signal processing circuit having a built-in memory and an external device accessing the signal processing circuit, comprising: And its address, and obtains a write request signal, data, and its address that are generated when the signal processing circuit writes data to the built-in memory, and stores them as data of each address. Data is stored in a memory other than the built-in memory of the signal processing circuit, and a read request signal and an address of data to be used are obtained from an external device. When the address indicates data from the external device, the address is obtained from the first data storage unit. Select the address data,
When the obtained address indicates data in the internal memory of the signal processing circuit, the data of the address is selected from the second data storage means and output to the external device, and the address of the data used by the signal processing circuit is obtained. Then, when the address is that of the data output by the external device, the data of the address stored in the first storage means is selected and output so that the signal processing circuit uses the data. A method of controlling a register, wherein data output from an external device can be used in the signal processing circuit without storing data output from the external device in the internal memory.